CN100437939C - 形成具有金属的栅电极的方法 - Google Patents
形成具有金属的栅电极的方法 Download PDFInfo
- Publication number
- CN100437939C CN100437939C CNB2005800116539A CN200580011653A CN100437939C CN 100437939 C CN100437939 C CN 100437939C CN B2005800116539 A CNB2005800116539 A CN B2005800116539A CN 200580011653 A CN200580011653 A CN 200580011653A CN 100437939 C CN100437939 C CN 100437939C
- Authority
- CN
- China
- Prior art keywords
- metal layer
- region
- layer
- gate dielectric
- gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
- H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
- H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
- H10D84/85—Complementary IGFETs, e.g. CMOS
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y30/00—Nanotechnology for materials or surface science, e.g. nanocomposites
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/04—Coating on selected surface areas, e.g. using masks
- C23C16/042—Coating on selected surface areas, e.g. using masks using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28079—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a single metal, e.g. Ta, W, Mo, Al
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/60—Electrodes characterised by their materials
- H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
- H10D64/665—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of elemental metal contacting the insulator, e.g. tungsten or molybdenum
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/60—Electrodes characterised by their materials
- H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
- H10D64/665—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of elemental metal contacting the insulator, e.g. tungsten or molybdenum
- H10D64/666—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of elemental metal contacting the insulator, e.g. tungsten or molybdenum the conductor further comprising additional layers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
- H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
- H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
- H10D84/0172—Manufacturing their gate conductors
- H10D84/0177—Manufacturing their gate conductors the gate conductors having different materials or different implants
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/02—Manufacture or treatment characterised by using material-based technologies
- H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
- H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/601—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs
Landscapes
- Chemical & Material Sciences (AREA)
- Engineering & Computer Science (AREA)
- Nanotechnology (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Crystallography & Structural Chemistry (AREA)
- Materials Engineering (AREA)
- Computer Hardware Design (AREA)
- Mechanical Engineering (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- General Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Composite Materials (AREA)
- Metallurgy (AREA)
- Organic Chemistry (AREA)
- Mathematical Physics (AREA)
- Theoretical Computer Science (AREA)
- Electrodes Of Semiconductors (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Thin Film Transistor (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US10/827,202 US7030001B2 (en) | 2004-04-19 | 2004-04-19 | Method for forming a gate electrode having a metal |
| US10/827,202 | 2004-04-19 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1947230A CN1947230A (zh) | 2007-04-11 |
| CN100437939C true CN100437939C (zh) | 2008-11-26 |
Family
ID=35096814
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2005800116539A Expired - Fee Related CN100437939C (zh) | 2004-04-19 | 2005-03-22 | 形成具有金属的栅电极的方法 |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US7030001B2 (enExample) |
| EP (1) | EP1776715B1 (enExample) |
| JP (1) | JP4757867B2 (enExample) |
| KR (1) | KR20070014152A (enExample) |
| CN (1) | CN100437939C (enExample) |
| WO (1) | WO2005106938A1 (enExample) |
Families Citing this family (35)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4040602B2 (ja) * | 2004-05-14 | 2008-01-30 | Necエレクトロニクス株式会社 | 半導体装置 |
| US20060011949A1 (en) * | 2004-07-18 | 2006-01-19 | Chih-Wei Yang | Metal-gate cmos device and fabrication method of making same |
| JP2006156807A (ja) * | 2004-11-30 | 2006-06-15 | Toshiba Corp | 半導体装置およびその製造方法 |
| JP4764030B2 (ja) * | 2005-03-03 | 2011-08-31 | 株式会社東芝 | 半導体装置及びその製造方法 |
| KR100639073B1 (ko) * | 2005-05-10 | 2006-10-30 | 한국과학기술원 | 선택적 다마신을 이용한 반도체 금속 배선의 형성방법 |
| US7871933B2 (en) * | 2005-12-01 | 2011-01-18 | International Business Machines Corporation | Combined stepper and deposition tool |
| JP4557879B2 (ja) * | 2005-12-09 | 2010-10-06 | 株式会社東芝 | 半導体装置及びその製造方法 |
| US7432567B2 (en) | 2005-12-28 | 2008-10-07 | International Business Machines Corporation | Metal gate CMOS with at least a single gate metal and dual gate dielectrics |
| US7579282B2 (en) * | 2006-01-13 | 2009-08-25 | Freescale Semiconductor, Inc. | Method for removing metal foot during high-k dielectric/metal gate etching |
| US7445976B2 (en) * | 2006-05-26 | 2008-11-04 | Freescale Semiconductor, Inc. | Method of forming a semiconductor device having an interlayer and structure therefor |
| US7671421B2 (en) | 2006-05-31 | 2010-03-02 | International Business Machines Corporation | CMOS structure and method for fabrication thereof using multiple crystallographic orientations and gate materials |
| KR100844954B1 (ko) | 2006-12-27 | 2008-07-09 | 주식회사 하이닉스반도체 | 반도체 소자의 트랜지스터 형성방법 |
| KR100843230B1 (ko) * | 2007-01-17 | 2008-07-02 | 삼성전자주식회사 | 금속층을 가지는 게이트 전극을 구비한 반도체 소자 및 그제조 방법 |
| KR100903383B1 (ko) * | 2007-07-31 | 2009-06-23 | 주식회사 하이닉스반도체 | 일함수가 조절된 게이트전극을 구비한 트랜지스터 및 그를구비하는 메모리소자 |
| US8030212B2 (en) * | 2007-09-26 | 2011-10-04 | Eastman Kodak Company | Process for selective area deposition of inorganic materials |
| GB0718841D0 (en) * | 2007-09-26 | 2007-11-07 | Eastman Kodak Co | Method of making a colour filter array |
| KR101589440B1 (ko) * | 2009-02-09 | 2016-01-29 | 삼성전자주식회사 | 듀얼 게이트 반도체 장치의 제조 방법 |
| US8153529B2 (en) * | 2009-11-20 | 2012-04-10 | Eastman Kodak Company | Method for selective deposition and devices |
| US8318249B2 (en) * | 2009-11-20 | 2012-11-27 | Eastman Kodak Company | Method for selective deposition and devices |
| US8168546B2 (en) * | 2009-11-20 | 2012-05-01 | Eastman Kodak Company | Method for selective deposition and devices |
| US20110120544A1 (en) * | 2009-11-20 | 2011-05-26 | Levy David H | Deposition inhibitor composition and method of use |
| US20110120543A1 (en) * | 2009-11-20 | 2011-05-26 | Levy David H | Method for selective deposition and devices |
| US7998878B2 (en) * | 2009-11-20 | 2011-08-16 | Eastman Kodak Company | Method for selective deposition and devices |
| US9177870B2 (en) * | 2011-12-16 | 2015-11-03 | Taiwan Semiconductor Manufacturing Company Ltd. | Enhanced gate replacement process for high-K metal gate technology |
| US8786018B2 (en) * | 2012-09-11 | 2014-07-22 | International Business Machines Corporation | Self-aligned carbon nanostructure field effect transistors using selective dielectric deposition |
| US10103057B2 (en) | 2014-11-11 | 2018-10-16 | The Board Of Trustees Of The University Of Illinois | Use of an inhibitor molecule in chemical vapor deposition to afford deposition of copper on a metal substrate with no deposition on adjacent SIO2 substrate |
| KR101747264B1 (ko) | 2015-11-30 | 2017-06-15 | 엘지디스플레이 주식회사 | 표시 장치와 그의 제조 방법 |
| US11584986B1 (en) | 2017-11-01 | 2023-02-21 | The Board Of Trustees Of The University Of Illinois | Area selective CVD of metallic films using precursor gases and inhibitors |
| JP7101551B2 (ja) | 2018-07-02 | 2022-07-15 | 東京エレクトロン株式会社 | 選択的に対象膜を形成する方法およびシステム |
| JP7109397B2 (ja) | 2019-03-13 | 2022-07-29 | 東京エレクトロン株式会社 | 成膜方法 |
| JP2021044534A (ja) | 2019-09-05 | 2021-03-18 | 東京エレクトロン株式会社 | 成膜方法 |
| JP7353200B2 (ja) | 2020-02-06 | 2023-09-29 | 東京エレクトロン株式会社 | 成膜方法 |
| JP2022091523A (ja) | 2020-12-09 | 2022-06-21 | 東京エレクトロン株式会社 | 成膜方法 |
| JP2022137698A (ja) | 2021-03-09 | 2022-09-22 | 東京エレクトロン株式会社 | 成膜方法および成膜システム |
| WO2022203222A1 (ko) * | 2021-03-26 | 2022-09-29 | 주식회사 랩토 | 핵생성 억제 형성용 물질 및 이를 포함하는 유기전계발광소자 |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5959337A (en) * | 1997-12-08 | 1999-09-28 | Advanced Micro Devices, Inc. | Air gap spacer formation for high performance MOSFETs |
| CN1243336A (zh) * | 1998-06-30 | 2000-02-02 | 摩托罗拉公司 | 互补金属氧化物半导体器件及其形成方法 |
| CN1096705C (zh) * | 1997-08-22 | 2002-12-18 | 日本电气株式会社 | 半导体装置的制造方法 |
| US6686282B1 (en) * | 2003-03-31 | 2004-02-03 | Motorola, Inc. | Plated metal transistor gate and method of formation |
| US6867441B1 (en) * | 2003-10-08 | 2005-03-15 | Taiwan Semiconductor Manufacturing Co., Ltd. | Metal fuse structure for saving layout area |
Family Cites Families (22)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0644631B2 (ja) * | 1987-05-29 | 1994-06-08 | 株式会社東芝 | 半導体装置及びその製造方法 |
| US5358743A (en) * | 1992-11-24 | 1994-10-25 | University Of New Mexico | Selective and blanket chemical vapor deposition of Cu from (β-diketonate)Cu(L)n by silica surface modification |
| US5725788A (en) * | 1996-03-04 | 1998-03-10 | Motorola | Apparatus and method for patterning a surface |
| US5869135A (en) * | 1997-10-03 | 1999-02-09 | Massachusetts Institute Of Technology | Selective chemical vapor deposition of polymers |
| US5937758A (en) * | 1997-11-26 | 1999-08-17 | Motorola, Inc. | Micro-contact printing stamp |
| KR100257583B1 (ko) * | 1997-12-17 | 2000-06-01 | 윤종용 | 경계 영역의 도전층 형성을 방지하는 반도체 메모리 장치의 게이트 형성 방법 |
| US6444512B1 (en) * | 2000-06-12 | 2002-09-03 | Motorola, Inc. | Dual metal gate transistors for CMOS process |
| US6605534B1 (en) * | 2000-06-28 | 2003-08-12 | International Business Machines Corporation | Selective deposition of a conductive material |
| KR100399356B1 (ko) * | 2001-04-11 | 2003-09-26 | 삼성전자주식회사 | 듀얼 게이트를 가지는 씨모스형 반도체 장치 형성 방법 |
| US6872627B2 (en) * | 2001-07-16 | 2005-03-29 | Taiwan Semiconductor Manufacturing Company | Selective formation of metal gate for dual gate oxide application |
| KR100426441B1 (ko) * | 2001-11-01 | 2004-04-14 | 주식회사 하이닉스반도체 | 반도체 소자의 시모스(cmos) 및 그의 제조 방법 |
| US6809026B2 (en) * | 2001-12-21 | 2004-10-26 | Applied Materials, Inc. | Selective deposition of a barrier layer on a metal film |
| US6828205B2 (en) * | 2002-02-07 | 2004-12-07 | Taiwan Semiconductor Manufacturing Co., Ltd | Method using wet etching to trim a critical dimension |
| US20030148618A1 (en) | 2002-02-07 | 2003-08-07 | Applied Materials, Inc. | Selective metal passivated copper interconnect with zero etch stops |
| US6828581B2 (en) * | 2002-02-26 | 2004-12-07 | The United States Of America As Represented By The Secretary Of Commerce | Selective electroless attachment of contacts to electrochemically-active molecules |
| US6649211B2 (en) * | 2002-02-28 | 2003-11-18 | The United States Of America As Represented By The Secretary Of The Navy | Selective deposition of hydrous ruthenium oxide thin films |
| US20040036129A1 (en) * | 2002-08-22 | 2004-02-26 | Micron Technology, Inc. | Atomic layer deposition of CMOS gates with variable work functions |
| US6641899B1 (en) * | 2002-11-05 | 2003-11-04 | International Business Machines Corporation | Nonlithographic method to produce masks by selective reaction, articles produced, and composition for same |
| KR100518270B1 (ko) * | 2002-12-18 | 2005-10-04 | 엘지.필립스 엘시디 주식회사 | 인쇄방식에 의한 패턴형성방법 |
| US6790719B1 (en) * | 2003-04-09 | 2004-09-14 | Freescale Semiconductor, Inc. | Process for forming dual metal gate structures |
| JP3790237B2 (ja) * | 2003-08-26 | 2006-06-28 | 株式会社東芝 | 半導体装置の製造方法 |
| US7005365B2 (en) * | 2003-08-27 | 2006-02-28 | Texas Instruments Incorporated | Structure and method to fabricate self-aligned transistors with dual work function metal gate electrodes |
-
2004
- 2004-04-19 US US10/827,202 patent/US7030001B2/en not_active Expired - Fee Related
-
2005
- 2005-03-22 KR KR1020067021698A patent/KR20070014152A/ko not_active Withdrawn
- 2005-03-22 WO PCT/US2005/009620 patent/WO2005106938A1/en not_active Ceased
- 2005-03-22 CN CNB2005800116539A patent/CN100437939C/zh not_active Expired - Fee Related
- 2005-03-22 EP EP05728396.2A patent/EP1776715B1/en not_active Expired - Lifetime
- 2005-03-22 JP JP2007508363A patent/JP4757867B2/ja not_active Expired - Fee Related
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1096705C (zh) * | 1997-08-22 | 2002-12-18 | 日本电气株式会社 | 半导体装置的制造方法 |
| US5959337A (en) * | 1997-12-08 | 1999-09-28 | Advanced Micro Devices, Inc. | Air gap spacer formation for high performance MOSFETs |
| CN1243336A (zh) * | 1998-06-30 | 2000-02-02 | 摩托罗拉公司 | 互补金属氧化物半导体器件及其形成方法 |
| US6686282B1 (en) * | 2003-03-31 | 2004-02-03 | Motorola, Inc. | Plated metal transistor gate and method of formation |
| US6867441B1 (en) * | 2003-10-08 | 2005-03-15 | Taiwan Semiconductor Manufacturing Co., Ltd. | Metal fuse structure for saving layout area |
Also Published As
| Publication number | Publication date |
|---|---|
| EP1776715A4 (en) | 2009-05-06 |
| JP2007533156A (ja) | 2007-11-15 |
| KR20070014152A (ko) | 2007-01-31 |
| CN1947230A (zh) | 2007-04-11 |
| US7030001B2 (en) | 2006-04-18 |
| EP1776715A1 (en) | 2007-04-25 |
| WO2005106938A1 (en) | 2005-11-10 |
| US20050233562A1 (en) | 2005-10-20 |
| EP1776715B1 (en) | 2013-06-19 |
| JP4757867B2 (ja) | 2011-08-24 |
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