WO2012088778A1 - 半导体器件及其形成方法 - Google Patents
半导体器件及其形成方法 Download PDFInfo
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- WO2012088778A1 WO2012088778A1 PCT/CN2011/070694 CN2011070694W WO2012088778A1 WO 2012088778 A1 WO2012088778 A1 WO 2012088778A1 CN 2011070694 W CN2011070694 W CN 2011070694W WO 2012088778 A1 WO2012088778 A1 WO 2012088778A1
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- WIPO (PCT)
- Prior art keywords
- dielectric layer
- isolation region
- semiconductor device
- layer
- forming
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 42
- 238000004519 manufacturing process Methods 0.000 title abstract description 7
- 239000010410 layer Substances 0.000 claims abstract description 168
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 64
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 64
- 239000010703 silicon Substances 0.000 claims abstract description 64
- 239000000758 substrate Substances 0.000 claims abstract description 49
- 238000000034 method Methods 0.000 claims abstract description 48
- 239000011229 interlayer Substances 0.000 claims abstract description 28
- 239000013078 crystal Substances 0.000 claims abstract description 23
- 238000002955 isolation Methods 0.000 claims description 56
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 12
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 12
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 12
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 12
- 238000011049 filling Methods 0.000 claims description 6
- 238000000137 annealing Methods 0.000 claims description 3
- 230000008569 process Effects 0.000 description 15
- 238000005516 engineering process Methods 0.000 description 7
- 229920002120 photoresistant polymer Polymers 0.000 description 7
- 230000000694 effects Effects 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 239000005388 borosilicate glass Substances 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 239000005360 phosphosilicate glass Substances 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000001459 lithography Methods 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 230000004044 response Effects 0.000 description 2
- 238000004380 ashing Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000005380 borophosphosilicate glass Substances 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 238000005507 spraying Methods 0.000 description 1
- 239000004575 stone Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
- H01L29/7846—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the lateral device isolation region, e.g. STI
Definitions
- the present invention relates to the field of semiconductor technology, and in particular, to a semiconductor device and a method of forming the same. Background technique
- CMOS Complementary Metal-oxide Semiconductor
- CD Critical Dimension
- the above table gives a comparison of the piezoelectric coefficient (piezoresistance coefficients) of a MOS field effect transistor (MOSFET, MOS transistor) and bulk silicon on a silicon wafer with a crystal face index of (001), and the piezoelectric coefficient. It is currently widely used in the art to predict and measure the mobility of electrons and holes.
- ⁇ ⁇ is the piezoelectric coefficient of the channel length (longitudinal direction) and the channel width (transverse direction), respectively.
- and ⁇ ⁇ can be expressed as three
- the basic cubic piezoelectric coefficient is a function of ⁇ naut, ⁇ 12 and ⁇ 44.
- the effect of piezoelectric coefficient on carrier mobility can be expressed as: ⁇ / ⁇ ⁇ + ⁇ ] , where is the percentage change in mobility , and 0" ⁇ are the stresses in the channel length and channel width directions, respectively.
- ⁇ the percentage change in mobility
- 0" ⁇ the stresses in the channel length and channel width directions, respectively.
- the method of introducing stress commonly used in the prior art mainly involves stress in the direction of the channel length I, such as double stress liner (DSL) technology, stress memory technology (SMT, Stress Memorization Technology) and the like.
- DSL double stress liner
- SMT stress memory technology
- SMT Stress Memorization Technology
- a tensor layer is covered with a tensile stress liner layer
- a PMOS transistor is covered with a compressive stress pad layer to respectively improve current carrying in the NMOS transistor and the PMOS transistor.
- Sub-mobility Therefore, in the manufacturing process, the double stress liner technology usually requires the formation of a pad layer having a corresponding stress for different types of transistors, and the process is complicated.
- Stress memory technology requires first forming a stress layer on the device and transferring the stress to the device channel through annealing or the like. The process is also complicated.
- the problem solved by the present invention is that the conventional semiconductor device imposes a stress on the MOS transistor, which is a complicated problem.
- the present invention provides a method of forming a semiconductor device, comprising: providing a silicon substrate, the silicon substrate is formed with a gate stack structure, the silicon substrate has a crystal face index of ⁇ 100 ⁇ ;
- first trench in the interlayer dielectric layer and/or the gate stack structure, the first trench extending in a crystal orientation ⁇ 110> and perpendicular to an extending direction of the gate stack structure;
- the invention also provides a semiconductor device comprising:
- the gate stack structure is formed on the silicon substrate
- the extension direction of the first isolation region is along a crystal orientation ⁇ 110> and perpendicular to an extension direction of the gate stack structure,
- the first isolation region includes a first dielectric layer, and the first dielectric layer is a tensile stress dielectric layer.
- the technical solution of the present invention has the following advantages: By forming the first trench and filling the tensile stress dielectric layer therein, the tensile stress dielectric layer is used to provide a tensile stress in the width direction of the channel of the ⁇ 110> direction in the longitudinal direction of the MOS transistor, which is advantageous for improving the response of the MOS transistor. Speed, improve device performance, and this technical solution can be applied to both PMOS transistors and NMOS transistors, which can improve the performance of the entire CMOS process circuit.
- FIG. 1 is a flow chart showing an embodiment of a method of forming a semiconductor device of the present invention. and a corresponding cross-sectional view.
- stress is typically introduced into the channel of a MOS transistor by a double stress liner technique, a stress memory technique, or the like.
- the technical solution provided by the present invention forms a first trench in the interlayer dielectric layer and/or the gate stack structure, and fills the tensile stress dielectric layer therein, so that the tensile stress dielectric layer is ⁇ 110> in the length direction of the MOS transistor.
- the channel provides tensile stress in the width direction, which is beneficial to improve the response speed of the MOS transistor and improve device performance.
- the technical solution can be applied to both PMOS transistors and NMOS transistors, and can improve the performance of the entire CMOS process circuit.
- the method for forming a semiconductor device of this embodiment includes:
- Step S11 providing a silicon substrate, the silicon substrate is formed with a gate stack structure, the silicon substrate has a crystal face index of ⁇ 100 ⁇ ;
- Step S12 forming an interlayer dielectric layer covering a surface of the silicon substrate
- Step S13 forming a first trench in the interlayer dielectric layer and/or the gate stack structure, the extending direction of the first trench is along the crystal orientation ⁇ 110> and perpendicular to the extension of the gate stack structure Direction
- Step S14 filling a first dielectric layer in the first trench, the first dielectric layer being a tensile stress dielectric layer.
- step S11 is performed to provide a silicon substrate 10 on which a gate stack structure 13 is formed, and the crystal plane index of the silicon substrate is ⁇ 100 ⁇ .
- Fig. 2a is a plan view of the silicon substrate 10
- Fig. 2b is a cross-sectional view taken along line a-a of Fig. 2a
- Fig. 2c is a cross-sectional view taken along line b-b of Fig. 2a.
- the crystal plane index of the silicon substrate 10 in the present embodiment is preferably ⁇ 100 ⁇ , that is, the crystal face index of the silicon substrate 10 belongs to the ⁇ 100 ⁇ family.
- the crystal plane index of the silicon substrate 10 in this embodiment is (100).
- a gate stack structure 13 is formed on the silicon substrate 10.
- the gate stack structure 13 may be before or after cutting.
- the gate stack structure 13 includes a gate dielectric layer 13a and a gate electrode 13b thereon, and an active region 10a and a drain region 10b are also formed in the silicon substrate 10 on both sides of the gate stack structure 13 (10a) And 10b also include source and drain extensions, such as LDD).
- the gate stack structure 13 may also include dummy gate electrodes in a back gate process.
- the channel length direction of the MOS transistor including the gate stack structure 13 is along the crystal orientation ⁇ 110>, that is, in the direction of the crystal orientation group ⁇ 110>, as a non-limiting example, specifically in the embodiment Extending in the [110] direction; correspondingly, the extending direction of the gate stack structure 13 is perpendicular to the crystal orientation [110].
- a second trench and a third trench may be formed on the silicon substrate 10 in advance, and the second trench extends in a direction parallel to a channel length direction of the MOS transistor, that is, along the crystal [110], the extending direction of the third trench is perpendicular to the extending direction of the second trench, and the MOS transistor is formed on the silicon substrate 10 surrounded by the second trench and the third trench.
- a second dielectric layer is formed (to form a second isolation region 11), and a third dielectric layer is filled in the third trench (to form a third isolation region 12).
- the number of the second trenches and the third trenches may be designed to be at least two, as a non-limiting example.
- the second trench and the third trench are respectively 2 The strip, the area enclosed by it, is formed with only one MOS transistor.
- the second dielectric layer may be a tensile stress dielectric layer, such as a silicon nitride layer having a tensile stress, a silicon oxide layer, a silicon oxynitride layer, or any combination of the three, preferably, the second The dielectric layer has a tensile stress of at least 1 GPa.
- the third dielectric layer is a low stress dielectric layer in this embodiment, such as a low stress silicon nitride layer, a silicon oxide layer, a silicon oxynitride layer, or any combination of the three, preferably the third dielectric layer. The stress does not exceed 180 MPa.
- the silicon oxide layer further comprises a doped silicon oxide layer such as PSG, BSG, BPSG, FSG or the like.
- the silicon nitride layer further includes a doped silicon nitride layer such as silicon nitride or the like.
- the silicon oxynitride layer further includes a doped silicon oxynitride layer such as silicon oxynitride or the like.
- the second dielectric layer having tensile stress can generate tensile stress in the channel width direction of the MOS transistor, which can improve the performance of the NMOS transistor and improve the performance of the PMOS transistor, and can effectively improve the performance of the entire CMOS circuit. .
- step S12 is performed to form an interlayer dielectric layer 14 covering the surface of the stone substrate 10.
- FIG. 3a is a plan view of the inter-layer dielectric layer 14
- FIG. 3b is a cross-sectional view along the line aa of FIG. 3a
- FIG. 3c is a cross-sectional view of FIG. 3a along the direction of bb, for clarity
- the second dielectric layer in the second trench below the interlayer dielectric layer 14 and the third dielectric layer in the third trench are shown by dashed lines in FIG. 3a using a see-through effect.
- the material of the interlayer dielectric layer 14 may be silicon oxide or doped silicon glass, such as borosilicate glass (BSG), phosphosilicate glass (PSG), etc., or other interlayer dielectric layers known to those skilled in the art.
- the method of forming the interlayer dielectric layer 14 may be chemical vapor deposition (CVD) or other methods known to those skilled in the art, planarizing it after formation to have its surface flush with the surface of the gate stack structure 13. Flat, the method of planarization may be chemical mechanical polishing (CMP).
- CVD chemical vapor deposition
- CMP chemical mechanical polishing
- step S13 is performed, and a first trench 16 is formed in the interlayer dielectric layer 14 and/or the gate stack structure 13, and the extending direction of the first trench 16 is perpendicular to The direction in which the gate stack structure 13 extends.
- 4a is a plan view of the photoresist layer 15 formed on the interlayer dielectric layer 14 and the gate stack structure 13 and patterned
- FIG. 4b is a cross-sectional view of FIG. 4a along the aa direction.
- Figure 4c is a cross-sectional view of Figure 4a along the direction of bb
- Figure 5a is a plan view after forming the first trench 16
- Figure 5b is a cross-sectional view of Figure 5a along the a-a' direction
- Figure 5c is a cross-sectional view of Figure 5a along the b-b
- Figures 4a and 5a also use dashed lines to indicate the perspective effect.
- a photoresist layer 15 is formed to cover the surface of the interlayer dielectric layer 14 and the gate stack structure 13, and the photoresist layer 15 is patterned to define a A pattern of the first groove is described.
- the photoresist layer 15 may be formed by spin coating, spray coating or the like, and the patterning method includes exposure, development, fixing, and the like.
- the interlayer dielectric layer 14 and the gate stack structure 13 are etched by using the patterned photoresist layer 15 as a mask to form a first trench 16 .
- the first trench 16 is located above the second isolation region 11 (including on the second isolation region 11), and the bottom portion exposes the second dielectric layer.
- the surface portion of the second dielectric layer is also etched away, such that the surface of the second dielectric layer is lower than the silicon.
- the second dielectric layer may not be etched only until the surface of the second dielectric layer is exposed.
- the etching method may be dry etching, wet etching, or the like.
- the width of the first trench 16 may be greater than, equal to, or smaller than the width of the second isolation region 11.
- the size of the first trench 16 is the same as the size of the second trench. Therefore, when the photoresist layer 15 is patterned, the same mask can be shared with the second trench, and the process steps can be reduced to reduce the cost.
- the first trench 16 is located above the second isolation region 11 in parallel with the extending direction of the second isolation region 11, that is, perpendicular to the extending direction of the gate stack structure 13. Since the gate stack structure 13 extends to cover the second dielectric layer, in the embodiment, the formation process of the first trench 16 can etch both the interlayer dielectric layer 14 and the gate stack structure 13. In other embodiments, only the gate stack structure 13 or the interlayer dielectric layer 14 may be etched.
- step S14 is performed, and the first trench 17 is filled in the first trench, and the first dielectric layer 17 is a tensile stress dielectric layer.
- the first dielectric layer 17 may be a tensile stress silicon nitride layer, a silicon oxide layer, a silicon oxynitride layer or any combination of the three, which may be formed by plasma enhanced chemical vapor deposition (PECVD), and may be deposited by adjustment.
- PECVD plasma enhanced chemical vapor deposition
- the stress type and stress magnitude of the formed first dielectric layer 17 are adjusted by parameters such as plasma power in the process.
- the tensile stress of the first dielectric layer 17 is at least 1 GPa.
- the material and the forming method of the first dielectric layer 17 may also be other materials and methods known to those skilled in the art, as long as the first dielectric layer 17 formed is a tensile stress dielectric layer.
- the first dielectric layer 17 can provide tensile stress to the width direction of the channel in the longitudinal direction of the MOS transistor of ⁇ 110>, which is advantageous for improving the performance of the NMOS transistor and the PMOS transistor, and can be applied to the CMOS process to improve the entire CMOS. The performance of the circuit. And it is convenient for industrial applications.
- the first dielectric layer 17 since the surface portion of the second dielectric layer is etched away during the process of forming the first trench, the first dielectric layer 17 also extends downward into the second isolation region 11, ie, Indirectly or directly embedded in the silicon substrate 10, the tensile stress of the first dielectric layer 17 on the silicon substrate 10 is promoted, which is advantageous for further improving the performance of the MOS transistor.
- the gate stack structure 13 is a dummy gate electrode in the back gate process
- the silicon substrate 10 including MOS
- the stress provided by the first dielectric layer 17 is memorized in the channel region of the transistor, and then the dummy gate electrode is removed and a gate dielectric layer and a gate electrode are formed.
- contact holes and plugs may also be formed in the interlayer dielectric layer 14 to form an upper metal interconnect structure.
- the structure of the MOS transistor formed in this embodiment is as shown in FIG. 6a to FIG. 6c, and includes: a silicon substrate 10 having a crystal plane index of ⁇ 100 ⁇ ; a gate formed on the silicon substrate 10. a stacked structure 13 and a source region 10a and a drain region 10b formed in the silicon substrate 10 on both sides of the gate stack structure 13; an interlayer dielectric layer 14 covering a surface of the silicon substrate 10; a first isolation region, located at the In the interlayer dielectric layer 14 and/or the gate stack structure 13, the extending direction of the first isolation region is along the crystal orientation ⁇ 110> and perpendicular to the extending direction of the gate stacked structure 13, the first isolation region includes The first dielectric layer 17 is a tensile stress dielectric layer.
- a second isolation region 11 and a third isolation region 12 are further formed in the silicon substrate 10.
- the extension direction of the second isolation region 11 is parallel to the extending direction of the first isolation region, and the third isolation
- the extending direction of the region 12 is perpendicular to the extending direction of the second isolation region 11, and the MOS transistor including the gate stacked structure 13 is formed on the silicon substrate 10 surrounded by the second isolation region 11 and the third isolation region 12.
- the second isolation region 11 includes a second dielectric layer
- the third isolation region 12 includes a third dielectric layer
- the first isolation region is located above the second isolation region 11, and the bottom of the first isolation region The second dielectric layer 11 is exposed.
- the second dielectric layer 11 is a tensile stress dielectric layer
- the third dielectric layer 12 is a low stress dielectric layer.
- the first isolation region extends downward into the surface portion of the second dielectric layer 11, that is, the surface of the second dielectric layer 11 is lower than the surface of the silicon substrate 10. In other embodiments, the first isolation region may not extend downward, that is, the surface of the second dielectric layer is flush with the surface of the silicon substrate 10.
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- Insulated Gate Type Field-Effect Transistor (AREA)
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Description
Claims
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201190000097.6U CN202534635U (zh) | 2010-12-29 | 2011-01-27 | 半导体器件 |
US13/142,591 US8772127B2 (en) | 2010-12-29 | 2011-01-27 | Semiconductor device and method for manufacturing the same |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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CN201010612577.XA CN102569086B (zh) | 2010-12-29 | 2010-12-29 | 半导体器件及其形成方法 |
CN201010612577.X | 2010-12-29 |
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WO2012088778A1 true WO2012088778A1 (zh) | 2012-07-05 |
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WO (1) | WO2012088778A1 (zh) |
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CN104795442A (zh) * | 2014-01-20 | 2015-07-22 | 中芯国际集成电路制造(上海)有限公司 | 一种半导体器件及其制造方法和电子装置 |
KR102318393B1 (ko) * | 2015-03-27 | 2021-10-28 | 삼성전자주식회사 | 전계 효과 트랜지스터를 포함하는 반도체 소자 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1478297A (zh) * | 2000-11-29 | 2004-02-25 | ض� | 利用特定晶体管取向的cmos制造方法 |
CN1507032A (zh) * | 2002-12-12 | 2004-06-23 | 国际商业机器公司 | 用于施加应力图形的隔离结构 |
CN1956221A (zh) * | 2005-10-27 | 2007-05-02 | 国际商业机器公司 | 具有介质应力产生区的晶体管及其制造方法 |
CN101533853A (zh) * | 2008-03-13 | 2009-09-16 | 台湾积体电路制造股份有限公司 | 半导体结构 |
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US7816198B2 (en) * | 2007-07-10 | 2010-10-19 | Infineon Technologies Ag | Semiconductor device and method for manufacturing the same |
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2011
- 2011-01-27 WO PCT/CN2011/070694 patent/WO2012088778A1/zh active Application Filing
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Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1478297A (zh) * | 2000-11-29 | 2004-02-25 | ض� | 利用特定晶体管取向的cmos制造方法 |
CN1507032A (zh) * | 2002-12-12 | 2004-06-23 | 国际商业机器公司 | 用于施加应力图形的隔离结构 |
CN1956221A (zh) * | 2005-10-27 | 2007-05-02 | 国际商业机器公司 | 具有介质应力产生区的晶体管及其制造方法 |
CN101533853A (zh) * | 2008-03-13 | 2009-09-16 | 台湾积体电路制造股份有限公司 | 半导体结构 |
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Publication number | Publication date |
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CN202534635U (zh) | 2012-11-14 |
CN102569086B (zh) | 2014-10-29 |
CN102569086A (zh) | 2012-07-11 |
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