CN111435658A - 形成介电层的方法 - Google Patents

形成介电层的方法 Download PDF

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CN111435658A
CN111435658A CN201910030825.0A CN201910030825A CN111435658A CN 111435658 A CN111435658 A CN 111435658A CN 201910030825 A CN201910030825 A CN 201910030825A CN 111435658 A CN111435658 A CN 111435658A
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dielectric layer
forming
substrate
region
patterns
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CN111435658B (zh
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刘玮鑫
邱达伟
张家隆
陈柏均
方宏义
陈意维
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United Microelectronics Corp
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Abstract

本发明公开一种形成介电层的方法，其包含有下述步骤。首先，提供一基底，其中基底包含一第一区以及一第二区。接着，形成多个图案于第一区的基底上以及一毯覆式堆叠结构于第二区的基底上。接续，形成一有机介电层覆盖此些图案、毯覆式堆叠结构以及基底。之后，以有机介电层作为一硬掩模层，图案化毯覆式堆叠结构，因而形成多个堆叠结构。其后，移除有机介电层。而后，形成一介电层全面覆盖此些图案、此些堆叠结构以及基底。

Description

形成介电层的方法
技术领域
本发明涉及一种形成介电层的方法，且特别是涉及一种应用有机介电层形成介电层的方法。
背景技术
现今介电材料的沉积方式大多以旋转涂布介电质(Spin-On Dielectric，SOD)制作工艺，或者化学气相沉积法(Chemical vapor deposition，CVD)而为之。采用旋转涂布介电质制作工艺最重要的考虑因素为，只要适当地调整、改变溶剂(DBE)系统，旋转涂布介电质制作工艺即可轻易地将流体状的介电质材料涂布至具有孔洞的基材内，此乃旋转涂布介电质制作工艺的独特优势，因此现阶段半导体业界乃以旋转涂布介电质制作工艺为应用主流。
一般而言，通常在半导体的结构上多将许多不同大小、规格、尺寸的结构设计于一基材的上方，当以旋转涂布介电质制作工艺涂布介电质材料于此基材上之后，介电质材料势必覆盖满基材表面的不规则凹凸起伏。
然而，在搭配不同区的图案制作工艺而个别涂布介电材料于各区时，多次进行旋转涂布介电质制作工艺及固化介电质制作工艺等，所进行的繁复制作工艺损害装置及增加制作工艺花费。
发明内容
本发明提出一种形成介电层的方法，其以有机介电层取代介电层并作为图案化堆叠结构的硬掩模，以简化制作工艺并减少制作工艺损害。
本发明提供一种形成介电层的方法，包含有下述步骤。首先，提供一基底，其中基底包含一第一区以及一第二区。接着，形成多个图案于第一区的基底上以及一毯覆式堆叠结构于第二区的基底上。接续，形成一有机介电层覆盖此些图案、毯覆式堆叠结构以及基底。之后，以有机介电层作为一硬掩模层，图案化毯覆式堆叠结构，因而形成多个堆叠结构。其后，移除有机介电层。而后，形成一介电层全面覆盖此些图案、此些堆叠结构以及基底。
基于上述，本发明提出一种形成介电层的方法，其形成一有机介电层覆盖于一第一区的一基底上的图案以及一第二区的基底上的一毯覆式堆叠结构，再以有机介电层作为一硬掩模层图案化毯覆式堆叠结构，而形成多个堆叠结构于第二区的基底上。如此一来，移除有机介电层后，则可同时形成一介电层全面覆盖第一区以及第二区的图案、堆叠结构以及基底。因此，本发明可省略一次在图案化毯覆式堆叠结构之前形成介电层的步骤，避免一次固化介电层所造成的热积存(thermal budget)而损害装置，且仅需要一次同时形成于第一区及第二区中的介电层的步骤而能简化制作工艺。
附图说明
图1为本发明优选实施例中形成介电层的方法的剖面示意图；
图2为本发明优选实施例中形成介电层的方法的剖面示意图；
图3为本发明优选实施例中形成介电层的方法的剖面示意图；
图4为本发明优选实施例中形成介电层的方法的剖面示意图；
图5为本发明优选实施例中形成介电层的方法的剖面示意图；
图6为本发明优选实施例中形成介电层的方法的剖面示意图；
图7为本发明优选实施例中形成介电层的方法的剖面示意图；
图8为本发明优选实施例中形成介电层的方法的剖面示意图；
图9为本发明优选实施例中形成介电层的方法的剖面示意图；
图10为本发明优选实施例中形成介电层的方法的剖面示意图。
主要元件符号说明
2、6：氧化硅层
4：氮化硅层
10：绝缘结构
20：埋入式的栅极结构
30：硅磷结构
40：含硅硬掩模底部抗反射涂层
110：基底
122：第一间隙壁
124：轻掺杂源/漏极
132：第二间隙壁
134：源/漏极
140：有机介电层
152：第三间隙壁
162：第四间隙壁
170、170a：介电层
A：第一区
B：第二区
g1、g2：间隙
M1：图案
M2：毯覆式堆叠结构
M2a：堆叠结构
P1：固化制作工艺
P2：研磨制作工艺
Q：光致抗蚀剂层
具体实施方式
图1～图10绘示本发明优选实施例中形成介电层的方法的剖面示意图。如图1所示，提供一基底110。基底110例如是一硅基底、一含硅基底(例如SiC)、一三五族基底(例如GaN)、一三五族覆硅基底(例如GaN-on-silicon)、一石墨烯覆硅基底(graphene-on-silicon)、一硅覆绝缘(silicon-on-insulator，SOI)基底或一含外延层的基底等半导体基底。基底110可包含一第一区A以及一第二区B。在一优选的实施例中，第二区B的图案密度小于第一区A的图案。例如，第一区A包含一逻辑区，且第二区B包含一动态随机存取存储器区，但本发明不以此为限。在其他实施例中，第一区A可包含一逻辑区，且第二区B包含一静态随机存取存储器区；或者，第一区A及第二区B都为逻辑区；或者，第一区A可包含一逻辑区，第二区B包含一闪存存储器区。形成绝缘结构10于基底110中。绝缘结构10用以电性隔绝第一区A以及第二区B等各区元件。绝缘结构10可例如为浅沟隔离(shallow trenchisolation,STI)结构，其可例如以一浅沟隔离(shallow trench isolation,STI)制作工艺形成，但本发明不限于此。
本实施例以第二区B为动态随机存取存储器区为例，因而可在第二区B的基底110中设置多个埋入式的栅极结构20，而绝缘结构10与覆盖于第二区B的基底110表面的绝缘材料可细部包含例如一氧化硅层2、一氮化硅层4与一氧化硅层6等，且形成硅磷结构30于第二区B的基底110上，但本发明不以此为限。在其他实施例中，第一区A以及第二区B可都为逻辑区，且第二区B的图案密度小于第一区A的图案，因而可省略埋设埋入式的栅极结构20、氧化硅层2、氮化硅层4、氧化硅层6与硅磷结构30等步骤。改以直接形成下述堆叠结构的步骤。
形成多个图案M1于第一区A的基底110上以及一毯覆式堆叠结构M2于第二区B的基底110上。详细而言，可先全面依序沉积多个材料层，再以光致抗蚀剂图案化而同时于第一区A形成图案M1，以及第二区B形成毯覆式堆叠结构M2。在本实施例中，图案M1及毯覆式堆叠结构M2可为一堆叠的结构，且堆叠的结构由下而上可包含以原子层沉积制作工艺形成厚度130埃的一氮化层、厚度226埃的一非晶硅层、厚度50埃的一硅钛层、厚度80埃的一氮化钛层、厚度20埃的一硅钨层、厚度230埃的一钨层、厚度20埃的一下层氮化层及厚度345埃的一上层氮化层，但本发明不以此为限。图案M1可例如为栅极，而毯覆式堆叠结构M2是在后续制作工艺图案化后形成位线栅极，但本发明不限于此。在第一区A以及第二区B都为逻辑区的其他实施例中，图案M1及毯覆式堆叠结构M2可用作为栅极的堆叠结构。堆叠结构因此可例如为由下而上堆叠的栅极介电层、栅极电极以及盖层等。
如图2所示，形成第一间隙壁122于图案M1与毯覆式堆叠结构M2的侧壁上，用以定义第一区A中形成轻掺杂源/漏极的区域。接着，形成轻掺杂源/漏极124于图案M1侧壁上的第一间隙壁122侧边的基底110中。具体而言，可例如先以一光致抗蚀剂遮蔽第二区B，而仅形成轻掺杂源/漏极124于图案M1侧壁上的第一间隙壁122侧边的基底110中。在本实施例中，第一间隙壁122是仅用以形成第一区A的轻掺杂源/漏极124，而第二区B的毯覆式堆叠结构M2的侧壁上也会同时形成第一间隙壁122，但不会形成轻掺杂源/漏极。
如图3所示，形成第二间隙壁132于图案M1与毯覆式堆叠结构M2的侧壁上，用以定义第一区A中形成源/漏极的区域。接着，形成源/漏极134于图案M1侧壁上的第二间隙壁132侧边的基底110中。具体而言，可例如先以一光致抗蚀剂遮蔽第二区B，而仅形成源/漏极134于图案M1侧壁上的第二间隙壁132侧边的基底110中。在本实施例中，第二间隙壁132仅用以形成第一区A的源/漏极134，而第二区B的毯覆式堆叠结构M2的侧壁上也会同时形成第二间隙壁132，但不会形成源/漏极。
如图4所示，形成一有机介电层140同时覆盖第一区A以及第二区B的图案M1、毯覆式堆叠结构M2以及基底110。有机介电层140可例如以一旋转涂布(spin on coating,SOC)制作工艺形成，但本发明不以此为限。
如图5～图6所示，图案化毯覆式堆叠结构M2，以形成多个堆叠结构M2a。本发明直接以有机介电层140作为一硬掩模层，图案化毯覆式堆叠结构M2。如图5所示，可先依序形成一含硅硬掩模底部抗反射涂层40以及一光致抗蚀剂层Q于有机介电层140上，再依序转移光致抗蚀剂层Q的图案至含硅硬掩模底部抗反射涂层40、转移含硅硬掩模底部抗反射涂层40的图案至有机介电层140、以及转移有机介电层140的图案至毯覆式堆叠结构M2，而形成多个堆叠结构M2a，如图6所示。随即，移除有机介电层140。在一优选实施例中，有机介电层140以一氧剥离(O2strip process)制作工艺移除，但本发明不以此为限。在本实施例中，多个堆叠结构M2a即为位线栅极，但本发明不以此为限。堆叠结构M2a的组成材质层与用途视实际情况而定。第二区B中的堆叠结构M2a之间的间隙g1小于第一区A中的图案M1之间的间隙g2，故本发明先形成图案M1再图案化毯覆式堆叠结构M2，因而在后续第一区A中形成四层间隙壁，但仅在第二区B中形成双层间隙壁。
在此强调，本发明以有机介电层140取代形成于第一区A的介电层，而能直接作为图案化毯覆式堆叠结构M2的硬掩模层，因而可省略以旋转涂布制作工艺形成介电层、固化介电层及平坦化介电层的步骤。再者，本发明可避免此步骤中以例如退火制作工艺等固化介电层制作工艺所造成的热积存(thermal budget)，而损害装置。
如图7所示，形成第三间隙壁152于图案M1与堆叠结构M2a的侧壁上，用以定义第二区B中形成轻掺杂源/漏极的区域。接续，形成轻掺杂源/漏极(未绘示)于堆叠结构M2a侧壁上的第三间隙壁152侧边的基底110中。具体而言，可例如先以一光致抗蚀剂遮蔽第一区A，而仅形成轻掺杂源/漏极(未绘示)于堆叠结构M2a侧壁上的第三间隙壁152侧边的基底110中。在本实施例中，第一区A及第二区B都会同时形成第三间隙壁152。
如图8所示，形成第四间隙壁162于图案M1与堆叠结构M2a的侧壁上，用以定义第二区B中形成源/漏极的区域。接续，形成源/漏极(未绘示)于堆叠结构M2a侧壁上的第四间隙壁162侧边的基底110中。具体而言，可例如先以一光致抗蚀剂遮蔽第一区A，而仅形成源/漏极(未绘示)于堆叠结构M2a侧壁上的第四间隙壁162侧边的基底110中。在本实施例中，第一区A及第二区B都会同时形成第四间隙壁162。在蚀刻形成第一区A及第二区B中的第四间隙壁162时，第一区A及第二区B中位于图案M1与堆叠结构M2a顶面的第三间隙壁152也可能部分或全部移除。
如图9所示，形成一介电层170全面覆盖图案M1、堆叠结构M2a以及基底110。介电层170可例如以一旋转介电(spin on dielectric,SOD)制作工艺形成，但本发明不以此为限。本发明的介电层170同时形成于第一区A及第二区B中。
之后，进行一固化制作工艺P1于介电层170，再进行一研磨制作工艺P2于介电层170，如图9～图10所示。在形成介电层170全面覆盖图案M1、堆叠结构M2a以及基底110之后，可进行固化制作工艺P1于介电层170，以固化介电层170。固化制作工艺P1可例如为一退火制作工艺，但本发明不限于此。之后，进行研磨制作工艺P2于介电层170，以形成具有平坦顶面的一介电层170a。如此，本发明仅需要一次同时形成介电层170于第一区A及第二区B中的步骤，而能简化制作工艺，并减少步骤所造成的装置损害。
综上所述，本发明提出一种形成介电层的方法，其形成一有机介电层覆盖于一第一区的一基底上的图案以及一第二区的基底上的一毯覆式堆叠结构，再以有机介电层作为一硬掩模层图案化毯覆式堆叠结构，而形成多个堆叠结构于第二区的基底上。如此一来，移除有机介电层后，则可同时形成一介电层全面覆盖第一区以及第二区的图案、堆叠结构以及基底。因此，本发明可省略一次在图案化毯覆式堆叠结构之前形成介电层的步骤(此步骤包含一旋转涂布制作工艺形成介电层、一固化制作工艺及一平坦化制作工艺)，因而可避免例如退火制作工艺等固化介电层制作工艺所造成的热积存(thermal budget)，而损害装置。进而，本发明仅需要一次同时形成第一区及第二区中的介电层的步骤，是以本发明能简化制作工艺并减少装置损害。
以上所述仅为本发明的优选实施例，凡依本发明权利要求所做的均等变化与修饰，都应属本发明的涵盖范围。

Claims (15)

1.一种形成介电层的方法，包含有：
提供基底，其中该基底包含第一区以及第二区；
形成多个图案于该第一区的该基底上以及毯覆式堆叠结构于该第二区的该基底上；
形成有机介电层覆盖该些图案、该毯覆式堆叠结构以及该基底；
以该有机介电层作为硬掩模层，图案化该毯覆式堆叠结构，因而形成多个堆叠结构；
移除该有机介电层；以及
形成介电层全面覆盖该些图案、该些堆叠结构以及该基底。
2.如权利要求1所述的形成介电层的方法，其中该第二区中的该些堆叠结构之间的间隙小于该第一区中的该些图案之间的间隙。
3.如权利要求2所述的形成介电层的方法，其中该第一区包含逻辑区，且该第二区包含动态随机存取存储器区。
4.如权利要求3所述的形成介电层的方法，其中该些图案包含栅极，且该些堆叠结构包含位线栅极。
5.如权利要求1所述的形成介电层的方法，在形成该有机介电层覆盖该些图案、该毯覆式堆叠结构以及该基底之后，还包含：
依序形成含硅硬掩模底部抗反射涂层以及光致抗蚀剂层于该有机介电层上，且图案化该毯覆式堆叠结构的方法为依序转移该光致抗蚀剂层、该含硅硬掩模底部抗反射涂层以及该有机介电层的图案。
6.如权利要求1所述的形成介电层的方法，其中以一氧剥离制作工艺移除该有机介电层。
7.如权利要求1所述的形成介电层的方法，在形成该有机介电层覆盖该些图案、该毯覆式堆叠结构以及该基底之前，还包含：
形成第一间隙壁于该些图案与该毯覆式堆叠结构的侧壁上。
8.如权利要求7所述的形成介电层的方法，还包含：
形成轻掺杂源/漏极于该些图案的侧壁上的该些第一间隙壁侧边的该基底中。
9.如权利要求7所述的形成介电层的方法，在形成该些第一间隙壁之后，还包含：
形成第二间隙壁于该些图案与该毯覆式堆叠结构的侧壁上。
10.如权利要求9所述的形成介电层的方法，还包含：
形成源/漏极于该些图案的侧壁上的该些第二间隙壁侧边的该基底中。
11.如权利要求1所述的形成介电层的方法，在移除该有机介电层之后，还包含：
形成第三间隙壁于该些图案与该些堆叠结构的侧壁上。
12.如权利要求11所述的形成介电层的方法，还包含：
形成轻掺杂源/漏极于该些堆叠结构的侧壁上的该些第三间隙壁侧边的该基底中。
13.如权利要求11所述的形成介电层的方法，在形成该些第三间隙壁之后，还包含：
形成第四间隙壁于该些图案与该些堆叠结构的侧壁上。
14.如权利要求13所述的形成介电层的方法，还包含：
形成源/漏极于该些堆叠结构的侧壁上的该些第四间隙壁侧边的该基底中。
15.如权利要求1所述的形成介电层的方法，还包含：
进行固化制作工艺于该介电层，再进行研磨制作工艺于该介电层。
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