JP2006190935A - フラッシュメモリ素子の製造方法 - Google Patents
フラッシュメモリ素子の製造方法 Download PDFInfo
- Publication number
- JP2006190935A JP2006190935A JP2005152127A JP2005152127A JP2006190935A JP 2006190935 A JP2006190935 A JP 2006190935A JP 2005152127 A JP2005152127 A JP 2005152127A JP 2005152127 A JP2005152127 A JP 2005152127A JP 2006190935 A JP2006190935 A JP 2006190935A
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- oxide film
- buffer oxide
- gate line
- spacer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims abstract description 64
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 14
- 125000006850 spacer group Chemical group 0.000 claims abstract description 42
- 238000005530 etching Methods 0.000 claims abstract description 23
- 150000004767 nitrides Chemical class 0.000 claims abstract description 20
- 239000000758 substrate Substances 0.000 claims abstract description 19
- 239000004065 semiconductor Substances 0.000 claims abstract description 18
- 238000000137 annealing Methods 0.000 claims abstract description 16
- 239000012535 impurity Substances 0.000 claims abstract description 13
- 238000005468 ion implantation Methods 0.000 claims abstract description 13
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 claims description 14
- 238000001039 wet etching Methods 0.000 claims description 13
- 229910000147 aluminium phosphate Inorganic materials 0.000 claims description 7
- 229910052751 metal Inorganic materials 0.000 abstract description 13
- 239000002184 metal Substances 0.000 abstract description 13
- 230000003647 oxidation Effects 0.000 abstract description 10
- 238000007254 oxidation reaction Methods 0.000 abstract description 10
- 230000002159 abnormal effect Effects 0.000 abstract description 9
- 239000010410 layer Substances 0.000 description 13
- 238000007789 sealing Methods 0.000 description 4
- 230000003213 activating effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
- H01L29/7881—Programmable transistors with only two possible levels of programmation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
- H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
- H01L21/28185—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42324—Gate electrodes for transistors with a floating gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Crystallography & Structural Chemistry (AREA)
- General Chemical & Material Sciences (AREA)
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Abstract
【解決手段】フラッシュメモリ素子の製造方法は、半導体基板上にゲートラインを形成する段階と、ゲートラインを含んだ全体構造上にバッファ酸化膜および窒化膜を順次形成する段階と、全面エッチング工程で窒化膜をエッチングして絶縁膜スペーサを形成する段階と、ゲートと絶縁膜スペーサをイオン注入マスクとして半導体基板に不純物領域を形成する段階と、バッファ酸化膜を稠密にするためにアニーリング工程を行う段階と、絶縁膜スペーサを除去する段階と、自体整合コンタクト工程を行う段階とを含む。
【選択図】なし
Description
202 …トンネル酸化膜
203 …フローティングゲート
204 …誘電体膜
205 …コントロールゲート
206 …金属層
207 …ハードマスク
208 …ゲートライン
209 …接合領域
209H …高濃度不純物領域
209L …低濃度不純物領域
210 …シーリング窒化膜
211 …バッファ酸化膜
212 …窒化膜
212a …絶縁膜スペーサ
Claims (6)
- 半導体基板上にゲートラインを形成する段階と、
前記ゲートラインを含んだ全体構造上にバッファ酸化膜および窒化膜を順次形成する段階と、
全面エッチング工程で前記窒化膜をエッチングして絶縁膜スペーサを形成する段階と、
前記ゲートと前記絶縁膜スペーサをイオン注入マスクとして前記半導体基板に不純物領域を形成する段階と、
前記バッファ酸化膜を稠密にするためにアニーリング工程を行う段階と、
前記絶縁膜スペーサを除去する段階と、
自体整合コンタクト工程を行う段階とを含み、
稠密になった前記バッファ酸化膜は、前記絶縁膜スペーサの除去の際にエッチング率がより低くなって前記ゲートラインの一部が露出し酸化することを防止することを特徴とするフラッシュメモリ素子の製造方法。 - 前記バッファ酸化膜を形成する前に、
前記ゲートラインをイオン注入マスクとしてイオン注入工程によって前記半導体基板に低濃度不純物領域を形成する段階をさらに含むことを特徴とする請求項1記載のフラッシュメモリ素子の製造方法。 - 前記絶縁膜スペーサは、リン酸を用いたウェットエッチング工程で除去されることを特徴とする請求項1記載のフラッシュメモリ素子の製造方法。
- 前記ウェットエッチング工程は、前記バッファ酸化膜のエッチング率と厚さを考慮し、前記絶縁膜スペーサは完全に除去するが、前記バッファ酸化膜が残留可能な程度の時間だけ行われることを特徴とする請求項1記載のフラッシュメモリ素子の製造方法。
- 前記ウェットエッチング工程は5分〜25分間行われることを特徴とする請求項1記載のフラッシュメモリ素子の製造方法。
- 前記バッファ酸化膜は、前記窒化膜のエッチング後に50Å〜150Åの厚さだけ残留することを特徴とする請求項1記載のフラッシュメモリ素子の製造方法。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR10-2004-0114142 | 2004-12-28 | ||
KR1020040114142A KR100632654B1 (ko) | 2004-12-28 | 2004-12-28 | 플래시 메모리 소자의 제조 방법 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2006190935A true JP2006190935A (ja) | 2006-07-20 |
JP4892198B2 JP4892198B2 (ja) | 2012-03-07 |
Family
ID=36612255
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2005152127A Expired - Fee Related JP4892198B2 (ja) | 2004-12-28 | 2005-05-25 | フラッシュメモリ素子の製造方法 |
Country Status (5)
Country | Link |
---|---|
US (1) | US20060141725A1 (ja) |
JP (1) | JP4892198B2 (ja) |
KR (1) | KR100632654B1 (ja) |
CN (1) | CN1797724A (ja) |
TW (1) | TWI276207B (ja) |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100845720B1 (ko) * | 2006-11-30 | 2008-07-10 | 동부일렉트로닉스 주식회사 | 플래시 메모리 소자 및 그의 제조방법 |
KR100800675B1 (ko) * | 2006-12-21 | 2008-02-01 | 동부일렉트로닉스 주식회사 | 플래쉬 메모리 소자의 제조 방법 |
KR100940661B1 (ko) * | 2007-12-24 | 2010-02-05 | 주식회사 동부하이텍 | 플래시 메모리 소자의 제조 방법 |
KR100932135B1 (ko) * | 2007-12-27 | 2009-12-16 | 주식회사 동부하이텍 | 플래쉬 메모리 소자 제조방법 |
KR100944342B1 (ko) * | 2008-03-13 | 2010-03-02 | 주식회사 하이닉스반도체 | 플로팅 바디 트랜지스터를 갖는 반도체 소자 및 그 제조방법 |
US20100032813A1 (en) * | 2008-08-08 | 2010-02-11 | Texas Instruments Incorporated | Ic formed with densified chemical oxide layer |
US9287282B2 (en) * | 2014-01-28 | 2016-03-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of forming a logic compatible flash memory |
Citations (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60177678A (ja) * | 1984-02-24 | 1985-09-11 | Hitachi Ltd | 半導体集積回路装置の製造方法 |
JPS62188375A (ja) * | 1986-02-14 | 1987-08-17 | Hitachi Ltd | 半導体集積回路装置 |
JPH0637326A (ja) * | 1992-07-15 | 1994-02-10 | Mitsubishi Electric Corp | 不揮発性半導体記憶装置およびその製造方法 |
JPH07161848A (ja) * | 1993-12-06 | 1995-06-23 | Toshiba Corp | 不揮発性半導体記憶装置 |
JPH11214547A (ja) * | 1998-01-26 | 1999-08-06 | Ricoh Co Ltd | 半導体装置及びその製造方法 |
JP2002057230A (ja) * | 2000-08-11 | 2002-02-22 | Toshiba Corp | 不揮発性半導体記憶装置 |
JP2002141500A (ja) * | 2000-10-31 | 2002-05-17 | Toshiba Corp | 半導体装置及びその製造方法 |
JP2003086718A (ja) * | 2001-09-13 | 2003-03-20 | Matsushita Electric Ind Co Ltd | 半導体装置の製造方法 |
JP2003152164A (ja) * | 2001-08-10 | 2003-05-23 | Hynix Semiconductor America Inc | 多様な技術及びアプリケーションに対して容易に修正可能な周辺トランジスタを有するセルフアラインメントコンタクト不揮発性メモリ装置及びその製造方法 |
JP2003197782A (ja) * | 2001-12-22 | 2003-07-11 | Hynix Semiconductor Inc | フラッシュメモリセルの製造方法 |
JP2004241780A (ja) * | 2003-02-06 | 2004-08-26 | Samsung Electronics Co Ltd | 選択的ディスポーザブルスペーサー技術を使用する半導体集積回路の製造方法及びそれによって製造される半導体集積回路 |
JP2004363457A (ja) * | 2003-06-06 | 2004-12-24 | Toshiba Corp | 不揮発性半導体記憶装置及びその製造方法 |
Family Cites Families (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6054355A (en) * | 1997-06-30 | 2000-04-25 | Kabushiki Kaisha Toshiba | Method of manufacturing a semiconductor device which includes forming a dummy gate |
US6025267A (en) * | 1998-07-15 | 2000-02-15 | Chartered Semiconductor Manufacturing, Ltd. | Silicon nitride--TEOS oxide, salicide blocking layer for deep sub-micron devices |
US6277674B1 (en) * | 1998-10-02 | 2001-08-21 | Micron Technology, Inc. | Semiconductor fuses, methods of using the same, methods of making the same, and semiconductor devices containing the same |
KR100366619B1 (ko) * | 1999-05-12 | 2003-01-09 | 삼성전자 주식회사 | 트랜치 소자분리방법, 트랜치를 포함하는 반도체소자의제조방법 및 그에 따라 제조된 반도체소자 |
US6660657B1 (en) * | 2000-08-07 | 2003-12-09 | Micron Technology, Inc. | Methods of incorporating nitrogen into silicon-oxide-containing layers |
US6506650B1 (en) * | 2001-04-27 | 2003-01-14 | Advanced Micro Devices, Inc. | Method of fabrication based on solid-phase epitaxy for a MOSFET transistor with a controlled dopant profile |
US7002223B2 (en) * | 2001-07-27 | 2006-02-21 | Samsung Electronics Co., Ltd. | Semiconductor device having elevated source/drain |
KR100432888B1 (ko) * | 2002-04-12 | 2004-05-22 | 삼성전자주식회사 | 비휘발성 메모리 소자 및 그 제조방법 |
JP2004014875A (ja) * | 2002-06-07 | 2004-01-15 | Fujitsu Ltd | 半導体装置及びその製造方法 |
US6740571B2 (en) * | 2002-07-25 | 2004-05-25 | Mosel Vitelic, Inc. | Method of etching a dielectric material in the presence of polysilicon |
US6891192B2 (en) * | 2003-08-04 | 2005-05-10 | International Business Machines Corporation | Structure and method of making strained semiconductor CMOS transistors having lattice-mismatched semiconductor regions underlying source and drain regions |
US20050054164A1 (en) * | 2003-09-09 | 2005-03-10 | Advanced Micro Devices, Inc. | Strained silicon MOSFETs having reduced diffusion of n-type dopants |
KR20050048114A (ko) * | 2003-11-19 | 2005-05-24 | 주식회사 하이닉스반도체 | 플래쉬 메모리 소자의 제조 방법 |
US7005700B2 (en) * | 2004-01-06 | 2006-02-28 | Jong Ho Lee | Double-gate flash memory device |
-
2004
- 2004-12-28 KR KR1020040114142A patent/KR100632654B1/ko not_active IP Right Cessation
-
2005
- 2005-05-16 TW TW094115722A patent/TWI276207B/zh not_active IP Right Cessation
- 2005-05-16 US US11/129,776 patent/US20060141725A1/en not_active Abandoned
- 2005-05-25 JP JP2005152127A patent/JP4892198B2/ja not_active Expired - Fee Related
- 2005-09-22 CN CN200510106945.2A patent/CN1797724A/zh active Pending
Patent Citations (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60177678A (ja) * | 1984-02-24 | 1985-09-11 | Hitachi Ltd | 半導体集積回路装置の製造方法 |
JPS62188375A (ja) * | 1986-02-14 | 1987-08-17 | Hitachi Ltd | 半導体集積回路装置 |
JPH0637326A (ja) * | 1992-07-15 | 1994-02-10 | Mitsubishi Electric Corp | 不揮発性半導体記憶装置およびその製造方法 |
JPH07161848A (ja) * | 1993-12-06 | 1995-06-23 | Toshiba Corp | 不揮発性半導体記憶装置 |
JPH11214547A (ja) * | 1998-01-26 | 1999-08-06 | Ricoh Co Ltd | 半導体装置及びその製造方法 |
JP2002057230A (ja) * | 2000-08-11 | 2002-02-22 | Toshiba Corp | 不揮発性半導体記憶装置 |
JP2002141500A (ja) * | 2000-10-31 | 2002-05-17 | Toshiba Corp | 半導体装置及びその製造方法 |
JP2003152164A (ja) * | 2001-08-10 | 2003-05-23 | Hynix Semiconductor America Inc | 多様な技術及びアプリケーションに対して容易に修正可能な周辺トランジスタを有するセルフアラインメントコンタクト不揮発性メモリ装置及びその製造方法 |
JP2003086718A (ja) * | 2001-09-13 | 2003-03-20 | Matsushita Electric Ind Co Ltd | 半導体装置の製造方法 |
JP2003197782A (ja) * | 2001-12-22 | 2003-07-11 | Hynix Semiconductor Inc | フラッシュメモリセルの製造方法 |
JP2004241780A (ja) * | 2003-02-06 | 2004-08-26 | Samsung Electronics Co Ltd | 選択的ディスポーザブルスペーサー技術を使用する半導体集積回路の製造方法及びそれによって製造される半導体集積回路 |
JP2004363457A (ja) * | 2003-06-06 | 2004-12-24 | Toshiba Corp | 不揮発性半導体記憶装置及びその製造方法 |
Also Published As
Publication number | Publication date |
---|---|
JP4892198B2 (ja) | 2012-03-07 |
KR20060075365A (ko) | 2006-07-04 |
TWI276207B (en) | 2007-03-11 |
TW200623341A (en) | 2006-07-01 |
KR100632654B1 (ko) | 2006-10-12 |
US20060141725A1 (en) | 2006-06-29 |
CN1797724A (zh) | 2006-07-05 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP4892198B2 (ja) | フラッシュメモリ素子の製造方法 | |
JP2006303009A (ja) | 半導体装置およびその製造方法 | |
JP2007103652A (ja) | 半導体装置およびその製造方法 | |
JP2006278967A (ja) | 半導体装置およびその製造方法 | |
JP2010040538A (ja) | 半導体装置の製造方法 | |
US7851290B2 (en) | Method of fabricating semiconductor device | |
JP2009049235A (ja) | 半導体装置およびその製造方法 | |
JP5063030B2 (ja) | NAND型フラッシュメモリ素子の製造方法{MethodofmanufacturingaNANDtypeflashmemorydevice} | |
KR100624923B1 (ko) | 플래쉬 메모리 셀의 제조 방법 | |
KR100807517B1 (ko) | 반도체 메모리 소자의 콘택 형성 방법 | |
JP2006066886A (ja) | フラッシュメモリ素子の製造方法 | |
KR100376269B1 (ko) | 플래쉬 메모리 소자의 제조방법 | |
KR20070059324A (ko) | Nand형 플래쉬 메모리 소자의 제조 방법 | |
US7160794B1 (en) | Method of fabricating non-volatile memory | |
JP2007227900A (ja) | 非揮発性メモリ素子の製造方法 | |
JP2006313874A (ja) | フラッシュメモリ素子の製造方法 | |
KR100691484B1 (ko) | 반도체소자의 플러그 제조 방법 | |
JP2009152413A (ja) | 半導体装置およびその製造方法 | |
KR100418090B1 (ko) | 반도체 소자의 제조 방법 | |
KR20090123513A (ko) | 반도체 소자 및 그 제조방법 | |
KR100593129B1 (ko) | 플래시 메모리 소자의 제조 방법 | |
KR100639465B1 (ko) | Nor형 플래쉬 메모리 소자의 제조 방법 | |
KR100833443B1 (ko) | 플래시 메모리 소자의 제조 방법 | |
KR20090123514A (ko) | 반도체 소자 및 그 제조방법 | |
KR101010837B1 (ko) | 반도체 소자의 스페이서 형성방법 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20080417 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20110818 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20110823 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20111116 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20111213 |
|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20111219 |
|
R150 | Certificate of patent or registration of utility model |
Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20141222 Year of fee payment: 3 |
|
LAPS | Cancellation because of no payment of annual fees |