JP2006100503A - 半導体装置およびその製造方法 - Google Patents
半導体装置およびその製造方法 Download PDFInfo
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- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
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- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
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- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
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- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53214—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being aluminium
- H01L23/53223—Additional layers associated with aluminium layers, e.g. adhesion, barrier, cladding layers
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
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Abstract
【解決手段】
半導体装置は、半導体基板と、半導体基板の上部に設けられている層間縁膜101と、この層間絶縁膜101上に設けられており、Ti膜105と、TiN膜107と、AlCu膜109と、Ti膜111およびTiN膜113と、エッチング調整膜115と、が順に積層されてなる積層体と、を備える。半導体装置は、層間絶縁膜101および積層体上に設けられている層間絶縁膜103と、層間絶縁膜103およびエッチング調整膜115を貫通し、端面がTiN膜113中に位置しているTi膜117、TiN膜119およびW膜121からなる導電プラグと、を備える。
【選択図】 図1
Description
図1は、実施の形態に係る半導体装置の一部を模式的に示した断面図である。
しかし、これらの対策は、Via抵抗の増加、投資増大、製造安定性低下、デバイス性能低下、設計制約増加を招く。
本実施形態に係る半導体装置は、互いに長さの異なる導電プラグが2本設けられている段違いビア構造を備える点を除いては、基本的に実施形態1に係る半導体装置と同様の構成を有する。図3は、実施の形態に係る半導体装置を模式的に示した断面図である。
本実施形態に係る半導体装置は、上記の複数の積層体に含まれるエッチング調整膜165は、互いに連続した膜からなる点を除いては、基本的に実施形態1に係る半導体装置と同様の構成を有する。
26 下部配線層
28 エッチング遅延層
32 層間絶縁膜
34 レジスト
36 コンタクトホール
38 コンタクトホール
A コンタクトホール形成領域
B コンタクトホール形成領域
101 層間絶縁膜
103 層間絶縁膜
105 Ti膜
107 TiN膜
109 AlCu膜
111 Ti膜
113 TiN膜
115 エッチング調整膜
117 Ti膜
119 TiN膜
121 W膜
141 レジスト
143 開口部
145 開口部
165 エッチング調整膜
1001 層間絶縁膜
1003 層間絶縁膜
1005 Ti膜
1007 TiN膜
1009 AlCu膜
1013 TiN膜
1043 開口部
Claims (11)
- 半導体基板と、
前記半導体基板の上部に設けられており、アルミニウム含有金属膜と、反射防止膜と、エッチング調整膜と、が順に積層されてなる積層体と、
前記積層体上に設けられている層間絶縁膜と、
前記層間絶縁膜および前記エッチング調整膜を貫通し、端面が前記反射防止膜中に位置している導電プラグと、
を備えることを特徴とする半導体装置。 - 請求項1に記載の半導体装置において、
前記反射防止膜の上面から前記導電プラグの端面までの深さは、前記反射防止膜の膜厚の1/10以上9/10以下であることを特徴とする半導体装置。 - 請求項1または2に記載の半導体装置において、
前記エッチング調整膜は、SiON膜であることを特徴とする半導体装置。 - 請求項1乃至3いずれかに記載の半導体装置において、
前記積層体は、同層内に複数設けられており、
前記複数の積層体に含まれる前記エッチング調整膜は、互いに連続した膜からなることを特徴とする半導体装置。 - 請求項1乃至4いずれかに記載の半導体装置において、
前記アルミニウム含有金属膜の側面および前記反射防止膜の側面に前記エッチング調整膜が設けられていることを特徴とする半導体装置。 - 請求項1乃至5いずれかに記載の半導体装置において、
前記層間絶縁膜中に前記導電プラグと同一工程により形成された第二の導電プラグをさらに備え、
前記導電プラグと前記第二の導電プラグとは、互いに長さが異なることを特徴とする半導体装置。 - 半導体基板の上部に、アルミニウム含有金属膜と、反射防止膜と、エッチング調整膜と、が順に積層されてなる積層体を形成する工程と、
前記積層体上に層間絶縁膜を形成する工程と、
前記層間絶縁膜、前記エッチング調整膜および前記反射防止膜を、同一のエッチングガスによりエッチングすることにより、前記層間絶縁膜および前記エッチング調整膜を貫通し、前記反射防止膜中に端部が位置する開口部を形成する工程と、
前記開口部内に導電膜を形成することにより、前記反射防止膜中に端面が位置している導電プラグを形成する工程と、
を含むことを特徴とする半導体装置の製造方法。 - 請求項7に記載の半導体装置の製造方法において、
前記エッチング調整膜を形成する工程は、SiON膜を形成する工程を含むことを特徴とする半導体装置の製造方法。 - 請求項7または8に記載の半導体装置の製造方法において、
前記積層体を形成する工程は、前記アルミニウム含有金属膜の側面、前記反射防止膜の上面および側面に前記エッチング調整膜を設ける工程を含む
ことを特徴とする半導体装置の製造方法。 - 請求項7乃至9いずれかに記載の半導体装置の製造方法において、
前記層間絶縁膜を、前記開口部を形成する工程と同一工程でエッチングすることにより、前記層間絶縁膜中に前記開口部と深さの異なる第二の開口部を形成し、前記第二の開口部内に、前記導電プラグと長さの異なる第二の導電プラグを形成する工程と、
をさらに含むことを特徴とする半導体装置の製造方法。 - 請求項7乃至10いずれかに記載の半導体装置の製造方法において、
前記エッチングガスは、CxFy(xは4以上の実数、yは正の実数)の一般式で表されるフルオロカーボン系化合物を含むエッチングガスである
ことを特徴とする半導体装置の製造方法。
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004283606A JP4447419B2 (ja) | 2004-09-29 | 2004-09-29 | 半導体装置の製造方法 |
US11/235,309 US7646096B2 (en) | 2004-09-29 | 2005-09-27 | Semiconductor device and manufacturing method thereof |
CN201010583222.2A CN102097365B (zh) | 2004-09-29 | 2005-09-28 | 制造半导体器件的方法 |
CNA2005101133603A CN1763944A (zh) | 2004-09-29 | 2005-09-28 | 半导体器件及其制造方法 |
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JP2004283606A JP4447419B2 (ja) | 2004-09-29 | 2004-09-29 | 半導体装置の製造方法 |
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Publication Number | Publication Date |
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JP2006100503A true JP2006100503A (ja) | 2006-04-13 |
JP4447419B2 JP4447419B2 (ja) | 2010-04-07 |
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JP2004283606A Expired - Fee Related JP4447419B2 (ja) | 2004-09-29 | 2004-09-29 | 半導体装置の製造方法 |
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US (1) | US7646096B2 (ja) |
JP (1) | JP4447419B2 (ja) |
CN (2) | CN102097365B (ja) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2017045871A (ja) * | 2015-08-27 | 2017-03-02 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法およびドライエッチングの終点検出方法 |
KR20220049616A (ko) * | 2019-11-05 | 2022-04-21 | 베이징 나우라 마이크로일렉트로닉스 이큅먼트 씨오., 엘티디. | 에칭 방법, 에어갭형 유전층 및 동적 랜덤 액세스 메모리 |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE102007004860B4 (de) * | 2007-01-31 | 2008-11-06 | Advanced Micro Devices, Inc., Sunnyvale | Verfahren zur Herstellung einer Kupfer-basierten Metallisierungsschicht mit einer leitenden Deckschicht durch ein verbessertes Integrationsschema |
US20100163759A1 (en) * | 2008-12-31 | 2010-07-01 | Stmicroelectronics S.R.L. | Radiation sensor with photodiodes being integrated on a semiconductor substrate and corresponding integration process |
CN104124204A (zh) * | 2013-04-28 | 2014-10-29 | 无锡华润上华科技有限公司 | 一种改善半导体工艺流程中铝残留的方法 |
US20180277387A1 (en) * | 2014-08-06 | 2018-09-27 | American Air Liquide, Inc. | Gases for low damage selective silicon nitride etching |
CN105633007A (zh) * | 2014-11-06 | 2016-06-01 | 中芯国际集成电路制造(上海)有限公司 | 金属连线制备方法 |
Family Cites Families (29)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH07249682A (ja) | 1994-03-08 | 1995-09-26 | Sony Corp | 半導体装置 |
JP3351177B2 (ja) | 1995-06-28 | 2002-11-25 | ソニー株式会社 | 接続孔を形成する工程を有する配線構造の形成方法 |
US5961791A (en) * | 1997-02-26 | 1999-10-05 | Motorola, Inc. | Process for fabricating a semiconductor device |
JPH1126577A (ja) | 1997-07-01 | 1999-01-29 | Sony Corp | 配線間コンタクトおよびその形成方法 |
KR100256110B1 (ko) * | 1997-08-16 | 2000-05-01 | 윤종용 | 반도체 장치의 상호연결 및 그의 형성 방법 |
JP3722610B2 (ja) | 1998-01-14 | 2005-11-30 | 株式会社リコー | 半導体装置の製造方法 |
JPH11265938A (ja) * | 1998-03-18 | 1999-09-28 | Toshiba Corp | 半導体装置及びその製造方法 |
JP3677644B2 (ja) * | 1998-09-01 | 2005-08-03 | 日本テキサス・インスツルメンツ株式会社 | 半導体装置の製造方法 |
US6174800B1 (en) * | 1998-09-08 | 2001-01-16 | Taiwan Semiconductor Manufacturing Company | Via formation in a poly(arylene ether) inter metal dielectric layer |
JP2000091318A (ja) * | 1998-09-09 | 2000-03-31 | Fujitsu Ltd | 半導体装置の製造方法 |
JP3257533B2 (ja) * | 1999-01-25 | 2002-02-18 | 日本電気株式会社 | 無機反射防止膜を使った配線形成方法 |
US6008075A (en) | 1999-02-11 | 1999-12-28 | Vanguard International Semiconductor Corporation | Method for simultaneous formation of contacts between metal layers and fuse windows in semiconductor manufacturing |
JP4201421B2 (ja) | 1999-02-17 | 2008-12-24 | 株式会社ルネサステクノロジ | 半導体装置の製造方法 |
KR100772736B1 (ko) * | 2000-03-13 | 2007-11-01 | 엔엑스피 비 브이 | 반도체 디바이스 제조 방법 |
US6531404B1 (en) * | 2000-08-04 | 2003-03-11 | Applied Materials Inc. | Method of etching titanium nitride |
JP2002170885A (ja) * | 2000-12-04 | 2002-06-14 | Fujitsu Ltd | 半導体装置の製造方法 |
JP2002190520A (ja) | 2000-12-21 | 2002-07-05 | Nec Yamagata Ltd | 半導体集積回路装置およびその製造方法 |
JP2002217288A (ja) * | 2001-01-17 | 2002-08-02 | Mitsubishi Electric Corp | 半導体装置およびその製造方法 |
JP4211235B2 (ja) | 2001-04-24 | 2009-01-21 | トヨタ自動車株式会社 | コンタクトホール形成方法 |
JP2003031576A (ja) * | 2001-07-17 | 2003-01-31 | Nec Corp | 半導体素子及びその製造方法 |
US6617231B1 (en) * | 2002-03-06 | 2003-09-09 | Texas Instruments Incorporated | Method for forming a metal extrusion free via |
US7388633B2 (en) * | 2002-12-13 | 2008-06-17 | Victor Company Of Japan, Limited | Reflective liquid crystal display |
JP2004266005A (ja) * | 2003-02-28 | 2004-09-24 | Renesas Technology Corp | 半導体装置の製造方法 |
US6876027B2 (en) * | 2003-04-10 | 2005-04-05 | Taiwan Semiconductor Manufacturing Company | Method of forming a metal-insulator-metal capacitor structure in a copper damascene process sequence |
KR100555515B1 (ko) * | 2003-08-27 | 2006-03-03 | 삼성전자주식회사 | 코발트층 캡핑막을 갖는 반도체 소자 및 그 제조방법 |
US7045455B2 (en) * | 2003-10-23 | 2006-05-16 | Chartered Semiconductor Manufacturing Ltd. | Via electromigration improvement by changing the via bottom geometric profile |
KR100570059B1 (ko) * | 2003-12-15 | 2006-04-10 | 주식회사 하이닉스반도체 | 반도체 소자의 메탈콘택 형성 방법 |
US20050241671A1 (en) * | 2004-04-29 | 2005-11-03 | Dong Chun C | Method for removing a substance from a substrate using electron attachment |
US7655570B2 (en) * | 2005-01-13 | 2010-02-02 | Tokyo Electron Limited | Etching method, program, computer readable storage medium and plasma processing apparatus |
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2004
- 2004-09-29 JP JP2004283606A patent/JP4447419B2/ja not_active Expired - Fee Related
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2005
- 2005-09-27 US US11/235,309 patent/US7646096B2/en active Active
- 2005-09-28 CN CN201010583222.2A patent/CN102097365B/zh not_active Expired - Fee Related
- 2005-09-28 CN CNA2005101133603A patent/CN1763944A/zh active Pending
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2017045871A (ja) * | 2015-08-27 | 2017-03-02 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法およびドライエッチングの終点検出方法 |
KR20220049616A (ko) * | 2019-11-05 | 2022-04-21 | 베이징 나우라 마이크로일렉트로닉스 이큅먼트 씨오., 엘티디. | 에칭 방법, 에어갭형 유전층 및 동적 랜덤 액세스 메모리 |
JP2022554086A (ja) * | 2019-11-05 | 2022-12-28 | ベイジン・ナウラ・マイクロエレクトロニクス・イクイップメント・カンパニー・リミテッド | エッチング方法、空隙誘電体層、及びダイナミックランダムアクセスメモリ |
KR102532136B1 (ko) | 2019-11-05 | 2023-05-12 | 베이징 나우라 마이크로일렉트로닉스 이큅먼트 씨오., 엘티디. | 에칭 방법, 에어갭형 유전층 및 동적 랜덤 액세스 메모리 |
JP7352732B2 (ja) | 2019-11-05 | 2023-09-28 | ベイジン・ナウラ・マイクロエレクトロニクス・イクイップメント・カンパニー・リミテッド | エッチング方法、空隙誘電体層、及びダイナミックランダムアクセスメモリ |
US11948805B2 (en) | 2019-11-05 | 2024-04-02 | Beijing Naura Microelectronics Equipment Co., Ltd. | Etching method, air-gap dielectric layer, and dynamic random-access memory |
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CN1763944A (zh) | 2006-04-26 |
JP4447419B2 (ja) | 2010-04-07 |
US20060065979A1 (en) | 2006-03-30 |
CN102097365A (zh) | 2011-06-15 |
CN102097365B (zh) | 2015-09-16 |
US7646096B2 (en) | 2010-01-12 |
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