JP2008270522A - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
- Publication number
- JP2008270522A JP2008270522A JP2007111524A JP2007111524A JP2008270522A JP 2008270522 A JP2008270522 A JP 2008270522A JP 2007111524 A JP2007111524 A JP 2007111524A JP 2007111524 A JP2007111524 A JP 2007111524A JP 2008270522 A JP2008270522 A JP 2008270522A
- Authority
- JP
- Japan
- Prior art keywords
- film
- wiring
- etching
- mask
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 44
- 238000004519 manufacturing process Methods 0.000 title claims description 36
- 238000005530 etching Methods 0.000 claims abstract description 114
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims abstract description 64
- 229910052721 tungsten Inorganic materials 0.000 claims abstract description 64
- 239000010937 tungsten Substances 0.000 claims abstract description 64
- 230000004888 barrier function Effects 0.000 claims abstract description 28
- 238000000059 patterning Methods 0.000 claims abstract description 18
- 238000000206 photolithography Methods 0.000 claims abstract description 7
- 239000011229 interlayer Substances 0.000 claims description 34
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 30
- 238000000034 method Methods 0.000 claims description 29
- 230000015572 biosynthetic process Effects 0.000 claims description 27
- 239000000460 chlorine Substances 0.000 claims description 12
- 238000001020 plasma etching Methods 0.000 claims description 11
- 229910052731 fluorine Inorganic materials 0.000 claims description 10
- 239000011737 fluorine Substances 0.000 claims description 10
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 claims description 9
- 239000010410 layer Substances 0.000 claims description 8
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 claims description 4
- 229910052801 chlorine Inorganic materials 0.000 claims description 4
- 239000004020 conductor Substances 0.000 claims description 4
- 230000003667 anti-reflective effect Effects 0.000 claims 1
- 230000006866 deterioration Effects 0.000 abstract description 3
- 125000001153 fluoro group Chemical class F* 0.000 abstract 2
- KZBUYRJDOAKODT-UHFFFAOYSA-N Chlorine Chemical compound ClCl KZBUYRJDOAKODT-UHFFFAOYSA-N 0.000 abstract 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 abstract 1
- 150000004767 nitrides Chemical class 0.000 abstract 1
- 239000010936 titanium Substances 0.000 abstract 1
- 229910052719 titanium Inorganic materials 0.000 abstract 1
- 230000008569 process Effects 0.000 description 18
- 229910052751 metal Inorganic materials 0.000 description 11
- 239000002184 metal Substances 0.000 description 11
- 239000000758 substrate Substances 0.000 description 9
- 229910052581 Si3N4 Inorganic materials 0.000 description 7
- 238000010586 diagram Methods 0.000 description 7
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 7
- 238000005229 chemical vapour deposition Methods 0.000 description 6
- 230000007423 decrease Effects 0.000 description 5
- 238000004544 sputter deposition Methods 0.000 description 5
- 238000004380 ashing Methods 0.000 description 3
- 238000004140 cleaning Methods 0.000 description 3
- 230000009467 reduction Effects 0.000 description 3
- 239000003870 refractory metal Substances 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 229910000838 Al alloy Inorganic materials 0.000 description 1
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 230000001133 acceleration Effects 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 150000002221 fluorine Chemical class 0.000 description 1
- 238000005755 formation reaction Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 239000005368 silicate glass Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76885—By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31127—Etching organic layers
- H01L21/31133—Etching organic layers by chemical means
- H01L21/31138—Etching organic layers by chemical means by dry-etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
- H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Plasma & Fusion (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Drying Of Semiconductors (AREA)
Abstract
【解決手段】先ず、下地100を用意して、下地上に、バリア膜120、配線膜130及びマスク膜140を順次に積層する。バリア膜及びマスク膜が窒化チタンであり、配線膜がタングステンである。次に、マスク膜上に、反射防止膜150を塗布する。次に、反射防止膜上に、レジスト膜を形成した後、フォトリソグラフィによりパターニングして、レジストマスク160を形成する。レジストマスクは、配線形成領域105を覆い、かつ配線非形成領域107を露出する。次に、フッ素系ガスを用いたエッチングにより反射防止膜のパターニングを行う。次に、塩素系ガスを用いたエッチングによりマスク膜のパターニングを行う。次に、フッ素系ガスを用いたエッチングにより配線膜のパターニングを行う。
【選択図】図2
Description
70、70a、70b、70c 層間絶縁膜
71、71a、71b、71c スルーホール
72、72a、72b、72c 導電プラグ
74a、74b 配線パターン
100、100a 下地
105 配線形成領域
107 配線非形成領域
110 多層膜
120 バリア膜
121、131、141、151 露出部分
122、142、152、162 エッチング残部
130 配線膜
132 配線(エッチング残部)
140 マスク膜
150 反射防止膜
160 レジストマスク
170 層間絶縁膜
171 スルーホール
180 上層メタル配線
182 窒化チタン(TiN)膜
184 メタル膜
Claims (15)
- 下地を用意する工程と、
前記下地上に、バリア膜、配線膜及びマスク膜が順次に積層された多層膜であって、前記バリア膜及びマスク膜が窒化チタン膜であり、前記配線膜がタングステン膜である当該多層膜を形成する工程と、
前記マスク膜上に、配線形成領域を覆い、かつ配線非形成領域を露出するレジストマスクを形成する工程と、
タングステンに対する窒化チタンのエッチング選択比が大きい第1のガスを用いたエッチングにより前記マスク膜のパターニングを行って、前記配線非形成領域の、前記マスク膜の部分を除去して、前記配線形成領域に前記マスク膜のエッチング残部を残存させる工程と、
窒化チタンに対するタングステンのエッチング選択比が大きい第2のガスを用いたエッチングにより前記配線膜のパターニングを行って、前記配線非形成領域の、前記配線膜の部分を除去して、前記配線形成領域に前記配線膜のエッチング残部を残存させて配線を形成する工程と
を備えることを特徴とする半導体装置の製造方法。 - 前記第1のガスとして、塩素系ガスを用い、
前記第2のガスとして、フッ素系ガスを用いる
ことを特徴とする請求項1に記載の半導体装置の製造方法。 - 前記第1のガスとして、Cl2を含む塩素系ガスを用い、
前記第2のガスとして、SF6を含むフッ素系ガスを用いる
ことを特徴とする請求項1に記載の半導体装置の製造方法。 - 前記配線を形成した後、
前記レジストマスクのエッチング残部を除去し、さらに前記配線上の前記マスク膜のエッチング残部及び前記配線非形成領域のバリア膜の部分をエッチングにより除去する工程
を行うことを特徴とする請求項1〜3のいずれか一項に記載の半導体装置の製造方法。 - 前記マスク膜のエッチング残部及び前記配線非形成領域のバリア膜の部分のエッチングを、前記第1のガスを用いて行うことを特徴とする請求項4に記載の半導体装置の製造方法。
- 前記レジストマスクのエッチング残部、前記配線上の前記マスク膜のエッチング残部及び前記配線非形成領域のバリア膜の部分を除去した後、
前記下地上に、前記配線を埋め込む層間絶縁膜を形成する工程と、
前記層間絶縁膜に前記配線を露出するスルーホールを形成する工程と、
前記スルーホールを導電体で埋め込むとともに、前記層間絶縁膜上に上層配線を形成する工程と
を行うことを特徴とする請求項4又は5に記載の半導体装置の製造方法。 - 前記マスク膜上に、レジストマスクを形成する工程に替えて、
前記マスク膜上に、反射防止膜を塗布する工程と、
該反射防止膜上に、レジストを塗布することによりレジスト膜を形成した後、フォトリソグラフィによりパターニングして、配線形成領域を覆い、かつ配線非形成領域を露出するレジストマスクを形成する工程と、
フッ素系ガスを用いたエッチングにより前記反射防止膜のパターニングを行って、前記配線非形成領域の、前記反射防止膜の部分を除去して、前記配線形成領域に前記反射防止膜のエッチング残部を残存させる工程と
を行うことを特徴とする請求項1〜3のいずれか一項に記載の半導体装置の製造方法。 - 前記反射防止膜をパターニングするにあたり、CHF3を含むフッ素系ガスを用いることを特徴とする請求項7に記載の半導体装置の製造方法。
- 前記反射防止膜をパターニングするにあたり、バイアス電力を30〜50Wとして反応性イオンエッチングを行うことを特徴とする請求項7又は8に記載の半導体装置の製造方法。
- 前記反射防止膜をパターニングするにあたり、
CHF3を含むフッ素系ガスとして、さらにCF4を含むガスを用い、及び
前記CHF3の流量を、前記CF4の流量の少なくとも6倍にする
ことを特徴とする請求項7〜9のいずれか一項に記載の半導体装置の製造方法。 - 前記配線を形成した後、
前記レジストマスク及び反射防止膜のエッチング残部を除去し、さらに前記配線上の前記マスク膜のエッチング残部及び前記配線非形成領域のバリア膜の部分をエッチングにより除去する工程
を行うことを特徴とする請求項7〜10のいずれか一項に記載の半導体装置の製造方法。 - 前記マスク膜のエッチング残部及び前記配線非形成領域のバリア膜の部分のエッチングを、前記第1のガスを用いて行うことを特徴とする請求項11に記載の半導体装置の製造方法。
- 前記レジストマスク及び反射防止膜のエッチング残部、前記配線上の前記マスク膜のエッチング残部及び前記配線非形成領域のバリア膜の部分を除去した後、
前記下地上に、前記配線を埋め込む層間絶縁膜を形成する工程と、
前記層間絶縁膜に前記配線を露出するスルーホールを形成する工程と、
前記スルーホールを導電体で埋め込むとともに、前記層間絶縁膜上に上層配線を形成する工程と
を行うことを特徴とする請求項11又は12に記載の半導体装置の製造方法。 - 前記配線の幅を最大でも150nmとする
ことを特徴とする請求項1〜13のいずれか一項に記載の半導体装置の製造方法。 - 前記配線膜の厚みを300〜400nmとする
ことを特徴とする請求項1〜14のいずれか一項に記載の半導体装置の製造方法。
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007111524A JP2008270522A (ja) | 2007-04-20 | 2007-04-20 | 半導体装置の製造方法 |
US12/078,086 US7704891B2 (en) | 2007-04-20 | 2008-03-27 | Method of producing semiconductor device |
KR1020080030319A KR20080094560A (ko) | 2007-04-20 | 2008-04-01 | 반도체 장치의 제조 방법 |
CNA2008100891439A CN101290906A (zh) | 2007-04-20 | 2008-04-01 | 半导体器件的制造方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007111524A JP2008270522A (ja) | 2007-04-20 | 2007-04-20 | 半導体装置の製造方法 |
Publications (1)
Publication Number | Publication Date |
---|---|
JP2008270522A true JP2008270522A (ja) | 2008-11-06 |
Family
ID=39872636
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2007111524A Pending JP2008270522A (ja) | 2007-04-20 | 2007-04-20 | 半導体装置の製造方法 |
Country Status (4)
Country | Link |
---|---|
US (1) | US7704891B2 (ja) |
JP (1) | JP2008270522A (ja) |
KR (1) | KR20080094560A (ja) |
CN (1) | CN101290906A (ja) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2011228424A (ja) * | 2010-04-19 | 2011-11-10 | Oki Semiconductor Co Ltd | 半導体装置の製造方法 |
JP7427155B2 (ja) | 2019-08-23 | 2024-02-05 | 東京エレクトロン株式会社 | 別の金属及び誘電体に対してチューニング可能な選択性を有するチタン含有材料層の非プラズマエッチング |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH08186120A (ja) * | 1994-12-28 | 1996-07-16 | Nec Corp | 半導体装置の製造方法 |
JP2006032801A (ja) * | 2004-07-20 | 2006-02-02 | Nec Electronics Corp | 半導体装置の製造方法 |
JP2006041364A (ja) * | 2004-07-29 | 2006-02-09 | Seiko Epson Corp | 配線の形成方法及び、電子デバイスの製造方法 |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH06275625A (ja) | 1993-03-23 | 1994-09-30 | Matsushita Electric Ind Co Ltd | 高融点金属を含む配線及びその形成方法 |
US6291361B1 (en) * | 1999-03-24 | 2001-09-18 | Conexant Systems, Inc. | Method and apparatus for high-resolution in-situ plasma etching of inorganic and metal films |
-
2007
- 2007-04-20 JP JP2007111524A patent/JP2008270522A/ja active Pending
-
2008
- 2008-03-27 US US12/078,086 patent/US7704891B2/en not_active Expired - Fee Related
- 2008-04-01 KR KR1020080030319A patent/KR20080094560A/ko not_active Application Discontinuation
- 2008-04-01 CN CNA2008100891439A patent/CN101290906A/zh active Pending
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH08186120A (ja) * | 1994-12-28 | 1996-07-16 | Nec Corp | 半導体装置の製造方法 |
JP2006032801A (ja) * | 2004-07-20 | 2006-02-02 | Nec Electronics Corp | 半導体装置の製造方法 |
JP2006041364A (ja) * | 2004-07-29 | 2006-02-09 | Seiko Epson Corp | 配線の形成方法及び、電子デバイスの製造方法 |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2011228424A (ja) * | 2010-04-19 | 2011-11-10 | Oki Semiconductor Co Ltd | 半導体装置の製造方法 |
JP7427155B2 (ja) | 2019-08-23 | 2024-02-05 | 東京エレクトロン株式会社 | 別の金属及び誘電体に対してチューニング可能な選択性を有するチタン含有材料層の非プラズマエッチング |
Also Published As
Publication number | Publication date |
---|---|
KR20080094560A (ko) | 2008-10-23 |
US7704891B2 (en) | 2010-04-27 |
US20080261391A1 (en) | 2008-10-23 |
CN101290906A (zh) | 2008-10-22 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6800550B2 (en) | Method for forming t-shaped conductive wires of semiconductor device utilizing notching phenomenon | |
US7482279B2 (en) | Method for fabricating semiconductor device using ArF photolithography capable of protecting tapered profile of hard mask | |
JP2006005344A (ja) | 半導体パターン形成方法 | |
JP2006339584A (ja) | 半導体装置およびその製造方法 | |
JP2006179853A (ja) | 半導体素子のキャパシタストレージノードの形成方法 | |
KR100652791B1 (ko) | 반도체소자 제조 방법 | |
JP2006222208A (ja) | 半導体装置の製造方法 | |
JP2008270522A (ja) | 半導体装置の製造方法 | |
JP2006216964A (ja) | ビアキャッピング保護膜を使用する半導体素子のデュアルダマシン配線の製造方法 | |
US6586324B2 (en) | Method of forming interconnects | |
JPH07221110A (ja) | 半導体装置の配線構造とその製造方法 | |
JP2007027234A (ja) | 半導体装置及びその製造方法 | |
KR20030002119A (ko) | 듀얼 다마신 공정에 의한 비아홀 형성 방법 | |
KR100421280B1 (ko) | 반도체 소자의 다층 금속 배선 형성 방법 | |
KR100539446B1 (ko) | 반도체 소자의 듀얼 다마신 패턴 형성방법 | |
KR20060023004A (ko) | 반도체소자의 콘택 플러그 형성 방법 | |
JP4768732B2 (ja) | 半導体装置及びその製造方法、ドライエッチング方法、配線材料の作製方法、並びにエッチング装置 | |
KR20050116490A (ko) | 반도체 소자의 콘택 플러그 형성 방법 | |
KR100291189B1 (ko) | 반도체 장치 제조 방법 | |
KR100685137B1 (ko) | 구리 금속 배선의 형성 방법 및 그에 의해 형성된 구리금속 배선을 포함하는 반도체 소자 | |
JP2007115889A (ja) | 半導体装置の製造方法 | |
JP2009088013A (ja) | 半導体装置の製造方法 | |
KR20050116483A (ko) | 반도체소자의 콘택홀 형성 방법 | |
KR20060029007A (ko) | 반도체 소자 제조 방법 | |
KR20050049003A (ko) | 이중 개구부를 갖는 반도체 소자의 제조 방법 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A711 | Notification of change in applicant |
Free format text: JAPANESE INTERMEDIATE CODE: A712 Effective date: 20081218 |
|
RD03 | Notification of appointment of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7423 Effective date: 20090226 |
|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20100319 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20120629 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20120710 |
|
A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20121113 |