JP2005129942A - 不揮発性メモリ素子の製造方法 - Google Patents
不揮発性メモリ素子の製造方法 Download PDFInfo
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- JP2005129942A JP2005129942A JP2004305876A JP2004305876A JP2005129942A JP 2005129942 A JP2005129942 A JP 2005129942A JP 2004305876 A JP2004305876 A JP 2004305876A JP 2004305876 A JP2004305876 A JP 2004305876A JP 2005129942 A JP2005129942 A JP 2005129942A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 21
- 230000002093 peripheral effect Effects 0.000 claims abstract description 16
- 238000000151 deposition Methods 0.000 claims abstract description 13
- 239000000758 substrate Substances 0.000 claims abstract description 13
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 9
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 9
- 239000010703 silicon Substances 0.000 claims abstract description 9
- 238000005530 etching Methods 0.000 claims abstract description 8
- 238000000034 method Methods 0.000 claims description 20
- 239000000463 material Substances 0.000 claims description 15
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 6
- 229920005591 polysilicon Polymers 0.000 claims description 6
- 238000005468 ion implantation Methods 0.000 claims description 4
- 230000008021 deposition Effects 0.000 claims description 3
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 claims description 3
- 229910021342 tungsten silicide Inorganic materials 0.000 claims description 3
- 229910018072 Al 2 O 3 Inorganic materials 0.000 claims description 2
- 239000000126 substance Substances 0.000 abstract description 5
- 230000008878 coupling Effects 0.000 description 7
- 238000010168 coupling process Methods 0.000 description 7
- 238000005859 coupling reaction Methods 0.000 description 7
- 239000004065 semiconductor Substances 0.000 description 5
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- 230000005684 electric field Effects 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- 238000002347 injection Methods 0.000 description 3
- 239000007924 injection Substances 0.000 description 3
- 230000010354 integration Effects 0.000 description 3
- 230000005641 tunneling Effects 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 239000005368 silicate glass Substances 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B99/00—Subject matter not provided for in other groups of this subclass
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42324—Gate electrodes for transistors with a floating gate
- H01L29/42336—Gate electrodes for transistors with a floating gate with one gate at least partly formed in a trench
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
- H10B41/42—Simultaneous manufacture of periphery and memory cells
- H10B41/43—Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
Abstract
【解決手段】周辺回路領域のシリコン基板100に第一深さの第一トレンチを形成し、埋め込み酸化膜130で平坦化する工程と、セル領域のシリコン基板に第二深さの第二トレンチを形成する工程と、セル領域にチャネルイオン注入し、第二トレンチ内部にトンネル酸化膜140を形成し、フローティングゲート物質を蒸着する工程と、フローティングゲート物質をエッチングしフローティングゲート150’を形成する工程と、セル領域にソース/ドレイン160接合を形成する工程と、周辺回路領域及びセル領域にウェルを形成し誘電体膜170を蒸着する工程と、セル領域のチャネル部位だけ誘電体膜を残してゲート物質を蒸着する工程と、ゲート物質をエッチングし周辺回路領域にゲートを形成し、セル領域にコントロールゲート180’形成する工程とを含む。
【選択図】図9
Description
Claims (9)
- 周辺回路領域のシリコン基板に第一の深さの第一トレンチを形成した後、埋め込み酸化膜で埋め込んで平坦化する工程と、
セル領域のシリコン基板に第二の深さの第二トレンチを形成する工程と、
前記セル領域にチャネルイオン注入を施し、前記第二トレンチの内部にトンネル酸化膜を形成して、フローティングゲート物質を蒸着する工程と、
前記フローティングゲート物質をエッチングしてフローティングゲートを形成する工程と、
前記セル領域にソース/ドレイン接合を形成する工程と、
前記周辺回路領域及び前記セル領域にウェルを形成して誘電体膜を蒸着する工程と、
前記セル領域のチャネル部位のみに誘電体膜を残してゲート物質を蒸着する工程と、
前記ゲート物質をエッチングして周辺回路領域にゲートを形成し、セル領域にコントロールゲートを形成する工程と、を含むことを特徴とする不揮発性メモリ素子の製造方法。 - 前記第二トレンチの幅は、フローティングゲート物質の蒸着厚の略1/2の厚さに形成することを特徴とする請求項1に記載の不揮発性メモリ素子の製造方法。
- 前記フローティングゲートは、非ドープポリシリコンまたは非晶質シリコンで形成することを特徴とする請求項1に記載の不揮発性メモリ素子の製造方法。
- 前記フローティングゲートは、前記第二トレンチの内部に凹状に形成されることを特徴とする請求項1に記載の不揮発性メモリ素子の製造方法。
- 前記埋め込み酸化膜は、HDP酸化膜またはUSG膜であることを特徴とする請求項1に記載の不揮発性メモリ素子の製造方法。
- 前記誘電体膜は、ONO誘電体膜またはAl2O3またはHfO2の中のいずれか1の高誘電体膜であることを特徴とする請求項1に記載の不揮発性メモリ素子の製造方法。
- 前記誘電体膜は、セル領域のコントロールゲートより略0.01〜略0.1μmオーバーラップするようにすることを特徴とする請求項1に記載の不揮発性メモリ素子の製造方法。
- 前記ゲート物質は、ポリシリコン、非晶質シリコンまたはタングステンシリサイドの中から選択されたいずれか1で形成されることを特徴とする請求項1に記載の不揮発性メモリ素子の製造方法。
- 前記セル領域のソース/ドレインは、前記第二の深さのトレンチと同じ深さに形成されることを特徴とする請求項1に記載の不揮発性メモリ素子の製造方法。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020030073987A KR100642901B1 (ko) | 2003-10-22 | 2003-10-22 | 비휘발성 메모리 소자의 제조 방법 |
KR2003-073987 | 2003-10-22 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2005129942A true JP2005129942A (ja) | 2005-05-19 |
JP4955203B2 JP4955203B2 (ja) | 2012-06-20 |
Family
ID=34511016
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2004305876A Active JP4955203B2 (ja) | 2003-10-22 | 2004-10-20 | 不揮発性メモリ素子の製造方法 |
Country Status (4)
Country | Link |
---|---|
US (1) | US20050090059A1 (ja) |
JP (1) | JP4955203B2 (ja) |
KR (1) | KR100642901B1 (ja) |
CN (1) | CN1333458C (ja) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2009253266A (ja) * | 2008-04-10 | 2009-10-29 | Nanya Technology Corp | 2ビットu字型メモリ構造及びその製作方法 |
US7635891B2 (en) | 2006-11-30 | 2009-12-22 | Kabushiki Kaisha Toshiba | Semiconductor device |
JP2014143377A (ja) * | 2013-01-25 | 2014-08-07 | Seiko Instruments Inc | 半導体不揮発性メモリ |
Families Citing this family (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100635199B1 (ko) | 2005-05-12 | 2006-10-16 | 주식회사 하이닉스반도체 | 플래쉬 메모리 소자 및 그의 제조방법 |
US7342272B2 (en) | 2005-08-31 | 2008-03-11 | Micron Technology, Inc. | Flash memory with recessed floating gate |
KR100726359B1 (ko) * | 2005-11-01 | 2007-06-11 | 삼성전자주식회사 | 리세스된 채널을 구비하는 비휘발성 메모리 장치의 형성방법 및 그에 의해 형성된 장치 |
US7531409B2 (en) | 2005-11-01 | 2009-05-12 | Samsung Electronics Co., Ltd. | Fabrication method and structure for providing a recessed channel in a nonvolatile memory device |
KR100731076B1 (ko) * | 2005-12-29 | 2007-06-22 | 동부일렉트로닉스 주식회사 | 수직형 스플리트 게이트 구조의 플래시 메모리 소자 및 그제조 방법 |
KR100812237B1 (ko) * | 2006-08-25 | 2008-03-10 | 삼성전자주식회사 | 임베디드 플래시 메모리 장치의 제조 방법 |
KR101030297B1 (ko) * | 2008-07-30 | 2011-04-20 | 주식회사 동부하이텍 | 반도체 메모리 소자 및 그 제조 방법 |
CN102201411B (zh) * | 2010-03-25 | 2013-04-03 | 上海丽恒光微电子科技有限公司 | 叠栅非易失性快闪存储单元、存储器件及其制造方法 |
CN101866931A (zh) * | 2010-05-19 | 2010-10-20 | 中国科学院微电子研究所 | 半导体结构及其形成方法 |
KR101802371B1 (ko) * | 2011-05-12 | 2017-11-29 | 에스케이하이닉스 주식회사 | 반도체 셀 및 그 형성 방법 |
CN102881693B (zh) * | 2012-10-25 | 2017-05-24 | 上海华虹宏力半导体制造有限公司 | 存储器件及其制作方法 |
CN105576016B (zh) * | 2014-10-09 | 2019-02-12 | 中芯国际集成电路制造(上海)有限公司 | 栅极结构、其制作方法及闪存器件 |
CN114864590A (zh) * | 2015-08-24 | 2022-08-05 | 蓝枪半导体有限责任公司 | 存储器元件及其制造方法 |
CN106783865B (zh) * | 2016-11-28 | 2019-02-15 | 武汉新芯集成电路制造有限公司 | 一种存储单元的制作方法 |
US10879251B2 (en) * | 2017-04-27 | 2020-12-29 | Taiwan Semiconductor Manufacturing Co., Ltd. | Integrated circuit and manufacturing method thereof |
CN112928064A (zh) * | 2021-01-27 | 2021-06-08 | 中国科学院微电子研究所 | 位线两侧气隙及半导体结构的制造方法 |
CN113939906A (zh) * | 2021-08-31 | 2022-01-14 | 长江存储科技有限责任公司 | 半导体结构、制作方法及三维存储器 |
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JPS5931064A (ja) * | 1982-08-13 | 1984-02-18 | Oki Electric Ind Co Ltd | Mos型半導体装置 |
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- 2003-10-22 KR KR1020030073987A patent/KR100642901B1/ko active IP Right Grant
-
2004
- 2004-10-19 US US10/968,200 patent/US20050090059A1/en not_active Abandoned
- 2004-10-20 JP JP2004305876A patent/JP4955203B2/ja active Active
- 2004-10-22 CN CNB2004100981329A patent/CN1333458C/zh active Active
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US7635891B2 (en) | 2006-11-30 | 2009-12-22 | Kabushiki Kaisha Toshiba | Semiconductor device |
JP2009253266A (ja) * | 2008-04-10 | 2009-10-29 | Nanya Technology Corp | 2ビットu字型メモリ構造及びその製作方法 |
JP2014143377A (ja) * | 2013-01-25 | 2014-08-07 | Seiko Instruments Inc | 半導体不揮発性メモリ |
Also Published As
Publication number | Publication date |
---|---|
KR20050038752A (ko) | 2005-04-29 |
KR100642901B1 (ko) | 2006-11-03 |
US20050090059A1 (en) | 2005-04-28 |
JP4955203B2 (ja) | 2012-06-20 |
CN1610100A (zh) | 2005-04-27 |
CN1333458C (zh) | 2007-08-22 |
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