JP2004538634A - ひずみ層を有する半導体基板及びその形成方法 - Google Patents

ひずみ層を有する半導体基板及びその形成方法 Download PDF

Info

Publication number
JP2004538634A
JP2004538634A JP2003519978A JP2003519978A JP2004538634A JP 2004538634 A JP2004538634 A JP 2004538634A JP 2003519978 A JP2003519978 A JP 2003519978A JP 2003519978 A JP2003519978 A JP 2003519978A JP 2004538634 A JP2004538634 A JP 2004538634A
Authority
JP
Japan
Prior art keywords
layer
strained
strain layer
compressive strain
strain
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2003519978A
Other languages
English (en)
Japanese (ja)
Other versions
JP2004538634A5 (enExample
Inventor
ミンジョー エル リー
クリストファー ダブリュ レイツ
ユージン エィ フィッツジェラルド
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Massachusetts Institute of Technology
Original Assignee
Massachusetts Institute of Technology
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Massachusetts Institute of Technology filed Critical Massachusetts Institute of Technology
Publication of JP2004538634A publication Critical patent/JP2004538634A/ja
Publication of JP2004538634A5 publication Critical patent/JP2004538634A5/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/751—Insulated-gate field-effect transistors [IGFET] having composition variations in the channel regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/80—FETs having rectifying junction gate electrodes
    • H10D30/801—FETs having heterojunction gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0167—Manufacturing their channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/85—Complementary IGFETs, e.g. CMOS

Landscapes

  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Recrystallisation Techniques (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
JP2003519978A 2001-08-06 2002-08-02 ひずみ層を有する半導体基板及びその形成方法 Pending JP2004538634A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US31034601P 2001-08-06 2001-08-06
PCT/US2002/024594 WO2003015142A2 (en) 2001-08-06 2002-08-02 Formation of planar strained layers

Publications (2)

Publication Number Publication Date
JP2004538634A true JP2004538634A (ja) 2004-12-24
JP2004538634A5 JP2004538634A5 (enExample) 2005-12-22

Family

ID=23202088

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2003519978A Pending JP2004538634A (ja) 2001-08-06 2002-08-02 ひずみ層を有する半導体基板及びその形成方法

Country Status (4)

Country Link
US (3) US6730551B2 (enExample)
EP (1) EP1415331A2 (enExample)
JP (1) JP2004538634A (enExample)
WO (1) WO2003015142A2 (enExample)

Families Citing this family (76)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1016129B2 (en) 1997-06-24 2009-06-10 Massachusetts Institute Of Technology Controlling threading dislocation densities using graded layers and planarization
US7227176B2 (en) 1998-04-10 2007-06-05 Massachusetts Institute Of Technology Etch stop layer system
US6602613B1 (en) 2000-01-20 2003-08-05 Amberwave Systems Corporation Heterointegration of materials using deposition and bonding
JP2003520444A (ja) * 2000-01-20 2003-07-02 アンバーウェーブ システムズ コーポレイション 高温成長を不要とする低貫通転位密度格子不整合エピ層
US6573126B2 (en) * 2000-08-16 2003-06-03 Massachusetts Institute Of Technology Process for producing semiconductor article using graded epitaxial growth
US6649480B2 (en) * 2000-12-04 2003-11-18 Amberwave Systems Corporation Method of fabricating CMOS inverter and integrated circuits utilizing strained silicon surface channel MOSFETs
US20020100942A1 (en) * 2000-12-04 2002-08-01 Fitzgerald Eugene A. CMOS inverter and integrated circuits utilizing strained silicon surface channel MOSFETs
JP2002232075A (ja) * 2001-01-31 2002-08-16 Ando Electric Co Ltd 波長可変光源
US6703688B1 (en) 2001-03-02 2004-03-09 Amberwave Systems Corporation Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits
US6830976B2 (en) 2001-03-02 2004-12-14 Amberwave Systems Corproation Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits
US6723661B2 (en) * 2001-03-02 2004-04-20 Amberwave Systems Corporation Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits
US6724008B2 (en) 2001-03-02 2004-04-20 Amberwave Systems Corporation Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits
US6940089B2 (en) 2001-04-04 2005-09-06 Massachusetts Institute Of Technology Semiconductor device structure
JP4831885B2 (ja) 2001-04-27 2011-12-07 株式会社半導体エネルギー研究所 半導体装置の作製方法
US7301180B2 (en) * 2001-06-18 2007-11-27 Massachusetts Institute Of Technology Structure and method for a high-speed semiconductor device having a Ge channel layer
JP2004531901A (ja) * 2001-06-21 2004-10-14 マサチューセッツ　インスティテュート　オブ　テクノロジー 歪み半導体層を備えたｍｏｓｆｅｔ
JP2004538634A (ja) * 2001-08-06 2004-12-24 マサチューセッツ　インスティテュート　オブ　テクノロジー ひずみ層を有する半導体基板及びその形成方法
US6974735B2 (en) * 2001-08-09 2005-12-13 Amberwave Systems Corporation Dual layer Semiconductor Devices
US7138649B2 (en) * 2001-08-09 2006-11-21 Amberwave Systems Corporation Dual-channel CMOS transistors with differentially strained channels
EP1428262A2 (en) 2001-09-21 2004-06-16 Amberwave Systems Corporation Semiconductor structures employing strained material layers with defined impurity gradients and methods for fabricating same
WO2003028106A2 (en) 2001-09-24 2003-04-03 Amberwave Systems Corporation Rf circuits including transistors having strained material layers
US6649492B2 (en) * 2002-02-11 2003-11-18 International Business Machines Corporation Strained Si based layer made by UHV-CVD, and devices therein
WO2003079415A2 (en) * 2002-03-14 2003-09-25 Amberwave Systems Corporation Methods for fabricating strained layers on semiconductor substrates
US7307273B2 (en) * 2002-06-07 2007-12-11 Amberwave Systems Corporation Control of strain in device layers by selective relaxation
US7074623B2 (en) 2002-06-07 2006-07-11 Amberwave Systems Corporation Methods of forming strained-semiconductor-on-insulator finFET device structures
US20030227057A1 (en) * 2002-06-07 2003-12-11 Lochtefeld Anthony J. Strained-semiconductor-on-insulator device structures
US6995430B2 (en) 2002-06-07 2006-02-07 Amberwave Systems Corporation Strained-semiconductor-on-insulator device structures
US7335545B2 (en) * 2002-06-07 2008-02-26 Amberwave Systems Corporation Control of strain in device layers by prevention of relaxation
US7615829B2 (en) 2002-06-07 2009-11-10 Amberwave Systems Corporation Elevated source and drain elements for strained-channel heterojuntion field-effect transistors
US7138310B2 (en) * 2002-06-07 2006-11-21 Amberwave Systems Corporation Semiconductor devices having strained dual channel layers
US6946371B2 (en) 2002-06-10 2005-09-20 Amberwave Systems Corporation Methods of fabricating semiconductor structures having epitaxially grown source and drain elements
US6982474B2 (en) 2002-06-25 2006-01-03 Amberwave Systems Corporation Reacted conductive gate electrodes
US6841457B2 (en) * 2002-07-16 2005-01-11 International Business Machines Corporation Use of hydrogen implantation to improve material properties of silicon-germanium-on-insulator material made by thermal diffusion
JP5144002B2 (ja) 2002-08-23 2013-02-13 台湾積體電路製造股▲ふん▼有限公司 減少した転位パイルアップを有する半導体ヘテロ構造および関連した方法
US7594967B2 (en) * 2002-08-30 2009-09-29 Amberwave Systems Corporation Reduction of dislocation pile-up formation during relaxed lattice-mismatched epitaxy
US6759712B2 (en) * 2002-09-12 2004-07-06 Micron Technology, Inc. Semiconductor-on-insulator thin film transistor constructions
EP1593145A2 (en) * 2002-10-30 2005-11-09 Amberwave Systems Corporation Methods for preserving strained semiconductor layers during oxide layer formation
JP4659732B2 (ja) * 2003-01-27 2011-03-30 台湾積體電路製造股▲ふん▼有限公司 半導体層を形成する方法
US6924181B2 (en) * 2003-02-13 2005-08-02 Taiwan Semiconductor Manufacturing Co., Ltd Strained silicon layer semiconductor product employing strained insulator layer
US6911379B2 (en) * 2003-03-05 2005-06-28 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming strained silicon on insulator substrate
CN100437970C (zh) 2003-03-07 2008-11-26 琥珀波系统公司 一种结构及用于形成半导体结构的方法
US6963078B2 (en) * 2003-03-15 2005-11-08 International Business Machines Corporation Dual strain-state SiGe layers for microelectronics
KR100679737B1 (ko) * 2003-05-19 2007-02-07 도시바세라믹스가부시키가이샤 왜곡층을 가지는 실리콘기판의 제조방법
US6831350B1 (en) 2003-10-02 2004-12-14 Freescale Semiconductor, Inc. Semiconductor structure with different lattice constant materials and method for forming the same
US6919258B2 (en) 2003-10-02 2005-07-19 Freescale Semiconductor, Inc. Semiconductor device incorporating a defect controlled strained channel structure and method of making the same
US7037770B2 (en) * 2003-10-20 2006-05-02 International Business Machines Corporation Method of manufacturing strained dislocation-free channels for CMOS
JP4413580B2 (ja) * 2003-11-04 2010-02-10 株式会社東芝 素子形成用基板の製造方法
US7615424B2 (en) * 2004-03-25 2009-11-10 Semiconductor Energy Laboratory Co., Ltd. Laser irradiation apparatus and method for manufacturing semiconductor device using the laser irradiation apparatus
US7791107B2 (en) * 2004-06-16 2010-09-07 Massachusetts Institute Of Technology Strained tri-channel layer for semiconductor-based electronic devices
US7229893B2 (en) * 2004-06-23 2007-06-12 Taiwan Semiconductor Manufacturing Company, Ltd. Method and apparatus for a semiconductor device with a high-k gate dielectric
US7244958B2 (en) * 2004-06-24 2007-07-17 International Business Machines Corporation Integration of strained Ge into advanced CMOS technology
US7279756B2 (en) * 2004-07-21 2007-10-09 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device with high-k gate dielectric and quasi-metal gate, and method of forming thereof
KR100674914B1 (ko) * 2004-09-25 2007-01-26 삼성전자주식회사 변형된 채널층을 갖는 모스 트랜지스터 및 그 제조방법
US20060113603A1 (en) * 2004-12-01 2006-06-01 Amberwave Systems Corporation Hybrid semiconductor-on-insulator structures and related methods
US7393733B2 (en) 2004-12-01 2008-07-01 Amberwave Systems Corporation Methods of forming hybrid fin field-effect transistor structures
US7355235B2 (en) * 2004-12-22 2008-04-08 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method for high-k gate dielectrics
US7332407B2 (en) * 2004-12-23 2008-02-19 Taiwan Semiconductor Manufacturing Company, Ltd. Method and apparatus for a semiconductor device with a high-k gate dielectric
US20060157806A1 (en) * 2005-01-18 2006-07-20 Omnivision Technologies, Inc. Multilayered semiconductor susbtrate and image sensor formed thereon for improved infrared response
US7465972B2 (en) * 2005-01-21 2008-12-16 Taiwan Semiconductor Manufacturing Company, Ltd. High performance CMOS device design
US7268362B2 (en) 2005-02-25 2007-09-11 Taiwan Semiconductor Manufacturing Company, Ltd. High performance transistors with SiGe strain
KR100703967B1 (ko) * 2005-02-28 2007-04-05 삼성전자주식회사 씨모스 트랜지스터 및 그 제조 방법
US7470972B2 (en) * 2005-03-11 2008-12-30 Intel Corporation Complementary metal oxide semiconductor integrated circuit using uniaxial compressive stress and biaxial compressive stress
KR101155097B1 (ko) * 2005-08-24 2012-06-11 삼성전자주식회사 반도체 장치의 제조 방법 및 그에 의해 제조된 반도체 장치
WO2007067589A2 (en) * 2005-12-05 2007-06-14 Massachusetts Institute Of Technology Insulated gate devices and method of making same
US7323392B2 (en) * 2006-03-28 2008-01-29 Taiwan Semiconductor Manufacturing Company, Ltd. High performance transistor with a highly stressed channel
US8063397B2 (en) * 2006-06-28 2011-11-22 Massachusetts Institute Of Technology Semiconductor light-emitting structure and graded-composition substrate providing yellow-green light emission
US7648853B2 (en) * 2006-07-11 2010-01-19 Asm America, Inc. Dual channel heterostructure
KR101007242B1 (ko) 2007-02-22 2011-01-13 후지쯔 세미컨덕터 가부시키가이샤 반도체 장치 및 그 제조 방법
US7795605B2 (en) * 2007-06-29 2010-09-14 International Business Machines Corporation Phase change material based temperature sensor
US8754455B2 (en) 2011-01-03 2014-06-17 International Business Machines Corporation Junction field effect transistor structure with P-type silicon germanium or silicon germanium carbide gate(s) and method of forming the structure
KR20120107762A (ko) * 2011-03-22 2012-10-04 삼성전자주식회사 반도체 소자의 제조 방법
US8828813B2 (en) * 2012-04-13 2014-09-09 Taiwan Semiconductor Manufacturing Co., Ltd. Replacement channels
US8796097B2 (en) * 2012-04-26 2014-08-05 University Of South Carolina Selectively area regrown III-nitride high electron mobility transistor
CN104465657B (zh) * 2013-09-22 2017-10-20 中芯国际集成电路制造(上海)有限公司 互补tfet 及其制造方法
US9379243B1 (en) 2015-02-19 2016-06-28 Intermational Business Machines Corporation Field-effect transistor with aggressively strained fins
US9793403B2 (en) * 2015-04-14 2017-10-17 Samsung Electronics Co., Ltd. Multi-layer fin field effect transistor devices and methods of forming the same

Family Cites Families (134)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US646322A (en) * 1897-05-04 1900-03-27 Wolverine Motor Works Explosive-engine.
US4497683A (en) * 1982-05-03 1985-02-05 At&T Bell Laboratories Process for producing dielectrically isolated silicon devices
DE3542482A1 (de) 1985-11-30 1987-06-04 Licentia Gmbh Modulationsdotierter feldeffekttransistor
US4692992A (en) * 1986-06-25 1987-09-15 Rca Corporation Method of forming isolation regions in a semiconductor device
JPS63122176A (ja) 1986-11-11 1988-05-26 Nippon Telegr & Teleph Corp <Ntt> 半導体装置とその製造方法
US4920076A (en) 1988-04-15 1990-04-24 The United States Of America As Represented By The United States Department Of Energy Method for enhancing growth of SiO2 in Si by the implantation of germanium
DE3816358A1 (de) 1988-05-13 1989-11-23 Eurosil Electronic Gmbh Nichtfluechtige speicherzelle und verfahren zur herstellung
US4958318A (en) 1988-07-08 1990-09-18 Eliyahou Harari Sidewall capacitor DRAM cell
US5241197A (en) 1989-01-25 1993-08-31 Hitachi, Ltd. Transistor provided with strained germanium layer
JP2675388B2 (ja) 1989-03-14 1997-11-12 日本電信電話株式会社 指向性を有するスピーカ装置
US5079447A (en) * 1990-03-20 1992-01-07 Integrated Device Technology BiCMOS gates with improved driver stages
US5089872A (en) 1990-04-27 1992-02-18 North Carolina State University Selective germanium deposition on silicon and resulting structures
US5155571A (en) 1990-08-06 1992-10-13 The Regents Of The University Of California Complementary field effect transistors having strained superlattice structure
DE4101167A1 (de) 1991-01-17 1992-07-23 Daimler Benz Ag Anordnung und verfahren zur herstellung komplementaerer feldeffekttransistoren
US5312766A (en) 1991-03-06 1994-05-17 National Semiconductor Corporation Method of providing lower contact resistance in MOS transistors
DE4200809C2 (de) * 1991-03-20 1996-12-12 Samsung Electronics Co Ltd Verfahren zur Bildung einer metallischen Verdrahtungsschicht in einem Halbleiterbauelement
JPH04307974A (ja) 1991-04-05 1992-10-30 Sharp Corp 電気的消去可能不揮発性半導体記憶装置
US5442205A (en) 1991-04-24 1995-08-15 At&T Corp. Semiconductor heterostructure devices with strained semiconductor layers
US5291439A (en) 1991-09-12 1994-03-01 International Business Machines Corporation Semiconductor memory cell and memory array with inversion layer
US5467305A (en) 1992-03-12 1995-11-14 International Business Machines Corporation Three-dimensional direct-write EEPROM arrays and fabrication methods
US5242847A (en) 1992-07-27 1993-09-07 North Carolina State University At Raleigh Selective deposition of doped silion-germanium alloy on semiconductor substrate
US5386132A (en) 1992-11-02 1995-01-31 Wong; Chun C. D. Multimedia storage system with highly compact memory device
US5418743A (en) 1992-12-07 1995-05-23 Nippon Steel Corporation Method of writing into non-volatile semiconductor memory
US5523592A (en) 1993-02-03 1996-06-04 Hitachi, Ltd. Semiconductor optical device, manufacturing method for the same, and opto-electronic integrated circuit using the same
US5792679A (en) 1993-08-30 1998-08-11 Sharp Microelectronics Technology, Inc. Method for forming silicon-germanium/Si/silicon dioxide heterostructure using germanium implant
JPH07106466A (ja) 1993-09-30 1995-04-21 Toppan Printing Co Ltd マルチチップモジュール搭載用プリント配線基板
JP3494458B2 (ja) 1993-10-05 2004-02-09 沖電気工業株式会社 半導体不揮発性記憶装置及びその製造方法
US5461243A (en) 1993-10-29 1995-10-24 International Business Machines Corporation Substrate for tensilely strained semiconductor
US5534713A (en) 1994-05-20 1996-07-09 International Business Machines Corporation Complementary metal-oxide semiconductor transistor logic using strained SI/SIGE heterostructure layers
US5479033A (en) * 1994-05-27 1995-12-26 Sandia Corporation Complementary junction heterostructure field-effect transistor
US5561302A (en) 1994-09-26 1996-10-01 Motorola, Inc. Enhanced mobility MOSFET device and method
US5710450A (en) 1994-12-23 1998-01-20 Intel Corporation Transistor with ultra shallow tip and method of fabrication
US5777347A (en) 1995-03-07 1998-07-07 Hewlett-Packard Company Vertical CMOS digital multi-valued restoring logic device
US5920088A (en) 1995-06-16 1999-07-06 Interuniversitair Micro-Electronica Centrum (Imec Vzw) Vertical MISFET devices
DE19533313A1 (de) 1995-09-08 1997-03-13 Max Planck Gesellschaft Halbleiterstruktur für einen Transistor
JP3403877B2 (ja) 1995-10-25 2003-05-06 三菱電機株式会社 半導体記憶装置とその製造方法
JP3372158B2 (ja) 1996-02-09 2003-01-27 株式会社東芝 半導体装置及びその製造方法
JP3217015B2 (ja) 1996-07-18 2001-10-09 インターナショナル・ビジネス・マシーンズ・コーポレーション 電界効果トランジスタの形成方法
US6399970B2 (en) 1996-09-17 2002-06-04 Matsushita Electric Industrial Co., Ltd. FET having a Si/SiGeC heterojunction channel
US5847419A (en) 1996-09-17 1998-12-08 Kabushiki Kaisha Toshiba Si-SiGe semiconductor device and method of fabricating the same
DE59707274D1 (de) 1996-09-27 2002-06-20 Infineon Technologies Ag Integrierte CMOS-Schaltungsanordnung und Verfahren zu deren Herstellung
EP0844651A1 (en) 1996-11-26 1998-05-27 Xerox Corporation Method of controlling oxidation in multilayer semiconductor structure comprising Group III elements
US5780922A (en) 1996-11-27 1998-07-14 The Regents Of The University Of California Ultra-low phase noise GE MOSFETs
US5808344A (en) 1996-12-13 1998-09-15 International Business Machines Corporation Single-transistor logic and CMOS inverters
KR100392909B1 (ko) * 1997-08-26 2004-03-22 엘지.필립스 엘시디 주식회사 박막트랜지스터및그의제조방법
US5891769A (en) 1997-04-07 1999-04-06 Motorola, Inc. Method for forming a semiconductor device having a heteroepitaxial layer
US5906951A (en) * 1997-04-30 1999-05-25 International Business Machines Corporation Strained Si/SiGe layers on insulator
US5951757A (en) 1997-05-06 1999-09-14 The United States Of America As Represented By The Secretary Of The Navy Method for making silicon germanium alloy and electric device structures
DE19720008A1 (de) 1997-05-13 1998-11-19 Siemens Ag Integrierte CMOS-Schaltungsanordnung und Verfahren zu deren Herstellung
EP1016129B2 (en) 1997-06-24 2009-06-10 Massachusetts Institute Of Technology Controlling threading dislocation densities using graded layers and planarization
US5936274A (en) 1997-07-08 1999-08-10 Micron Technology, Inc. High density flash memory
US5963817A (en) 1997-10-16 1999-10-05 International Business Machines Corporation Bulk and strained silicon on insulator using local selective oxidation
JP3447939B2 (ja) 1997-12-10 2003-09-16 株式会社東芝 不揮発性半導体メモリ及びデータ読み出し方法
JP3059145B2 (ja) 1997-12-12 2000-07-04 松下電子工業株式会社 不揮発性半導体記憶装置およびその駆動方法
FR2773177B1 (fr) 1997-12-29 2000-03-17 France Telecom Procede d'obtention d'une couche de germanium ou silicium monocristallin sur un substrat de silicium ou germanium monocristallin, respectivement, et produits multicouches obtenus
US6013134A (en) 1998-02-18 2000-01-11 International Business Machines Corporation Advance integrated chemical vapor deposition (AICVD) for semiconductor devices
TW415103B (en) * 1998-03-02 2000-12-11 Ibm Si/SiGe optoelectronic integrated circuits
WO1999053539A1 (en) 1998-04-10 1999-10-21 Massachusetts Institute Of Technology Silicon-germanium etch stop layer system
JP4258034B2 (ja) * 1998-05-27 2009-04-30 ソニー株式会社 半導体装置及び半導体装置の製造方法
JP3403076B2 (ja) 1998-06-30 2003-05-06 株式会社東芝 半導体装置及びその製造方法
US6130453A (en) 1999-01-04 2000-10-10 International Business Machines Corporation Flash memory structure with floating gate in vertical trench
DE60042666D1 (de) 1999-01-14 2009-09-17 Panasonic Corp Halbleiterbauelement und Verfahren zu dessen Herstellung
US6235568B1 (en) 1999-01-22 2001-05-22 Intel Corporation Semiconductor device having deposited silicon regions and a method of fabrication
KR100441469B1 (ko) 1999-03-12 2004-07-23 인터내셔널 비지네스 머신즈 코포레이션 전계 효과 장치용 고속 게르마늄 채널 이종구조물
US6350993B1 (en) 1999-03-12 2002-02-26 International Business Machines Corporation High speed composite p-channel Si/SiGe heterostructure for field effect devices
JP4521542B2 (ja) 1999-03-30 2010-08-11 ルネサスエレクトロニクス株式会社 半導体装置および半導体基板
US6251755B1 (en) 1999-04-22 2001-06-26 International Business Machines Corporation High resolution dopant/impurity incorporation in semiconductors via a scanned atomic force probe
US6281532B1 (en) 1999-06-28 2001-08-28 Intel Corporation Technique to obtain increased channel mobilities in NMOS transistors by gate electrode engineering
US6228694B1 (en) 1999-06-28 2001-05-08 Intel Corporation Method of increasing the mobility of MOS transistors by use of localized stress regions
US6151248A (en) 1999-06-30 2000-11-21 Sandisk Corporation Dual floating gate EEPROM cell array with steering gates shared by adjacent cells
US6204529B1 (en) 1999-08-27 2001-03-20 Hsing Lan Lung 8 bit per cell non-volatile semiconductor memory structure utilizing trench technology and dielectric floating gate
JP2001160594A (ja) 1999-09-20 2001-06-12 Toshiba Corp 半導体装置
US6339232B1 (en) 1999-09-20 2002-01-15 Kabushika Kaisha Toshiba Semiconductor device
US6249022B1 (en) 1999-10-22 2001-06-19 United Microelectronics Corp. Trench flash memory with nitride spacers for electron trapping
JP4226175B2 (ja) 1999-12-10 2009-02-18 富士通株式会社 半導体装置およびその製造方法
US7391087B2 (en) 1999-12-30 2008-06-24 Intel Corporation MOS transistor structure and method of fabrication
WO2001054202A1 (en) 2000-01-20 2001-07-26 Amberwave Systems Corporation Strained-silicon metal oxide semiconductor field effect transistors
KR100392166B1 (ko) 2000-03-17 2003-07-22 가부시끼가이샤 도시바 반도체 장치의 제조 방법 및 반도체 장치
JP3603747B2 (ja) 2000-05-11 2004-12-22 三菱住友シリコン株式会社 ＳｉＧｅ膜の形成方法とヘテロ接合トランジスタの製造方法、及びヘテロ接合バイポーラトランジスタ
DE10025264A1 (de) 2000-05-22 2001-11-29 Max Planck Gesellschaft Feldeffekt-Transistor auf der Basis von eingebetteten Clusterstrukturen und Verfahren zu seiner Herstellung
US6693641B1 (en) * 2000-05-25 2004-02-17 Intel Corporation Calculating display mode values
WO2001093338A1 (en) 2000-05-26 2001-12-06 Amberwave Systems Corporation Buried channel strained silicon fet using an ion implanted doped layer
US6437375B1 (en) * 2000-06-05 2002-08-20 Micron Technology, Inc. PD-SOI substrate with suppressed floating body effect and method for its fabrication
US6461945B1 (en) 2000-06-22 2002-10-08 Advanced Micro Devices, Inc. Solid phase epitaxy process for manufacturing transistors having silicon/germanium channel regions
EP1295319A2 (en) 2000-06-22 2003-03-26 Massachusetts Institute Of Technology Etch stop layer system for sige devices
US6583015B2 (en) 2000-08-07 2003-06-24 Amberwave Systems Corporation Gate technology for strained surface channel and strained buried channel MOSFET devices
US6573126B2 (en) * 2000-08-16 2003-06-03 Massachusetts Institute Of Technology Process for producing semiconductor article using graded epitaxial growth
KR100649303B1 (ko) * 2000-11-16 2006-11-24 엘지전자 주식회사 양쪽 눈의 홍채 이미지 집사 장치
US7312485B2 (en) 2000-11-29 2007-12-25 Intel Corporation CMOS fabrication process utilizing special transistor orientation
US6649480B2 (en) 2000-12-04 2003-11-18 Amberwave Systems Corporation Method of fabricating CMOS inverter and integrated circuits utilizing strained silicon surface channel MOSFETs
US20020100942A1 (en) 2000-12-04 2002-08-01 Fitzgerald Eugene A. CMOS inverter and integrated circuits utilizing strained silicon surface channel MOSFETs
EP1399970A2 (en) 2000-12-04 2004-03-24 Amberwave Systems Corporation Cmos inverter circuits utilizing strained silicon surface channel mosfets
US6563152B2 (en) 2000-12-29 2003-05-13 Intel Corporation Technique to obtain high mobility channels in MOS transistors by forming a strain layer on an underside of a channel
WO2002071491A1 (en) 2001-03-02 2002-09-12 Amberwave Systems Corporation Relaxed silicon germanium platform for high speed cmos electronics and high speed analog circuits
WO2002071488A1 (en) 2001-03-02 2002-09-12 Amberwave Systems Corporation Relaxed silicon germanium platform for high speed cmos electronics and high speed analog circuits
US6593641B1 (en) 2001-03-02 2003-07-15 Amberwave Systems Corporation Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits
US6724008B2 (en) 2001-03-02 2004-04-20 Amberwave Systems Corporation Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits
US6723661B2 (en) 2001-03-02 2004-04-20 Amberwave Systems Corporation Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits
US6646322B2 (en) 2001-03-02 2003-11-11 Amberwave Systems Corporation Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits
US6703688B1 (en) * 2001-03-02 2004-03-09 Amberwave Systems Corporation Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits
JP2004531054A (ja) 2001-03-02 2004-10-07 アンバーウェーブ システムズ コーポレイション 高速ｃｍｏｓ電子機器及び高速アナログ回路のための緩和シリコンゲルマニウムプラットフォーム
US6677192B1 (en) * 2001-03-02 2004-01-13 Amberwave Systems Corporation Method of fabricating a relaxed silicon germanium platform having planarizing for high speed CMOS electronics and high speed analog circuits
US6603156B2 (en) 2001-03-31 2003-08-05 International Business Machines Corporation Strained silicon on insulator structures
US6940089B2 (en) * 2001-04-04 2005-09-06 Massachusetts Institute Of Technology Semiconductor device structure
US6593625B2 (en) * 2001-06-12 2003-07-15 International Business Machines Corporation Relaxed SiGe layers on Si or silicon-on-insulator substrates by ion implantation and thermal annealing
WO2002103760A2 (en) 2001-06-14 2002-12-27 Amberware Systems Corporation Method of selective removal of sige alloys
US7301180B2 (en) 2001-06-18 2007-11-27 Massachusetts Institute Of Technology Structure and method for a high-speed semiconductor device having a Ge channel layer
JP2004531901A (ja) * 2001-06-21 2004-10-14 マサチューセッツ　インスティテュート　オブ　テクノロジー 歪み半導体層を備えたｍｏｓｆｅｔ
JP2004538634A (ja) * 2001-08-06 2004-12-24 マサチューセッツ　インスティテュート　オブ　テクノロジー ひずみ層を有する半導体基板及びその形成方法
US6974735B2 (en) 2001-08-09 2005-12-13 Amberwave Systems Corporation Dual layer Semiconductor Devices
US7138649B2 (en) * 2001-08-09 2006-11-21 Amberwave Systems Corporation Dual-channel CMOS transistors with differentially strained channels
US6621131B2 (en) 2001-11-01 2003-09-16 Intel Corporation Semiconductor transistor having a stressed channel
US6600170B1 (en) 2001-12-17 2003-07-29 Advanced Micro Devices, Inc. CMOS with strained silicon channel NMOS and silicon germanium channel PMOS
US6620664B2 (en) * 2002-02-07 2003-09-16 Sharp Laboratories Of America, Inc. Silicon-germanium MOSFET with deposited gate dielectric and metal gate electrode and method for making the same
US6605498B1 (en) 2002-03-29 2003-08-12 Intel Corporation Semiconductor transistor having a backfilled channel material
US7138310B2 (en) * 2002-06-07 2006-11-21 Amberwave Systems Corporation Semiconductor devices having strained dual channel layers
US7473947B2 (en) 2002-07-12 2009-01-06 Intel Corporation Process for ultra-thin body SOI devices that incorporate EPI silicon tips and article made thereby
US6812086B2 (en) 2002-07-16 2004-11-02 Intel Corporation Method of making a semiconductor transistor
US6743684B2 (en) 2002-10-11 2004-06-01 Texas Instruments Incorporated Method to produce localized halo for MOS transistor
US6703648B1 (en) 2002-10-29 2004-03-09 Advanced Micro Devices, Inc. Strained silicon PMOS having silicon germanium source/drain extensions and method for its fabrication
US6657223B1 (en) 2002-10-29 2003-12-02 Advanced Micro Devices, Inc. Strained silicon MOSFET having silicon source/drain regions and method for its fabrication
US20040119101A1 (en) 2002-12-23 2004-06-24 Gerhard Schrom Contact layout for MOSFETs under tensile strain
US7001837B2 (en) 2003-01-17 2006-02-21 Advanced Micro Devices, Inc. Semiconductor with tensile strained substrate and method of making the same
US6921913B2 (en) 2003-03-04 2005-07-26 Taiwan Semiconductor Manufacturing Co., Ltd. Strained-channel transistor structure with lattice-mismatched zone
US6955952B2 (en) * 2003-03-07 2005-10-18 Taiwan Semiconductor Manufacturing Company, Ltd. Strain balanced structure with a tensile strained silicon channel and a compressive strained silicon-germanium channel for CMOS performance enhancement
US6916694B2 (en) * 2003-08-28 2005-07-12 International Business Machines Corporation Strained silicon-channel MOSFET using a damascene gate process
US6943087B1 (en) * 2003-12-17 2005-09-13 Advanced Micro Devices, Inc. Semiconductor on insulator MOSFET having strained silicon channel
US7033869B1 (en) * 2004-01-13 2006-04-25 Advanced Micro Devices Strained silicon semiconductor on insulator MOSFET
KR100528486B1 (ko) * 2004-04-12 2005-11-15 삼성전자주식회사 불휘발성 메모리 소자 및 그 형성 방법
US7268065B2 (en) * 2004-06-18 2007-09-11 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of manufacturing metal-silicide features
US7902058B2 (en) * 2004-09-29 2011-03-08 Intel Corporation Inducing strain in the channels of metal gate transistors
US7163853B2 (en) * 2005-02-09 2007-01-16 Taiwan Semiconductor Manufacturing Company, Ltd. Method of manufacturing a capacitor and a metal gate on a semiconductor device
US7176537B2 (en) * 2005-05-23 2007-02-13 Taiwan Semiconductor Manufacturing Company, Ltd. High performance CMOS with metal-gate and Schottky source/drain
US7719058B2 (en) * 2005-10-12 2010-05-18 Seliskar John J Mixed-signal semiconductor platform incorporating fully-depleted castellated-gate MOSFET device and method of manufacture thereof

Also Published As

Publication number Publication date
US20030025131A1 (en) 2003-02-06
US6730551B2 (en) 2004-05-04
US20040164318A1 (en) 2004-08-26
US7141820B2 (en) 2006-11-28
EP1415331A2 (en) 2004-05-06
WO2003015142A3 (en) 2003-11-27
US20070072354A1 (en) 2007-03-29
WO2003015142A2 (en) 2003-02-20

Similar Documents

Publication Publication Date Title
JP2004538634A (ja) ひずみ層を有する半導体基板及びその形成方法
US6982208B2 (en) Method for producing high throughput strained-Si channel MOSFETS
CN100583395C (zh) 半导体装置及其制造方法
US8610175B2 (en) Semiconductor device and manufacturing method thereof
TWI222106B (en) Semiconductor substrate, field-effect transistor, and their production methods
JP4949628B2 (ja) Ｃｍｏｓプロセス中に歪み半導基板層を保護する方法
US20040007715A1 (en) Heterojunction field effect transistors using silicon-germanium and silicon-carbon alloys
WO2008054967A2 (en) Method for providing a nanoscale, high electron mobility transistor (hemt) on insulator
US20070029553A1 (en) Methods of fabricating strained semiconductor-on-insulator field-effect transistors and related devices
US20080116487A1 (en) Methods of fabricating transistors having high carrier mobility and transistors fabricated thereby
US7495266B2 (en) Strained silicon-on-silicon by wafer bonding and layer transfer
US20040245552A1 (en) Production method for semiconductor substrate and production method for field effect transistor and semiconductor substrate and field effect transistor
WO2005059979A1 (en) Method for forming a strained si-channel in a mosfet structure
US11121254B2 (en) Transistor with strained superlattice as source/drain region
CN101916770A (zh) 具有双缓变结的Si-Ge-Si半导体结构及其形成方法
US20170179127A1 (en) Semiconductor structure having silicon germanium fins and method of fabricating same
US7202142B2 (en) Method for producing low defect density strained -Si channel MOSFETS
CN100397574C (zh) 具有应变的多层结构及具有应变层的场效应晶体管的制法
JP4325139B2 (ja) 半導体基板の製造方法及び電界効果型トランジスタの製造方法
US20060088966A1 (en) Semiconductor device having a smooth EPI layer and a method for its manufacture
CN1845304A (zh) 制作金属氧化物半导体晶体管的方法
JP4506035B2 (ja) 半導体基板と電界効果型トランジスタ並びにＳｉＧｅ層の形成方法及びこれを用いた歪みＳｉ層の形成方法と電界効果型トランジスタの製造方法
US20050280081A1 (en) Semiconductor devices having bonded interfaces and methods for making the same
JP3714230B2 (ja) 半導体基板及び電界効果型トランジスタ並びにこれらの製造方法
TWI231043B (en) Method for fabricating strained multi-layer structure

Legal Events

Date Code Title Description
RD03 Notification of appointment of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7423

Effective date: 20050708

RD04 Notification of resignation of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7424

Effective date: 20050728

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20080226

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20080722