TWI231043B - Method for fabricating strained multi-layer structure - Google Patents

Abstract

A method for fabricating a strained multi-layer structure. A step-graded silicon germanium (Si1-xGex) buffer layer and a silicon germanium capping layer are successively deposited overlying a substrate by reduced pressure chemical vapor deposition (RPCVD) using disilane or trisilane as a first reacting gas. Subsequently, a single crystalline silicon layer is deposited on the silicon germanium capping layer by RPCVD using silane or dichlorosilane as a second reacting gas to form a strained layer. A field effect transistor (FET) having a strained layer is also disclosed.

Description

1231043

FIELD OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a multilayer structure having strain and a method in which a strained layer is a crystal. Call the prior art: In order to meet the increase in the integration of integrated circuits to increase the demand for components, the size of semiconductor components must be continuously reduced. However, the word of =, in the semiconductor components commonly used in integrated circuits, such as metal oxide; and the body (M0SFET), it is very difficult to make it have a high crystal current and high speed performance at low operating voltage . Therefore, many people are working on ways to improve the performance of metal-oxide-semiconductor half-field-effect transistor devices. Seeking • Some people have proposed to use the mobility of the band structure-induced carriers induced by stress to increase the driving current of field effect transistors and the effectiveness of the effect transistor elements', and this method has been used in various fields. The silicon channel system of these devices is under strain. Types can be added to improve field components. Traditionally, a strained silicon layer is prepared by epitaxial growth of a silicon channel layer on a relaxed silicon germanium layer or substrate. Before growing a strained silicon channel layer, it is usually necessary to grow a SUe with a gradually deformed lattice on the silicon substrate. The ratio of the germanium x in the layer gradually increases from 0 to 0.2, which is referred to as step-graded here. Silicon germanium buffer layer. Then, a slack silicon germanium (Sink ") cap layer is grown on the progressive silicon germanium buffer layer. These silicon germanium layers and strained silicon layers are prepared by an epitaxy method, among which the low pressure chemical vapor deposition method is the most common. general

1231043

V. Description of the invention (2) As far as the reaction gas (process precursor) used is SiCl4, SiH2cl2, SiHci (SiΗ4), etc. The mechanism can be known from the growth rate and temperature 3 curves. Generally, the slope of the relationship curve of the above four gases is small at f (above 800 ° C), and it is larger in the low temperature region, with a turn of summer point between them. At the slope In a small area, the growth rate is relatively unaffected by temperature. The mass transfer rate from the main reaction gas to the substrate is directly proportional. This area is called mass transfer controlled region (S). On the other hand, in a region with a large slope, growth The rate is related to the surface reaction rate and has an exponential relationship with temperature. This region is called the surface reaction control region (surface level and reaction control led region). In the mass transfer control region (at high temperature (surface reaction controlled region), but due to the use, The high growth temperature required for the reaction gas is not conducive to the integration of the strained film into the semiconductor process. Therefore, in the current semiconductor process, the epitaxial growth is more than the surface reaction. Control zone.) Stupid uniformity of the formed polycrystalline thin film is superior than the control surface of the reaction zone

• However, 'the preparation of an epitaxial film at a low temperature (for example, below 700 ° C) is quite time-consuming', especially when using the above-mentioned reaction gas. For example. ‘Stand-by growth of low-pressure chemical rolling phase deposition (LPWCVD)’ It takes at least an hour for each wafer to produce a strained multilayer structure. Furthermore, if ultra-high vacuum CVD (UHVCVD) is used, each wafer will cost at least ten hours or more. That is, it takes a long time to manufacture and seriously affects production capacity and manufacturing costs.

1231043 V. Description of the invention (3) US Patent No. 5,951,757 discloses a method of silicon germanium layer, which uses silicon to passivate the surface of a sapphire substrate, and then uses silane and germane as process precursors to form silicon germanium. Floor. Furthermore, U.S. Patent No. 6,410,371 discloses a method for manufacturing a silicon insulating layer (SO I) having a silicon / silicon germanium / silicon layer active layer, by fabricating a silicon dioxide substrate with a silicon dioxide layer and A silicon dioxide / silicon germanium / silicon germanium / silicon germanium / silicon germanium / silicon germanium / silicon germanium / silicon germanium / silicon germanium / silicon germanium / silicon germanium layer Active silicon substrate. Furthermore, US Patent No. 6,51 5,3 3 5 discloses a method for fabricating a relaxed silicon germanium layer on a silicon insulating layer substrate. First, a wetting layer is formed on a silicon insulating layer substrate. ), Followed by molecular beam epitaxy (MBE) or CVD in order to form silicon germanium islands and a silicon germanium cap layer covering the islands in order, and then through a tempering process to make the wet layer, silicon germanium islands, And the silicon germanium cap layer interacts to form a single crystal silicon germanium layer, and finally a strained epitaxial silicon layer is formed thereon. Among the above methods, either the silane is still used as the precursor of the process or the process is too effective to increase the production capacity of the components ^ Summary of the invention:

In view of this, the purpose of the present invention is to provide a multi-layered field-effect transistor with a strained layer for producing a variety of field-effect transistors with a strained layer for chemical vapor deposition. Cheng Zhigang has replaced the first-generation process dredger of Filigree to maintain the stock and single production capacity at the same time. Check the properties of the strain layer and increase the production of components Page 8 丨 · 0503-976nW (Nl); TSMC2002.1389; Spin.ptd 1231043

According to the above-mentioned object, the present invention provides a strainable manufacturing device.结构 的 方法。 Construction method. First, a substrate is provided. Next, # by two silicon :: Sanmeng Bingxuan as the -th-reaction gas, the dream germanium (Si, _xGex) buffer layer and the Shixi germanium cap layer are sequentially deposited on the substrate, where χ increases with the thickness of the buffer layer. Gradually increased from 0 to 0.3. After that, the silicon silicate is used as a second reactive gas to cover the silicon germanium by Shi Xi; a second gas layer is deposited to form a strained layer. The silicon substrate on weekdays may be a silicon substrate, and further includes a silicon buffer between the substrate and the progressive silicon germanium buffer layer, and the thickness is in the range of 丨. ·

Furthermore, the thickness of the progressive SiGe buffer layer is in the range of 2 to 5 microns. The thickness of the germanium cap layer is in the range of 0.5 to 1 micrometer. / In the range of 100 to 300 Angstroms. In addition, the thickness of the chip is further formed by a progressive silicon-germanium buffer layer, a silicon-germanium cap layer, and single crystal silicon by reduced pressure chemical vapor deposition (RPCVD). The process temperature of the reduced pressure 77 chemical vapor deposition is in the range of 600 I to 800 c, and the pressure is in the range of 50 Torr to 760 Torr.

According to the above object, the present invention provides a method for manufacturing a field effect transistor. First, a substrate is provided. Then, using Ersanshiyu as the first reaction and gas, the substrate is formed with a progressive silicon-germanium (SU ') buffer layer and a silicon-germanium cap layer, which increases with the thickness of the progressive silicon-germanium buffer layer. And gradually increased from 0 to 0.3. After that, a single crystal silicon layer was deposited on the silicon germanium cap layer as a strained channel layer by using silane <2 gas silane as a second reaction gas. Finally, on the strain channel layer

0503-976nW (Nl); TSMC2002.1389; Spin.ptd Page 9 1231043 V. Description of the invention (5): A U-pole structure and a strain channel outside the gate structure form a source / drain region. The center of the forced layer further comprises a silicon buffer layer formed between the silicon substrate and the punching layer, and its thickness is in the range of 01 to 0.9 micrometers. Further, the thickness of the progressive silicon germanium buffer layer is in the range of 2 to 5 micrometers, and the thickness of the capping layer of germanium is in the range of 0.5 to 1 micrometer. Monocrystalline &amp; ° is in the range of 100 to 300 angstroms. Increasing thickness Further, the progressive silicon germanium buffer layer, the silicon germanium cap layer and the single crystal are formed by reduced pressure chemical vapor deposition (RPCVD). The process temperature of the chemical chemical vapor deposition is in the range of 60 (rc to 80 (rc), and the decompression pressure is in the range of 50 Torr to 760 Torr. Furthermore, the gate structure includes a gate dielectric layer, a gate electrode, and A gate gap wall, wherein the gate dielectric layer is disposed above the strain channel layer, the gate electrode is disposed above the gate dielectric layer, and the gate gap ^ is disposed on a side wall of the gate electrode. The purpose, features, and advantages can be more clearly understood. The preferred embodiments are described below in detail with the accompanying drawings as follows: Implementation: The following describes the implementation of the present invention with Figures 1 A to 1C and Figure 2 For example, a method for manufacturing a field effect transistor with a strain layer. First, please refer to FIG. 1A, and provide a substrate 10, which can be a single crystal substrate, a silicon substrate (silicon 〇) n insulator,

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V. Description of the invention (6) --- L son or other semiconductor substrate. Here, a single crystal silicon substrate with a crystal orientation of (100) is taken as an example, and then a silicon buffer layer 12 can be selectively formed over the substrate 10, which is used as a seed for the subsequent deposition of silicon germanium buffer 1. Layer (seed layer). In this embodiment, the silicon buffer layer 12 can be formed on the substrate by epitaxial method. For example, dioxane (SiH2Cl2), silane (SiH4), disiloxane (Si2H6), or trisilicon is used. (ShH8) was used as a reaction gas to perform chemical vapor deposition (cvd). The silicon buffer layer 12 is formed to a thickness of 0.1 to 0.9 micrometers (u / 彳 μ ^, and a preferred thickness is about 0.5 ...), and then a silicon germanium layer is deposited on the silicon buffer layer 12. In the embodiment, 'this Shi Xi fault layer includes two parts, the lower part is a setp-graded silicon germanium (sue) buffer layer 14, and the upper part is a relaxed silicon germanium cap layer. 16 (as shown in FIG. 1B) [The atomic ratio of germanium in the progressive silicon germanium buffer layer 14 is gradually increased from 0 to 0.3 as the thickness of the progressive silicon germanium buffer layer 14 increases. That is, the progressive silicon germanium buffer layer i4S and At the interface of the silicon buffer layer 12, the content of germanium is about 0, while in the progressive silicon-germanium buffer, the content of germanium at the top surface of the layer 14 is about 0.3, and the increase rate is about 0 · 06 / // m To a perimeter of 0.15 /// m ... In this embodiment, the progressive stone germanium buffer layer 14 can be formed by an epitaxial method. The method may be to use disilane or trisilane as the silicon. Source reaction gas, and using germane (Germane, Gel) as the reaction source of the wrong source to perform reduced pressure chemical vapor deposition (RPCVD). In the temperature range of 60 0 ° C to to 800 ° C. Furthermore, a progressive SiGe process pressure in the range from 1 to 760T〇rr 50T〇rr the formed buffer layer with a thickness of 14

1231043 V. Description of the invention (7) The degree is in the range of 2 to 5 # m, and the preferred thickness is about 21. Next, refer to FIG. 1B. Similarly, the epitaxial method is used to deposit a slack silicon germanium (SiiyGey) capping layer on the silicon germanium buffer layer 14, which is different from the progressive dream germanium buffer layer 14. The germanium atom ratio y in the cap layer 16 is a constant, for example, y is in a range of 0.25 to 0.3. In this embodiment, the silicon-germanium cap layer 16 is similarly subjected to reduced-pressure chemical vapor deposition using disilane or trisilpropane as a reaction gas derived from silicon, and using germane as a reaction gas derived from germanium. . Among them, the deposition process temperature is in the range of 600 ° C to 80 ° C. In addition, the flow rate of disilane / trisilpropane is in the range of 50 to 20 Sccm, and the flow rate of germane is 5 (^ j2. 〇sccin range. In addition, the process pressure is in the range of 50 Torr to 760 Torr. The thickness of the formed Si Xi Ge cap layer 16 is in the range of 0.5 to lem, and the preferred thickness is about 0.9 / zm. Here, the progressive silicon germanium buffer layer 14 in the silicon germanium layer is used to gather and reduce the lattice defects_threading dislocation 'therein, and the silicon cap layer 16 is provided for the subsequent formation of a strain layer. After the progressive silicon germanium buffer layer 14 and the silicon germanium cap layer 16 are formed, a single crystal silicon layer 8 is then deposited thereon to form a strained silicon layer for use as a strained channel layer for subsequent transistor production. In the embodiment, the monocrystalline silicon layer 18 can also be formed by epitaxial method. However, here, silane or digasite firing is used as the reaction source for the silicon source to perform vacuum chemical vapor deposition without using Silane or trisilane, this is to reduce the hydrogen content in the monocrystalline silicon layer Fan facilitate lifting the carrier mobility as the strain rate of the single crystal silicon layer of the channel layer 18 in which, in the deposition process temperature to 600 ° C to 800 ° C

I1H 0503-9761BfF (Nl); TSMC2002-1389; Spin.ptd Page 12 1231043 V. Description of the invention (8). Furthermore, the process pressure ranges from 50 Torr to 76 Torr. The thickness of the formed single crystal silicon layer 18 is in the range of 100 to 300 Angstroms (A), and the preferred thickness is about 135 A. In this way, the strained multilayer structure of the present invention is completed. Finally, please refer to FIG. 1C, and a gate structure 25 is formed above the strained silicon layer. It includes a gate dielectric layer 20, a gate electrode 22, and a gate electrode 24. The gate dielectric layer 20 is disposed above the strained silicon layer 18 as a channel layer. Furthermore, the gate electrode 22 is disposed above the gate dielectric layer 20. In addition, the gate spacer 24 is provided on the side wall of the gate electrode. Here, the method of forming the gate structure 25 is as follows: First, a silicon oxide layer (not shown) can be formed on the strained silicon layer 18 by a hafnium oxidation method, wherein the oxidation temperature is lower than 800. . . Then, a conventional deposition technique, such as chemical vapor deposition, can be used to form a polycrystalline silicon layer (not ^ = i) on top of the silicon oxide layer. Layer, gate; 丨 electrical layer 20 and gate electrode composed of polycrystalline silicon layer. Afterwards, chemical vapor deposition can also be used to deposit a gasification conformation on the sidewall and surface of the strained silicon closed-electrode ...: The painted surface and the concatenator use anisotropic etching, such as reactive ion etching (reactive ^^^^ '"㈡'qianqi gasification stone layer' to leave at the gate electrode 22 ^! 2. p 分 的 气Cut layer 24, which is used as the gate gap wall 24. After the fabrication of the gate structure 25, an impurity region can be formed in the ion channel layer 18 and the stone germanium cap layer 16; rdc In this way, the fabrication of a metal oxide + conductor field effect transistor (MOSFET) with a strained layer is completed.

1231043 V. Description of the invention (9) It should be noted that although the present invention is based on mosfet as an example, those skilled in the art can integrate the present invention with other semiconductors based on the needs of the architecture. It looks like a CMOS transistor. ▼ Fanshi's production, examples, redundant: :: fresh photo 2 ’which shows the pair of different reaction gases. As mentioned earlier, the curves A, β, and e in the figure are smaller at high temperatures, but in areas where the low temperature is larger and the slope of E is small, which is the turning point of mass transfer control E, eight. Slope ^ ^ Seek &amp; the area with a large slope, that is, the helmet master: should control the area. In addition, the curve A indicates that four gasified fossils are used as the surface rolling body, and the curve B indicates that three gas silane (SiHci0 is the reaction 4 is =

The curve table uses the second gas Shi Xiyuan (SiH2Cl2) as the second line and one C uses Shi Xixuan (SiH4) as the reaction gas, and the E-body D curve is not shown as the reaction gas. The curve table does not use disilane (Si2H6 in order to cope with the current low temperature (for example, it is limited at 700), and the reaction gas A, B, C, and D of the ea process must be deposited in the surface reaction control zone. The use of E »Therefore, the present invention uses a reactive gas to reduce the deposition rate of the germanium overlying layer below the reactive gas, which can greatly increase the deposition rate. 2 Entering the Shixibu buffer layer and increasing the production capacity of components and reducing the production J = shorten In addition, as described earlier, in order to increase the hydrogen content in the through layer, the strain rate should not be excessive, so the strained stone layer is prepared from the strained stone layer. D to make the device have better electrical characteristics. In addition, 'can increase the carrier rate, electricity generation. In addition, compared with the use of reactive gas page 140503.976nW (Nl); ptd 1231043

A, B, can have a faster deposition rate and shorten the process. Although the present invention has been limited to the present invention with the better two, anyone familiar with this item, T: However, it is not used within the scope of God and can be changed and moisturized. Without departing from the spirit and scope of the present invention, the scope of the patent application attached hereafter will be equal to the scope of protection of the present invention.

1231043 Brief Description of Drawings Figures 1A to 1C are schematic cross-sectional views illustrating a process for manufacturing a field effect transistor having a strain layer according to an embodiment of the present invention. Fig. 2 is a graph showing the relationship between the logarithmic deposition rate of different reaction gases and the reaction temperature. Symbol description 10 ~ substrate; 1 ~ 2 ~ silicon buffer layer; 1 ~ 4 ~ progressive silicon germanium buffer layer; 16 ~ silicon germanium cap layer; 18 ~ monocrystalline silicon layer; 20 ~ gate dielectric layer; 2 ~ 2 ~ Gate electrode; 24 gate gap wall; 2 5 ~ gate structure; 2 6 ~ source / drain region.

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Claims (1)

1231043 VI. The scope of patent application is less 1. A method for manufacturing a strained multi-layer structure including the following steps: providing a substrate; and using disiloxane / trisilane as a first reaction gas A progressive silicon-germanium (Sii-xGex) buffer germanium cap layer is formed on the silicon substrate in sequence, where X increases from · to 0 · 3 as the thickness of the progressive silicon-germanium buffer layer increases; and Silane / digas silane is used as a second reaction gas to form a strained layer by depositing a single crystal silicon layer on the germanium cap layer. Treatment M2. The method for manufacturing a strained structure as described in item 1 of the scope of the patent application, wherein the substrate is a silicon substrate. 3. The method for manufacturing a strained,% recorded structure as described in item 2 of the scope of the patent application, further comprising forming a silicon buffer layer between the substrate and the progressive dream buffer layer. 4. The method for manufacturing a strained multilayer recording structure as described in item 3 of the scope of the patent application, wherein the thickness of the silicon buffer layer is in the range of 0.1 to 0.9 microns. 5. The method for manufacturing a strained multilayer structure as described in item 1 of the scope of patent application, wherein the first reaction gas further includes germane. 6 · The method for manufacturing a strained multi-layered substrate as described in item 1 of the scope of the patent application, wherein the thickness of the progressive silicon germanium buffer layer is in the range of 2 to 5 microns in the stomach. 7. As stated in the scope of the patent application The method of manufacturing a strained multi-drawer surname structure, wherein the thickness of the overburden layer of Shi Xicuo is from 0.5 to 1 microns ^ 1231043 -----. 6. The scope of patent application. 8. The method for producing a strained poly 1 structure as described in item i of the patent application range, wherein the single crystal second layer term ranges from 100 to 300 Angstroms. 9 · Should the manufacturing tools described in item i of the patent application be applied? Xi layer 2 structure method, wherein the pressure reduction chemical fluorine W product (RPCVD) is used to form the / chopped into the germanium buffer layer and the Shi Xicuo cap layer 10 · as claimed in the patent application; Multi-layer structure method, wherein the process temperature of the vacuum chemical vapor deposition is in the range of 600 C to 80 0 ° C. U. Such as the method described in item 9 of the "Patent for Green Patent", a method for manufacturing a multi-layer structure Wherein, the process pressure of the vacuum chemical vapor deposition is in a range of 50T0 to 760T0rr. 12. The method of manufacturing a strained multilayer structure as described in item 丨 of the patent application range, wherein Vapor deposition (RPCVD) forms the single crystal fragmentation layer. 13. The method for manufacturing a strained multilayer structure as described in item 12 of the scope of patent application, wherein the process temperature of the vacuum chemical fluorine phase deposition is 600 ° C to 800 ° C. 14. The method for manufacturing a strained multilayer structure as described in item 12 of the patent application range, wherein the process pressure of the reduced pressure chemical vapor deposition is in the range of 50 Torr to 760 Torr. 15 ·-A kind of field effect with strain layer The method of the crystal, comprising the steps of: 0503-976nW (Nl); TSMC2002.1389; Spin.ptd Page 18 1231043 6. The scope of the patent application provides a silicon substrate; using disilane / trisilane as a first reaction gas above the substrate A progressive silicon germanium (Si ^ Ge,) buffer layer and a silicon germanium cap layer are sequentially formed, where X gradually increases from 0 to 0.3 as the thickness of the progressive silicon germanium buffer layer increases; and Silane is used as a second reaction gas to deposit a monocrystalline stone layer on the Shixiu cap layer as a strained channel layer; a gate structure is formed above the strained channel layer; and outside the gate structure A source and a pole region are formed in the strained channel layer. 16. The method for manufacturing a field effect transistor having a strained layer as described in item 15 of the scope of the patent application, wherein the substrate is a silicon substrate. 17. The method for manufacturing a field effect transistor having a strained layer as described in item 16 of the scope of the patent application, further comprising forming a silicon buffer layer between the substrate and the progressive silicon germanium buffer layer. 18. The method for manufacturing a field effect transistor having a strained layer as described in item 17 of the scope of the patent application, wherein the thickness of the silicon buffer layer is in the range of 0.1 to 0.9 micrometers. 19 · The method for manufacturing a field-effect transistor with a strained layer as described in item 15 of the scope of patent application, wherein the thallium reaction gas further includes germane. 20. The method for manufacturing a field effect transistor with a strained layer as described in item 15 of the scope of the patent application, wherein the thickness of the progressive silicon buffer layer is in the range of 2 to 5 microns. 2 1 · Manufacture of a strained layer as described in item 15 of the scope of patent application 0503-976nW (Nl); TSMC2002-1389; Spin.ptd 19th true 1231043 VI. Patent Application __ --- Field-effect transistor method, in which the thickness of the SiGe cap layer is in the range of micrometers. # · U Tian 22. The method for manufacturing a field effect transistor having a strained layer as described in item 15 of the scope of the patent application, wherein the thickness of the single crystal silicon layer is in the range of 100 to 30 (A). Tian 23 · The method for manufacturing a field effect transistor with a strained layer as described in item 15 of the scope of patent application, wherein the progressive SiGe buffer layer and the SiGe cap layer are formed by reduced pressure chemical vapor deposition (RpcvD) . 24. The method for manufacturing a field-effect transistor with a strained layer as described in item 23 of the scope of the patent application, wherein the production process of the vacuum chemical vapor deposition is at 600. (: To 80 0 t. Λ &amp; 25 · The method for manufacturing a field effect transistor with a strained layer as described in item 23 of the scope of patent application, wherein the process pressure of the vacuum chemical vapor deposition is 50 Torr The range is from 760 Torr. 26. The method for manufacturing a% -effect electric crystal having a strained layer as described in item 15 of Shen Qing's patent scope, wherein the single crystal silicon layer is formed by reduced pressure chemical vapor deposition (rp). 27 · The method for manufacturing a field effect transistor with a strained layer as described in item 26 of the scope of the patent application, wherein the process temperature of the vacuum chemical vapor deposition is in the range of 60 (TC to 80 0 ° C. 又 28 · The method of manufacturing a% -effect solar cell with a strained layer as described in item 26 of the scope of the patent application, wherein the process pressure of the depressurized vapor phase deposition is in the range of 50 Torr to 7 60 Torr. Fabrication of a strained layer as described in item 15 1231043 VI. Patent application method of field-effect transistor, wherein the gate structure further includes: a gate dielectric layer disposed above the strain channel layer; a gate electrode disposed above the gate dielectric layer And a gate gap wall; disposed on a side wall of the gate electrode. 0503-9761TWF (Nl); TSMC2002-1389; Spin.ptd p. 21