JP2004165627A - L字型スペーサを採用した半導体素子の製造方法 - Google Patents
L字型スペーサを採用した半導体素子の製造方法 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 76
- 125000006850 spacer group Chemical group 0.000 title claims abstract description 70
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 28
- 238000000034 method Methods 0.000 claims abstract description 60
- 239000000758 substrate Substances 0.000 claims abstract description 43
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 34
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 34
- 229910052751 metal Inorganic materials 0.000 claims abstract description 27
- 239000002184 metal Substances 0.000 claims abstract description 27
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 20
- 239000012535 impurity Substances 0.000 claims description 27
- 238000005530 etching Methods 0.000 claims description 25
- 238000000137 annealing Methods 0.000 claims description 19
- 150000004767 nitrides Chemical class 0.000 claims description 13
- 238000010438 heat treatment Methods 0.000 claims description 11
- 238000005468 ion implantation Methods 0.000 claims description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 4
- 229910052710 silicon Inorganic materials 0.000 claims description 4
- 239000010703 silicon Substances 0.000 claims description 4
- 238000000348 solid-phase epitaxy Methods 0.000 claims description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 3
- 229920005591 polysilicon Polymers 0.000 claims description 3
- 229910018072 Al 2 O 3 Inorganic materials 0.000 claims description 2
- -1 Si 3 N 4 Inorganic materials 0.000 claims description 2
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 2
- 229910017052 cobalt Inorganic materials 0.000 claims description 2
- 239000010941 cobalt Substances 0.000 claims description 2
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 claims description 2
- RUFLMLWJRZAWLJ-UHFFFAOYSA-N nickel silicide Chemical compound [Ni]=[Si]=[Ni] RUFLMLWJRZAWLJ-UHFFFAOYSA-N 0.000 claims description 2
- 229910021334 nickel silicide Inorganic materials 0.000 claims description 2
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 2
- 229910021341 titanium silicide Inorganic materials 0.000 claims description 2
- 239000010410 layer Substances 0.000 description 54
- 230000000694 effects Effects 0.000 description 6
- 238000001039 wet etching Methods 0.000 description 6
- 230000002265 prevention Effects 0.000 description 5
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 4
- 238000002955 isolation Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
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Abstract
【解決手段】 トランジスタ部及び抵抗部に区分された半導体基板のトランジスタ部にゲートパターンを形成する。前記ゲートパターンの両側壁の絶縁膜の上に除去スペーサを形成する。前記トランジスタ部の前記除去スペーサにアラインされた半導体基板及び前記抵抗部の半導体基板に深いソース/ドレーン領域を形成する。前記除去スペーサ及び絶縁膜を順次に除去した後、前記トランジスタ部の深いソース/ドレーン領域に隣接して前記ゲートパターンの両側の半導体基板に浅いソース/ドレーン領域を形成する。前記トランジスタ部のゲートパターンの両側壁にL字型スペーサを形成しつつ前記抵抗部にはシリサイド形成防止膜パターンを同時に形成する。前記ゲート電極の上面、前記トランジスタ部及び抵抗部の深いソース及びドレーン領域上に金属シリサイドを形成する。
【選択図】 図13
Description
103 ゲート絶縁膜
105 ゲート電極
106 ゲートパターン
113 深いソース/ドレーン領域
115 浅いソース/ドレーン領域
127 金属シリサイド
128 層間絶縁膜
129 金属コンタクトホール
131 金属フラグ
133 金属膜
Claims (20)
- トランジスタ部及び抵抗部に区分された半導体基板のトランジスタ部にゲートパターンを形成する段階と、
前記ゲートパターン及び半導体基板の全面にバッファ絶縁膜、第1絶縁膜及び第2絶縁膜を順次に形成する段階と、
前記第2絶縁膜をエッチングして前記ゲートパターンの両側壁の第1絶縁膜上に除去スペーサを形成する段階と、
前記トランジスタ部の前記除去スペーサにアラインされた半導体基板及び前記抵抗部の半導体基板に深いソース/ドレーン領域を形成する段階と、
前記除去スペーサ及び第1絶縁膜を順次に除去する段階と、
前記トランジスタ部の深いソース/ドレーン領域に隣接して前記ゲートパターンの両側の半導体基板に浅いソース/ドレーン領域を形成する段階と、
前記バッファ絶縁膜上に第3絶縁膜及び第4絶縁膜を順次に形成する段階と、
前記第4絶縁膜、第3絶縁膜及びバッファ絶縁膜をパターニングして前記トランジスタ部のゲートパターンの両側壁にL字型スペーサを形成しつつ前記抵抗部にはシリサイド形成防止膜パターンを同時に形成する段階と、
前記ゲート電極の上面、前記トランジスタ部及び抵抗部の深いソース及びドレーン領域上に金属シリサイドを形成する段階と、
を含んでなることを特徴とする半導体素子の製造方法。 - 前記第4絶縁膜を形成する段階後に前記抵抗部にマスクパターンを形成して、前記シリサイド形成防止膜パターンの形成時にエッチングマスクとして利用することを特徴とする請求項1に記載の半導体素子の製造方法。
- 前記第2絶縁膜は前記第1絶縁膜に対してエッチング選択比の高い膜質を利用して形成することを特徴とする請求項1に記載の半導体素子の製造方法。
- 前記第2絶縁膜は酸化膜よりなり、前記第1絶縁膜は窒化膜よりなることを特徴とする請求項3に記載の半導体素子の製造方法。
- 前記第1絶縁膜は前記バッファ絶縁膜に対してエッチング選択比の高い膜質を利用して形成することを特徴とする請求項1に記載の半導体素子の製造方法。
- 前記第1絶縁膜は窒化膜よりなり、前記バッファ絶縁膜は酸化膜よりなることを特徴とする請求項5に記載の半導体素子の製造方法。
- 前記深いソース/ドレーン領域を形成する段階は、前記除去スペーサをマスクとして不純物をイオン注入する段階と、前記注入された不純物をアニーリングする段階と、よりなることを特徴とする請求項1に記載の半導体素子の製造方法。
- 前記深いソース/ドレーン領域を形成するためのアニーリングは前記浅いソース/ドレーン領域を形成する前に行うことを特徴とする請求項7に記載の半導体素子の製造方法。
- 前記浅いソース/ドレーン領域を形成する段階は、前記バッファ絶縁膜が形成された半導体基板の全面に不純物をイオン注入する段階と、前記注入された不純物をアニーリングする段階と、よりなることを特徴とする請求項1に記載の半導体素子の製造方法。
- 前記浅いソース/ドレーン領域を形成するためのアニーリングは前記金属シリサイドを形成する前に行うことを特徴とする請求項9に記載の半導体素子の製造方法。
- 前記浅いソース/ドレーン領域を形成するためのアニーリングは500〜800℃の低温で行うか、あるいは900〜1300℃で急速熱処理又はスパイク熱処理方法を利用して行うことを特徴とする請求項9に記載の半導体素子の製造方法。
- 前記第4絶縁膜は前記第3絶縁膜に対してエッチング選択比の高い膜質を利用して形成することを特徴とする請求項1に記載の半導体素子の製造方法。
- 前記第4絶縁膜は酸化膜よりなり、前記第3絶縁膜は窒化膜よりなることを特徴とする請求項12に記載の半導体素子の製造方法。
- 前記浅いソース/ドレーン領域はイオン注入方法、固相エピタクシ方法またはプラズマドーピング方法を利用して形成することを特徴とする請求項1に記載の半導体素子の製造方法。
- 前記ゲートパターンの両側壁から前記深いソース及びドレーン領域までの長さは前記除去スペーサの長さによって決定され、前記ゲートパターンの両側壁から前記金属シリサイドまでの距離は前記スペーサの長さによって決定されることを特徴とする請求項1に記載の半導体素子の製造方法。
- 前記半導体基板はシリコン基板又はSOI基板を利用することを特徴とする請求項1に記載の半導体素子の製造方法。
- 前記ゲートパターンはゲート絶縁膜及びゲート電極を順次に形成することによって形成することを特徴とする請求項1に記載の半導体素子の製造方法。
- 前記ゲート絶縁膜はSiO2、Si3N4、SiON、ZrO2、HfO2、Ta2O5またはAl2O3よりなることを特徴とする請求項17に記載の半導体素子の製造方法。
- 前記ゲート電極は不純物がドーピングされたポリシリコン膜、金属シリサイド膜及び金属膜の単一膜または多重膜よりなることを特徴とする請求項17に記載の半導体素子の製造方法。
- 前記金属シリサイドはコバルトシリサイド、ニッケルシリサイドまたはチタンシリサイドを利用して形成することを特徴とする請求項1に記載の半導体素子の製造方法。
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KR10-2002-0070864A KR100446309B1 (ko) | 2002-11-14 | 2002-11-14 | L자형 스페이서를 채용한 반도체 소자의 제조 방법 |
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Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007181349A (ja) * | 2005-12-28 | 2007-07-12 | Denso Corp | ドライバ用半導体素子の過電流保護装置 |
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JP2005191228A (ja) * | 2003-12-25 | 2005-07-14 | Sanyo Electric Co Ltd | 半導体装置の製造方法 |
DE102004031606B4 (de) * | 2004-06-30 | 2009-03-12 | Infineon Technologies Ag | Integrierte Schaltungsanordnung mit pin-Diode und Herstellungsverfahren |
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CN102655110B (zh) * | 2011-03-04 | 2014-10-22 | 中芯国际集成电路制造(上海)有限公司 | Soi晶体管及其制造方法 |
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US7776751B2 (en) | 2005-05-17 | 2010-08-17 | Canon Anelva Corporation | Process for producing silicon compound |
JP2007181349A (ja) * | 2005-12-28 | 2007-07-12 | Denso Corp | ドライバ用半導体素子の過電流保護装置 |
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JP2008263052A (ja) * | 2007-04-12 | 2008-10-30 | Renesas Technology Corp | 半導体装置の製造方法 |
JP2017120821A (ja) * | 2015-12-28 | 2017-07-06 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
Also Published As
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KR20040042913A (ko) | 2004-05-22 |
KR100446309B1 (ko) | 2004-09-01 |
US6869839B2 (en) | 2005-03-22 |
US20040097031A1 (en) | 2004-05-20 |
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