JP2005191228A - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 67
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 34
- 239000000758 substrate Substances 0.000 claims abstract description 27
- 238000005530 etching Methods 0.000 claims abstract description 22
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 21
- 239000012535 impurity Substances 0.000 claims abstract description 20
- 125000006850 spacer group Chemical group 0.000 claims abstract description 14
- 238000000034 method Methods 0.000 claims abstract description 12
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 4
- 239000010410 layer Substances 0.000 claims description 116
- 238000009792 diffusion process Methods 0.000 claims description 59
- 238000002955 isolation Methods 0.000 claims description 18
- 239000011241 protective layer Substances 0.000 claims description 5
- 238000005229 chemical vapour deposition Methods 0.000 claims description 2
- 230000001681 protective effect Effects 0.000 claims description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
- 230000001133 acceleration Effects 0.000 description 5
- 229910052814 silicon oxide Inorganic materials 0.000 description 5
- 238000002513 implantation Methods 0.000 description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 3
- 229910052796 boron Inorganic materials 0.000 description 3
- 230000006866 deterioration Effects 0.000 description 2
- OKZIUSOJQLYFSE-UHFFFAOYSA-N difluoroboron Chemical compound F[B]F OKZIUSOJQLYFSE-UHFFFAOYSA-N 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/20—Resistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
- H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
- H01L27/0629—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with diodes, or resistors, or capacitors
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- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
【解決手段】
本発明の半導体装置の製造方法は、以下の特徴を有する。即ち、n型ウェル11上に形成されたゲート電極22及びp+型の拡散抵抗層30上を含むn型ウェル11の全面に、CVD絶縁膜23を形成する。そして、拡散抵抗層30の一部上に開口部42mを有する第2のホトレジスト層42を形成し、これをマスクとして、CVD絶縁膜23を異方性エッチングして、ゲート電極22の側壁に側壁スペーサー23sを形成する。さらに、第2のホトレジスト層42をマスクとして、高濃度のp型不純物をドーピングして、MOSトランジスタ20のソース層24s及びドレイン層24d、及び拡散抵抗層30のコンタクト形成用p+型層31を形成する。
【選択図】 図7
Description
Claims (4)
- 同一の半導体基板上にMOSトランジスタ及び拡散抵抗層を備える半導体装置の製造方法であって、
前記半導体基板上に複数の素子分離層を形成する工程と、
前記素子分離層に隣接する領域に、ゲート絶縁膜を介してゲート電極を形成する工程と、
前記素子分離層で囲まれた前記半導体基板上の領域に低濃度の不純物をドーピングして拡散抵抗層を形成する工程と、
前記ゲート電極及び前記拡散抵抗層上を含む前記半導体基板の全面に、CVD法によりCVD絶縁膜を形成する工程と、
前記拡散抵抗層の主要部上にエッチング保護層を形成し、前記エッチング保護層をエッチング保護マスクとして、前記CVD絶縁膜を異方性エッチングして、前記ゲート電極の側壁に側壁スペーサーを形成する工程と、を有することを特徴とする半導体装置の製造方法。 - 前記側壁スペーサーを形成する工程の後、
高濃度の不純物をドーピングして、前記MOSトランジスタのソース層及びドレイン層を形成する工程と、を含むことを特徴とする請求項1記載の半導体装置の製造方法。 - 同一の第1導電型半導体基板上にMOSトランジスタ及び第1導電型の拡散抵抗層を備える半導体装置の製造方法であって、
前記第1導電型半導体基板上に第2導電型ウェルを形成する工程と、前記第2導電型ウェル内に複数の素子分離層を形成する工程と、
前記素子分離層に隣接する領域に、ゲート絶縁膜を介してゲート電極を形成する工程と、
前記素子分離層で囲まれた前記第2導電型ウェル上の領域に開口部を有する第1のホトレジスト層を形成し、前記第1のホトレジスト層をマスクとして、前記第2導電型ウェルに対して、低濃度の第1導電型不純物をドーピングして第1導電型の拡散抵抗層を形成する工程と、
前記第1のホトレジストを除去した後、前記ゲート電極及び前記拡散抵抗層上を含む前記第2導電型ウェルの全面に、CVD法によりCVD絶縁膜を形成する工程と、
前記拡散抵抗層の一部上に開口部を有する第2のホトレジスト層を形成し、前記第2のホトレジスト層をエッチング保護マスクとして、前記CVD絶縁膜を異方性エッチングして、前記拡散抵抗層の一部上及び前記第2導電型ウェルの一部上の前記ゲート絶縁膜及び前記CVD絶縁膜を除去すると共に、前記ゲート電極上の不要な前記CVD絶縁膜を除去して前記ゲート電極の側壁に側壁スペーサーを形成する工程と、
前記第2のホトレジスト層をマスクとして、高濃度の第1導電型不純物をドーピングして、前記MOSトランジスタのソース層及びドレイン層、及び前記拡散抵抗層のコンタクト形成用高濃度層を形成する工程と、を有することを特徴とする半導体装置の製造方法。 - 前記半導体装置は、バイポーラトランジスタと共に、前記同一の半導体基板上に形成されることを特徴とする請求項1,2,3のいずれかに記載の半導体装置の製造方法。
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2003429823A JP2005191228A (ja) | 2003-12-25 | 2003-12-25 | 半導体装置の製造方法 |
TW093138887A TWI239566B (en) | 2003-12-25 | 2004-12-15 | Manufacture method for semiconductor device |
US11/011,785 US7300836B2 (en) | 2003-12-25 | 2004-12-15 | Manufacturing method of semiconductor device |
CNB2004101020545A CN100352015C (zh) | 2003-12-25 | 2004-12-17 | 半导体装置的制造方法 |
KR1020040111698A KR100702097B1 (ko) | 2003-12-25 | 2004-12-24 | 반도체 장치의 제조 방법 |
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JP2003429823A JP2005191228A (ja) | 2003-12-25 | 2003-12-25 | 半導体装置の製造方法 |
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JP2005191228A true JP2005191228A (ja) | 2005-07-14 |
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JP2003429823A Pending JP2005191228A (ja) | 2003-12-25 | 2003-12-25 | 半導体装置の製造方法 |
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US (1) | US7300836B2 (ja) |
JP (1) | JP2005191228A (ja) |
KR (1) | KR100702097B1 (ja) |
CN (1) | CN100352015C (ja) |
TW (1) | TWI239566B (ja) |
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EP3883073B1 (en) * | 2020-03-20 | 2022-09-07 | TRUMPF Photonic Components GmbH | Method of forming an electrical metal contact and method of producing a vertical cavity surface emitting laser |
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US5134088A (en) * | 1990-04-27 | 1992-07-28 | Digital Equipment Corporation | Precision resistor in self-aligned silicided mos process |
JP2903881B2 (ja) * | 1992-06-22 | 1999-06-14 | 日本電気株式会社 | 半導体装置の製造方法 |
EP0681319B1 (en) * | 1994-04-15 | 2002-10-30 | Kabushiki Kaisha Toshiba | Semiconductor device and method of manufacturing the same |
JP3143366B2 (ja) | 1995-07-31 | 2001-03-07 | 三洋電機株式会社 | Cmos半導体装置の製造方法 |
US6221760B1 (en) * | 1997-10-20 | 2001-04-24 | Nec Corporation | Semiconductor device having a silicide structure |
EP0880165B1 (en) * | 1997-05-20 | 2007-07-25 | STMicroelectronics S.r.l. | A method of manufacturing an integrated circuit with MOS transistors having high breakdown voltages, and with precision resistors |
US6096591A (en) * | 1997-06-30 | 2000-08-01 | Advanced Micro Devices, Inc. | Method of making an IGFET and a protected resistor with reduced processing steps |
EP0975021B1 (en) * | 1998-07-22 | 2005-11-02 | STMicroelectronics S.r.l. | Process for manufacturing an electronic device including MOS transistors with salicided junctions and non-salicided resistors |
EP1006568A1 (en) * | 1998-12-02 | 2000-06-07 | STMicroelectronics S.r.l. | Enhancing protection of dielectrics from plasma induced damages |
KR100446309B1 (ko) * | 2002-11-14 | 2004-09-01 | 삼성전자주식회사 | L자형 스페이서를 채용한 반도체 소자의 제조 방법 |
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2003
- 2003-12-25 JP JP2003429823A patent/JP2005191228A/ja active Pending
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2004
- 2004-12-15 US US11/011,785 patent/US7300836B2/en not_active Expired - Fee Related
- 2004-12-15 TW TW093138887A patent/TWI239566B/zh not_active IP Right Cessation
- 2004-12-17 CN CNB2004101020545A patent/CN100352015C/zh not_active Expired - Fee Related
- 2004-12-24 KR KR1020040111698A patent/KR100702097B1/ko not_active IP Right Cessation
Also Published As
Publication number | Publication date |
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TWI239566B (en) | 2005-09-11 |
KR100702097B1 (ko) | 2007-04-02 |
CN100352015C (zh) | 2007-11-28 |
US20050158943A1 (en) | 2005-07-21 |
US7300836B2 (en) | 2007-11-27 |
KR20050065405A (ko) | 2005-06-29 |
TW200522208A (en) | 2005-07-01 |
CN1638062A (zh) | 2005-07-13 |
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