JP2002063069A - メモリ制御装置、データ処理システム及び半導体装置 - Google Patents

メモリ制御装置、データ処理システム及び半導体装置

Info

Publication number
JP2002063069A
JP2002063069A JP2000254245A JP2000254245A JP2002063069A JP 2002063069 A JP2002063069 A JP 2002063069A JP 2000254245 A JP2000254245 A JP 2000254245A JP 2000254245 A JP2000254245 A JP 2000254245A JP 2002063069 A JP2002063069 A JP 2002063069A
Authority
JP
Japan
Prior art keywords
mode
address
page
access
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2000254245A
Other languages
English (en)
Japanese (ja)
Other versions
JP2002063069A5 (enExample
Inventor
Seishi Miura
誓士 三浦
Kazushige Ayukawa
一重 鮎川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP2000254245A priority Critical patent/JP2002063069A/ja
Priority to TW090115419A priority patent/TWI284801B/zh
Priority to TW093100573A priority patent/TWI251739B/zh
Priority to TW091101193A priority patent/TW544574B/zh
Priority to KR1020010042823A priority patent/KR100764633B1/ko
Priority to US09/931,860 priority patent/US6587934B2/en
Priority to US09/986,348 priority patent/US6542957B2/en
Priority to US09/986,347 priority patent/US6574700B2/en
Publication of JP2002063069A publication Critical patent/JP2002063069A/ja
Priority to US10/357,412 priority patent/US6675269B2/en
Priority to US10/712,050 priority patent/US7076601B2/en
Priority to US11/453,907 priority patent/US7624238B2/en
Publication of JP2002063069A5 publication Critical patent/JP2002063069A5/ja
Priority to US12/620,912 priority patent/US8024512B2/en
Priority to US13/233,308 priority patent/US8255622B2/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/161—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0215—Addressing or allocation; Relocation with look ahead addressing means
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1018—Serial bit line access mode, e.g. using bit line address shift registers, bit line address counters, bit line burst counters
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Dram (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Memory System (AREA)
JP2000254245A 2000-08-21 2000-08-21 メモリ制御装置、データ処理システム及び半導体装置 Pending JP2002063069A (ja)

Priority Applications (13)

Application Number Priority Date Filing Date Title
JP2000254245A JP2002063069A (ja) 2000-08-21 2000-08-21 メモリ制御装置、データ処理システム及び半導体装置
TW090115419A TWI284801B (en) 2000-08-21 2001-06-26 Memory controller, data processing system, and semiconductor device
TW093100573A TWI251739B (en) 2000-08-21 2001-06-26 Semiconductor device
TW091101193A TW544574B (en) 2000-08-21 2001-06-26 Memory control method
KR1020010042823A KR100764633B1 (ko) 2000-08-21 2001-07-16 메모리 제어장치, 데이터 처리시스템 및 반도체장치
US09/931,860 US6587934B2 (en) 2000-08-21 2001-08-20 Memory controller and data processing system
US09/986,347 US6574700B2 (en) 2000-08-21 2001-11-08 Semiconductor device with auto address allocation means for a cache memory
US09/986,348 US6542957B2 (en) 2000-08-21 2001-11-08 Memory of controlling page mode access
US10/357,412 US6675269B2 (en) 2000-08-21 2003-02-04 Semiconductor device with memory controller that controls page mode access
US10/712,050 US7076601B2 (en) 2000-08-21 2003-11-14 Memory controller and data processing system
US11/453,907 US7624238B2 (en) 2000-08-21 2006-06-16 Memory controller and data processing system
US12/620,912 US8024512B2 (en) 2000-08-21 2009-11-18 Memory controller and data processing system
US13/233,308 US8255622B2 (en) 2000-08-21 2011-09-15 Memory controller and data processing system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2000254245A JP2002063069A (ja) 2000-08-21 2000-08-21 メモリ制御装置、データ処理システム及び半導体装置

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2010232206A Division JP4936489B2 (ja) 2010-10-15 2010-10-15 半導体装置

Publications (2)

Publication Number Publication Date
JP2002063069A true JP2002063069A (ja) 2002-02-28
JP2002063069A5 JP2002063069A5 (enExample) 2007-05-31

Family

ID=18743225

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000254245A Pending JP2002063069A (ja) 2000-08-21 2000-08-21 メモリ制御装置、データ処理システム及び半導体装置

Country Status (4)

Country Link
US (8) US6587934B2 (enExample)
JP (1) JP2002063069A (enExample)
KR (1) KR100764633B1 (enExample)
TW (3) TWI251739B (enExample)

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KR20040021485A (ko) * 2002-09-04 2004-03-10 삼성전자주식회사 메모리 접근시간을 줄이기 위하여 페이지 모드를 선택할수 있는 메모리 제어장치 및 메모리 접근 제어방법
JP2006343947A (ja) * 2005-06-08 2006-12-21 Kyocera Mita Corp メモリアクセス制御装置及びコンピュータプログラム
JP2009032055A (ja) * 2007-07-27 2009-02-12 Hitachi Ltd データ記憶装置
US7535792B2 (en) 2006-11-07 2009-05-19 Seiko Epson Corporation Data transmission control device, and data transmission control method
JP2011070666A (ja) * 2009-09-23 2011-04-07 Samsung Electronics Co Ltd 電子デバイスの性能改善のための電子デバイスコントローラ
JP2012520535A (ja) * 2009-03-20 2012-09-06 クアルコム，インコーポレイテッド メモリアクセス時間を最適化するための、メモリアクセスコントローラ、システム、および方法

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CN102270181B (zh) * 2010-06-01 2013-10-02 炬力集成电路设计有限公司 一种内存访问方法和装置
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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20040021485A (ko) * 2002-09-04 2004-03-10 삼성전자주식회사 메모리 접근시간을 줄이기 위하여 페이지 모드를 선택할수 있는 메모리 제어장치 및 메모리 접근 제어방법
JP2006343947A (ja) * 2005-06-08 2006-12-21 Kyocera Mita Corp メモリアクセス制御装置及びコンピュータプログラム
US7535792B2 (en) 2006-11-07 2009-05-19 Seiko Epson Corporation Data transmission control device, and data transmission control method
JP2009032055A (ja) * 2007-07-27 2009-02-12 Hitachi Ltd データ記憶装置
JP2012520535A (ja) * 2009-03-20 2012-09-06 クアルコム，インコーポレイテッド メモリアクセス時間を最適化するための、メモリアクセスコントローラ、システム、および方法
JP2011070666A (ja) * 2009-09-23 2011-04-07 Samsung Electronics Co Ltd 電子デバイスの性能改善のための電子デバイスコントローラ

Also Published As

Publication number Publication date
US20030126392A1 (en) 2003-07-03
US20120005421A1 (en) 2012-01-05
US20100064101A1 (en) 2010-03-11
US20060245281A1 (en) 2006-11-02
TWI284801B (en) 2007-08-01
TWI251739B (en) 2006-03-21
US6587934B2 (en) 2003-07-01
TW200408945A (en) 2004-06-01
US8024512B2 (en) 2011-09-20
TW544574B (en) 2003-08-01
US6675269B2 (en) 2004-01-06
US7076601B2 (en) 2006-07-11
US20020035662A1 (en) 2002-03-21
KR20020015266A (ko) 2002-02-27
US7624238B2 (en) 2009-11-24
KR100764633B1 (ko) 2007-10-08
US6542957B2 (en) 2003-04-01
US20020023197A1 (en) 2002-02-21
US8255622B2 (en) 2012-08-28
US6574700B2 (en) 2003-06-03
US20020053001A1 (en) 2002-05-02
US20040095818A1 (en) 2004-05-20

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