ITMI912260A0 - Struttura di interconnessione di un dispositivo a circuito integrato a semiconduttore e procedimento per la fabbricazione di essa - Google Patents
Struttura di interconnessione di un dispositivo a circuito integrato a semiconduttore e procedimento per la fabbricazione di essaInfo
- Publication number
- ITMI912260A0 ITMI912260A0 IT91MI2260A ITMI912260A ITMI912260A0 IT MI912260 A0 ITMI912260 A0 IT MI912260A0 IT 91MI2260 A IT91MI2260 A IT 91MI2260A IT MI912260 A ITMI912260 A IT MI912260A IT MI912260 A0 ITMI912260 A0 IT MI912260A0
- Authority
- IT
- Italy
- Prior art keywords
- procedure
- manufacturing
- integrated circuit
- semiconductor integrated
- circuit device
- Prior art date
Links
- 238000004519 manufacturing process Methods 0.000 title 1
- 238000000034 method Methods 0.000 title 1
- 239000004065 semiconductor Substances 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53214—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being aluminium
- H01L23/53223—Additional layers associated with aluminium layers, e.g. adhesion, barrier, cladding layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5226—Via connections in a multilevel interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2227061A JP2598335B2 (ja) | 1990-08-28 | 1990-08-28 | 半導体集積回路装置の配線接続構造およびその製造方法 |
Publications (3)
Publication Number | Publication Date |
---|---|
ITMI912260A0 true ITMI912260A0 (it) | 1991-08-20 |
ITMI912260A1 ITMI912260A1 (it) | 1992-02-29 |
IT1251290B IT1251290B (it) | 1995-05-08 |
Family
ID=16854919
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
ITMI912260A IT1251290B (it) | 1990-08-28 | 1991-08-20 | Struttura di interconnessione di un dispositivo a circuito integrato a semiconduttore e procedimento per la fabbricazione di essa |
Country Status (5)
Country | Link |
---|---|
US (2) | US5313101A (it) |
JP (1) | JP2598335B2 (it) |
KR (1) | KR950014686B1 (it) |
DE (1) | DE4128421C2 (it) |
IT (1) | IT1251290B (it) |
Families Citing this family (39)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2598335B2 (ja) * | 1990-08-28 | 1997-04-09 | 三菱電機株式会社 | 半導体集積回路装置の配線接続構造およびその製造方法 |
JP2533414B2 (ja) * | 1991-04-09 | 1996-09-11 | 三菱電機株式会社 | 半導体集積回路装置の配線接続構造およびその製造方法 |
JP2811126B2 (ja) * | 1991-05-02 | 1998-10-15 | 三菱電機株式会社 | 半導体集積回路装置の配線接続構造およびその製造方法 |
JP3086556B2 (ja) * | 1993-02-09 | 2000-09-11 | 株式会社神戸製鋼所 | 半導体ダイヤモンド層上の耐熱性オーミック電極及びその形成方法 |
US5358901A (en) * | 1993-03-01 | 1994-10-25 | Motorola, Inc. | Process for forming an intermetallic layer |
JP3401843B2 (ja) * | 1993-06-21 | 2003-04-28 | ソニー株式会社 | 半導体装置における多層配線の形成方法 |
US5360995A (en) * | 1993-09-14 | 1994-11-01 | Texas Instruments Incorporated | Buffered capped interconnect for a semiconductor device |
US6675361B1 (en) * | 1993-12-27 | 2004-01-06 | Hyundai Electronics America | Method of constructing an integrated circuit comprising an embedded macro |
US5671397A (en) * | 1993-12-27 | 1997-09-23 | At&T Global Information Solutions Company | Sea-of-cells array of transistors |
DE19515564B4 (de) | 1994-04-28 | 2008-07-03 | Denso Corp., Kariya | Elektrode für ein Halbleiterbauelement und Verfahren zur Herstellung derselben |
US5571751A (en) * | 1994-05-09 | 1996-11-05 | National Semiconductor Corporation | Interconnect structures for integrated circuits |
JPH0864695A (ja) * | 1994-08-24 | 1996-03-08 | Sony Corp | コンタクトプログラム方式rom及びその作製方法 |
US5625233A (en) * | 1995-01-13 | 1997-04-29 | Ibm Corporation | Thin film multi-layer oxygen diffusion barrier consisting of refractory metal, refractory metal aluminide, and aluminum oxide |
US5573171A (en) * | 1995-02-16 | 1996-11-12 | Trw Inc. | Method of thin film patterning by reflow |
JPH09115829A (ja) * | 1995-10-17 | 1997-05-02 | Nissan Motor Co Ltd | アルミニウム配線部を有する半導体装置およびその製造方法 |
JPH1027797A (ja) * | 1996-07-10 | 1998-01-27 | Oki Electric Ind Co Ltd | Al/Ti積層配線およびその形成方法 |
US5956612A (en) * | 1996-08-09 | 1999-09-21 | Micron Technology, Inc. | Trench/hole fill processes for semiconductor fabrication |
US5998296A (en) * | 1997-04-16 | 1999-12-07 | Texas Instruments Incorporated | Method of forming contacts and vias in semiconductor |
US6077778A (en) * | 1997-04-17 | 2000-06-20 | Taiwan Semiconductor Manufacturing Company | Method of improving refresh time in DRAM products |
KR100241506B1 (ko) * | 1997-06-23 | 2000-03-02 | 김영환 | 반도체 소자의 금속 배선 형성 방법 |
KR100338008B1 (ko) * | 1997-11-20 | 2002-10-25 | 삼성전자 주식회사 | 질화 몰리브덴-금속 합금막과 그의 제조 방법, 액정표시장치용 배선과 그의 제조 방법 및 액정 표시 장치와 그의 제조방법 |
US6140236A (en) * | 1998-04-21 | 2000-10-31 | Kabushiki Kaisha Toshiba | High throughput A1-Cu thin film sputtering process on small contact via for manufacturable beol wiring |
JPH11340228A (ja) * | 1998-05-28 | 1999-12-10 | Fujitsu Ltd | Al合金配線を有する半導体装置 |
US6274486B1 (en) * | 1998-09-02 | 2001-08-14 | Micron Technology, Inc. | Metal contact and process |
US6096651A (en) * | 1999-01-11 | 2000-08-01 | Taiwan Semiconductor Manufacturing Company | Key-hole reduction during tungsten plug formation |
KR100358063B1 (ko) * | 1999-08-04 | 2002-10-25 | 주식회사 하이닉스반도체 | 반도체 소자의 캐패시터 제조 방법 |
US6833623B2 (en) * | 1999-08-11 | 2004-12-21 | Micron Technology, Inc. | Enhanced barrier liner formation for via |
JP2001060590A (ja) | 1999-08-20 | 2001-03-06 | Denso Corp | 半導体装置の電気配線及びその製造方法 |
JP2001127270A (ja) * | 1999-10-27 | 2001-05-11 | Nec Corp | 半導体装置及びその製造方法 |
JP4190118B2 (ja) * | 1999-12-17 | 2008-12-03 | 三菱電機株式会社 | 半導体装置、液晶表示装置および半導体装置の製造方法 |
US7192827B2 (en) * | 2001-01-05 | 2007-03-20 | Micron Technology, Inc. | Methods of forming capacitor structures |
JP4344101B2 (ja) * | 2001-02-14 | 2009-10-14 | Okiセミコンダクタ株式会社 | 配線構造部 |
KR100455380B1 (ko) * | 2002-02-27 | 2004-11-06 | 삼성전자주식회사 | 다층 배선 구조를 구비한 반도체 소자 및 그 제조 방법 |
KR100463178B1 (ko) * | 2002-04-19 | 2004-12-23 | 아남반도체 주식회사 | 반도체 소자의 금속배선 적층구조 형성 방법 |
US7170176B2 (en) * | 2003-11-04 | 2007-01-30 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device |
TWI467702B (zh) | 2005-03-28 | 2015-01-01 | Semiconductor Energy Lab | 記憶裝置和其製造方法 |
US9960118B2 (en) | 2016-01-20 | 2018-05-01 | Globalfoundries Inc. | Contact using multilayer liner |
US10418314B2 (en) * | 2017-11-01 | 2019-09-17 | Advanced Semiconductor Engineering, Inc. | External connection pad for semiconductor device package |
US20220352198A1 (en) * | 2021-04-29 | 2022-11-03 | Sandisk Technologies Llc | Three-dimensional memory device with intermetallic barrier liner and methods for forming the same |
Family Cites Families (29)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4410622A (en) * | 1978-12-29 | 1983-10-18 | International Business Machines Corporation | Forming interconnections for multilevel interconnection metallurgy systems |
JPS57208161A (en) * | 1981-06-18 | 1982-12-21 | Fujitsu Ltd | Semiconductor device |
JPS605560A (ja) * | 1983-06-23 | 1985-01-12 | Fujitsu Ltd | 半導体装置 |
CA1222543A (fr) * | 1984-04-11 | 1987-06-02 | Hydro-Quebec | Anodes denses d'alliages de lithium pour batteries tout solide |
JPS6190445A (ja) * | 1984-10-09 | 1986-05-08 | Nec Corp | 半導体装置 |
JP2581666B2 (ja) * | 1985-09-06 | 1997-02-12 | 株式会社日立製作所 | 配線構造体の製造方法 |
US4751198A (en) * | 1985-09-11 | 1988-06-14 | Texas Instruments Incorporated | Process for making contacts and interconnections using direct-reacted silicide |
JPS6351630A (ja) * | 1986-08-21 | 1988-03-04 | Sanken Electric Co Ltd | シリコン基板への電極形成法 |
JPS6373660A (ja) * | 1986-09-17 | 1988-04-04 | Fujitsu Ltd | 半導体装置 |
US4924295A (en) * | 1986-11-28 | 1990-05-08 | Siemens Aktiengesellschaft | Integrated semi-conductor circuit comprising at least two metallization levels composed of aluminum or aluminum compounds and a method for the manufacture of same |
US4910580A (en) * | 1987-08-27 | 1990-03-20 | Siemens Aktiengesellschaft | Method for manufacturing a low-impedance, planar metallization composed of aluminum or of an aluminum alloy |
US4987562A (en) * | 1987-08-28 | 1991-01-22 | Fujitsu Limited | Semiconductor layer structure having an aluminum-silicon alloy layer |
JP2581097B2 (ja) * | 1987-08-31 | 1997-02-12 | ソニー株式会社 | 半導体装置 |
JPH0719841B2 (ja) * | 1987-10-02 | 1995-03-06 | 株式会社東芝 | 半導体装置 |
US4962414A (en) * | 1988-02-11 | 1990-10-09 | Sgs-Thomson Microelectronics, Inc. | Method for forming a contact VIA |
US5070392A (en) * | 1988-03-18 | 1991-12-03 | Digital Equipment Corporation | Integrated circuit having laser-alterable metallization layer |
US5008730A (en) * | 1988-10-03 | 1991-04-16 | International Business Machines Corporation | Contact stud structure for semiconductor devices |
JP2537413B2 (ja) * | 1989-03-14 | 1996-09-25 | 三菱電機株式会社 | 半導体装置およびその製造方法 |
US4917759A (en) * | 1989-04-17 | 1990-04-17 | Motorola, Inc. | Method for forming self-aligned vias in multi-level metal integrated circuits |
JPH038359A (ja) * | 1989-06-06 | 1991-01-16 | Fujitsu Ltd | 半導体装置の製造方法 |
US5051812A (en) * | 1989-07-14 | 1991-09-24 | Hitachi, Ltd. | Semiconductor device and method for manufacturing the same |
JP2598335B2 (ja) * | 1990-08-28 | 1997-04-09 | 三菱電機株式会社 | 半導体集積回路装置の配線接続構造およびその製造方法 |
US5052812A (en) * | 1990-11-19 | 1991-10-01 | New Brunswick Scientific Co., Inc. | Bath shaker |
US5231053A (en) * | 1990-12-27 | 1993-07-27 | Intel Corporation | Process of forming a tri-layer titanium coating for an aluminum layer of a semiconductor device |
JP2660359B2 (ja) * | 1991-01-30 | 1997-10-08 | 三菱電機株式会社 | 半導体装置 |
JPH0529254A (ja) * | 1991-07-24 | 1993-02-05 | Sony Corp | 配線形成方法 |
US5200359A (en) * | 1991-10-03 | 1993-04-06 | Micron Technology, Inc. | Method of decreasing contact resistance between a lower elevation aluminum layer and a higher elevation electrically conductive layer |
US5358901A (en) * | 1993-03-01 | 1994-10-25 | Motorola, Inc. | Process for forming an intermetallic layer |
US5356836A (en) * | 1993-08-19 | 1994-10-18 | Industrial Technology Research Institute | Aluminum plug process |
-
1990
- 1990-08-28 JP JP2227061A patent/JP2598335B2/ja not_active Expired - Lifetime
-
1991
- 1991-08-20 IT ITMI912260A patent/IT1251290B/it active IP Right Grant
- 1991-08-26 KR KR1019910014771A patent/KR950014686B1/ko not_active IP Right Cessation
- 1991-08-27 DE DE4128421A patent/DE4128421C2/de not_active Expired - Lifetime
-
1993
- 1993-08-10 US US08/104,520 patent/US5313101A/en not_active Expired - Lifetime
-
1994
- 1994-03-15 US US08/213,417 patent/US5488014A/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
US5488014A (en) | 1996-01-30 |
JP2598335B2 (ja) | 1997-04-09 |
DE4128421C2 (de) | 1996-10-24 |
KR920005304A (ko) | 1992-03-28 |
KR950014686B1 (ko) | 1995-12-13 |
DE4128421A1 (de) | 1992-03-05 |
ITMI912260A1 (it) | 1992-02-29 |
JPH04107954A (ja) | 1992-04-09 |
US5313101A (en) | 1994-05-17 |
IT1251290B (it) | 1995-05-08 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
0001 | Granted | ||
TA | Fee payment date (situation as of event date), data collected since 19931001 |
Effective date: 19970829 |