DE69124735D1 - Integrierte Halbleiterschaltung - Google Patents

Integrierte Halbleiterschaltung

Info

Publication number
DE69124735D1
DE69124735D1 DE69124735T DE69124735T DE69124735D1 DE 69124735 D1 DE69124735 D1 DE 69124735D1 DE 69124735 T DE69124735 T DE 69124735T DE 69124735 T DE69124735 T DE 69124735T DE 69124735 D1 DE69124735 D1 DE 69124735D1
Authority
DE
Germany
Prior art keywords
semiconductor circuit
integrated semiconductor
integrated
circuit
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69124735T
Other languages
English (en)
Other versions
DE69124735T2 (de
Inventor
Tsukasa Shirotori
Kazutaka Nogami
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Toshiba Electronic Device Solutions Corp
Original Assignee
Toshiba Corp
Toshiba Microelectronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Toshiba Microelectronics Corp filed Critical Toshiba Corp
Publication of DE69124735D1 publication Critical patent/DE69124735D1/de
Application granted granted Critical
Publication of DE69124735T2 publication Critical patent/DE69124735T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G11C29/26—Accessing multiple arrays
    • G11C29/28—Dependent multiple arrays, e.g. multi-bit arrays
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
DE69124735T 1990-12-27 1991-12-24 Integrierte Halbleiterschaltung Expired - Fee Related DE69124735T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2418754A JPH0770240B2 (ja) 1990-12-27 1990-12-27 半導体集積回路

Publications (2)

Publication Number Publication Date
DE69124735D1 true DE69124735D1 (de) 1997-03-27
DE69124735T2 DE69124735T2 (de) 1997-07-03

Family

ID=18526542

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69124735T Expired - Fee Related DE69124735T2 (de) 1990-12-27 1991-12-24 Integrierte Halbleiterschaltung

Country Status (5)

Country Link
US (1) US5388104A (de)
EP (1) EP0492624B1 (de)
JP (1) JPH0770240B2 (de)
KR (1) KR960000346B1 (de)
DE (1) DE69124735T2 (de)

Families Citing this family (52)

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US5528600A (en) 1991-01-28 1996-06-18 Actel Corporation Testability circuits for logic arrays
JP3247937B2 (ja) * 1992-09-24 2002-01-21 株式会社日立製作所 論理集積回路
US5453992A (en) * 1993-08-02 1995-09-26 Texas Instruments Incorporated Method and apparatus for selectable parallel execution of test operations
US5831918A (en) * 1994-02-14 1998-11-03 Micron Technology, Inc. Circuit and method for varying a period of an internal control signal during a test mode
US5535164A (en) * 1995-03-03 1996-07-09 International Business Machines Corporation BIST tester for multiple memories
US5657443A (en) * 1995-05-16 1997-08-12 Hewlett-Packard Company Enhanced test system for an application-specific memory scheme
US5661732A (en) * 1995-05-31 1997-08-26 International Business Machines Corporation Programmable ABIST microprocessor for testing arrays with two logical views
US5689635A (en) * 1995-12-27 1997-11-18 Sgs-Thomson Microelectronics, Inc. Microprocessor memory test circuit and method
US5721863A (en) * 1996-01-29 1998-02-24 International Business Machines Corporation Method and structure for accessing semi-associative cache memory using multiple memories to store different components of the address
JPH09223065A (ja) * 1996-02-16 1997-08-26 Kikusui Electron Corp メモリ容量テスト方法およびコンピュータ・システム
US5796745A (en) * 1996-07-19 1998-08-18 International Business Machines Corporation Memory array built-in self test circuit for testing multi-port memory arrays
US6253302B1 (en) * 1996-08-29 2001-06-26 Intel Corporation Method and apparatus for supporting multiple overlapping address spaces on a shared bus
US5831988A (en) * 1997-01-23 1998-11-03 Unisys Corporation Fault isolating to a block of ROM
US5862151A (en) * 1997-01-23 1999-01-19 Unisys Corporation Array self-test fault tolerant programmable threshold algorithm
US5961653A (en) * 1997-02-19 1999-10-05 International Business Machines Corporation Processor based BIST for an embedded memory
US5954830A (en) * 1997-04-08 1999-09-21 International Business Machines Corporation Method and apparatus for achieving higher performance data compression in ABIST testing by reducing the number of data outputs
US6001662A (en) * 1997-12-02 1999-12-14 International Business Machines Corporation Method and system for providing a reusable configurable self-test controller for manufactured integrated circuits
US5896331A (en) * 1997-12-23 1999-04-20 Lsi Logic Corporation Reprogrammable addressing process for embedded DRAM
US5907511A (en) * 1997-12-23 1999-05-25 Lsi Logic Corporation Electrically selectable redundant components for an embedded DRAM
US5901095A (en) * 1997-12-23 1999-05-04 Lsi Logic Corporation Reprogrammable address selector for an embedded DRAM
US5995731A (en) * 1997-12-29 1999-11-30 Motorola, Inc. Multiple BIST controllers for testing multiple embedded memory arrays
KR19990069337A (ko) * 1998-02-06 1999-09-06 윤종용 복합 반도체 메모리장치의자기 테스트 회로 및 이를 이용한 자기 테스트 방법
JP3553786B2 (ja) * 1998-03-13 2004-08-11 松下電器産業株式会社 半導体集積回路装置およびその製造方法
US5999440A (en) * 1998-03-30 1999-12-07 Lsi Logic Corporation Embedded DRAM with noise-protecting substrate isolation well
US6064588A (en) * 1998-03-30 2000-05-16 Lsi Logic Corporation Embedded dram with noise-protected differential capacitor memory cells
TW411463B (en) * 1998-06-23 2000-11-11 Nat Science Council Built-in self test for multiple memories in a chip
US6005824A (en) * 1998-06-30 1999-12-21 Lsi Logic Corporation Inherently compensated clocking circuit for dynamic random access memory
US5978304A (en) * 1998-06-30 1999-11-02 Lsi Logic Corporation Hierarchical, adaptable-configuration dynamic random access memory
EP1105876A4 (de) * 1998-08-21 2003-09-17 Credence Systems Corp Verfahren und apparat zum eingebauten selbsttesten von integrierten schaltungen
KR100308621B1 (ko) 1998-11-19 2001-12-17 윤종용 반도체 메모리 장치를 위한 프로그램 가능한 내장 자기 테스트 시스템
JP3913413B2 (ja) * 1999-08-25 2007-05-09 富士通株式会社 半導体装置
DE10037794A1 (de) * 2000-08-03 2002-02-21 Infineon Technologies Ag Verfahren und Vorrichtung zum Testen einer integrierten Schaltung, zu testende integrierte Schaltung, und Wafer mit einer Vielzahl von zu testenden integrierten Schaltungen
US7444575B2 (en) * 2000-09-21 2008-10-28 Inapac Technology, Inc. Architecture and method for testing of an integrated circuit device
US7240254B2 (en) * 2000-09-21 2007-07-03 Inapac Technology, Inc Multiple power levels for a chip within a multi-chip semiconductor package
US6812726B1 (en) * 2002-11-27 2004-11-02 Inapac Technology, Inc. Entering test mode and accessing of a packaged semiconductor device
US6658610B1 (en) * 2000-09-25 2003-12-02 International Business Machines Corporation Compilable address magnitude comparator for memory array self-testing
US20020174394A1 (en) * 2001-05-16 2002-11-21 Ledford James S. External control of algorithm execution in a built-in self-test circuit and method therefor
US8001439B2 (en) * 2001-09-28 2011-08-16 Rambus Inc. Integrated circuit testing module including signal shaping interface
US8286046B2 (en) 2001-09-28 2012-10-09 Rambus Inc. Integrated circuit testing module including signal shaping interface
US7313740B2 (en) * 2002-07-25 2007-12-25 Inapac Technology, Inc. Internally generating patterns for testing in an integrated circuit device
US8166361B2 (en) * 2001-09-28 2012-04-24 Rambus Inc. Integrated circuit testing module configured for set-up and hold time testing
DE10245713B4 (de) * 2002-10-01 2004-10-28 Infineon Technologies Ag Testsystem und Verfahren zum Testen von Speicherschaltungen
US8063650B2 (en) 2002-11-27 2011-11-22 Rambus Inc. Testing fuse configurations in semiconductor devices
JP4381014B2 (ja) 2003-03-18 2009-12-09 株式会社ルネサステクノロジ 半導体集積回路
US6993692B2 (en) * 2003-06-30 2006-01-31 International Business Machines Corporation Method, system and apparatus for aggregating failures across multiple memories and applying a common defect repair solution to all of the multiple memories
US7194670B2 (en) * 2004-02-13 2007-03-20 International Business Machines Corp. Command multiplier for built-in-self-test
US7246280B2 (en) * 2004-03-23 2007-07-17 Samsung Electronics Co., Ltd. Memory module with parallel testing
JP2007287223A (ja) * 2006-04-14 2007-11-01 Phison Electronics Corp フラッシュメモリー及びその使用方法
KR20080089015A (ko) * 2007-03-30 2008-10-06 주식회사 하이닉스반도체 테스트 코드롬을 구비한 반도체 메모리 장치
JP5074968B2 (ja) * 2008-03-18 2012-11-14 ルネサスエレクトロニクス株式会社 集積回路及びメモリテスト方法
JP5310654B2 (ja) * 2010-06-10 2013-10-09 富士通セミコンダクター株式会社 メモリ装置及びメモリシステム
CN103093829A (zh) * 2011-10-27 2013-05-08 迈实电子(上海)有限公司 存储器测试系统及存储器测试方法

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4577314A (en) * 1983-03-31 1986-03-18 At&T Bell Laboratories Digital multi-customer data interface
US4713748A (en) * 1985-02-12 1987-12-15 Texas Instruments Incorporated Microprocessor with block move instruction
JPH0733100Y2 (ja) * 1988-05-19 1995-07-31 三順 中嶋 ジョッキ用保冷具
CA1286803C (en) * 1989-02-28 1991-07-23 Benoit Nadeau-Dostie Serial testing technique for embedded memories
US5072138A (en) * 1990-08-17 1991-12-10 Sgs-Thomson Microelectronics, Inc. Semiconductor memory with sequential clocked access codes for test mode entry

Also Published As

Publication number Publication date
KR920013476A (ko) 1992-07-29
JPH04229499A (ja) 1992-08-18
US5388104A (en) 1995-02-07
JPH0770240B2 (ja) 1995-07-31
DE69124735T2 (de) 1997-07-03
KR960000346B1 (ko) 1996-01-05
EP0492624B1 (de) 1997-02-19
EP0492624A1 (de) 1992-07-01

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee