EP1105876A4 - Verfahren und apparat zum eingebauten selbsttesten von integrierten schaltungen - Google Patents

Verfahren und apparat zum eingebauten selbsttesten von integrierten schaltungen

Info

Publication number
EP1105876A4
EP1105876A4 EP98945762A EP98945762A EP1105876A4 EP 1105876 A4 EP1105876 A4 EP 1105876A4 EP 98945762 A EP98945762 A EP 98945762A EP 98945762 A EP98945762 A EP 98945762A EP 1105876 A4 EP1105876 A4 EP 1105876A4
Authority
EP
European Patent Office
Prior art keywords
built
integrated circuits
self test
self
test
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP98945762A
Other languages
English (en)
French (fr)
Other versions
EP1105876A1 (de
Inventor
Y D Lepejian
Hrant Marandjian
Hovhannes Ghukasyan
Lawrence Kraus
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Credence Systems Corp
Original Assignee
Credence Systems Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Credence Systems Corp filed Critical Credence Systems Corp
Publication of EP1105876A1 publication Critical patent/EP1105876A1/de
Publication of EP1105876A4 publication Critical patent/EP1105876A4/de
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
EP98945762A 1998-08-21 1998-08-21 Verfahren und apparat zum eingebauten selbsttesten von integrierten schaltungen Withdrawn EP1105876A4 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/US1998/017298 WO2000011674A1 (en) 1998-08-21 1998-08-21 Method and apparatus for built-in self test of integrated circuits

Publications (2)

Publication Number Publication Date
EP1105876A1 EP1105876A1 (de) 2001-06-13
EP1105876A4 true EP1105876A4 (de) 2003-09-17

Family

ID=22267708

Family Applications (1)

Application Number Title Priority Date Filing Date
EP98945762A Withdrawn EP1105876A4 (de) 1998-08-21 1998-08-21 Verfahren und apparat zum eingebauten selbsttesten von integrierten schaltungen

Country Status (4)

Country Link
EP (1) EP1105876A4 (de)
JP (1) JP2002523854A (de)
KR (1) KR100589532B1 (de)
WO (1) WO2000011674A1 (de)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6550034B1 (en) * 2000-02-17 2003-04-15 Hewlett Packard Development Company, L.P. Built-in self test for content addressable memory
US6658610B1 (en) * 2000-09-25 2003-12-02 International Business Machines Corporation Compilable address magnitude comparator for memory array self-testing
JP2006252702A (ja) * 2005-03-11 2006-09-21 Nec Electronics Corp 半導体集積回路装置及びその検査方法
JP2008065862A (ja) * 2006-09-04 2008-03-21 System Fabrication Technologies Inc 半導体記憶装置
US8185694B2 (en) * 2008-07-25 2012-05-22 International Business Machines Corporation Testing real page number bits in a cache directory
KR101232195B1 (ko) * 2011-02-25 2013-02-12 연세대학교 산학협력단 반도체 메모리 장치 테스트 방법 및 테스트 장치

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0492624A1 (de) * 1990-12-27 1992-07-01 Kabushiki Kaisha Toshiba Integrierte Halbleiterschaltung
US5258986A (en) * 1990-09-19 1993-11-02 Vlsi Technology, Inc. Tightly coupled, low overhead RAM built-in self-test logic with particular applications for embedded memories
US5477494A (en) * 1992-05-26 1995-12-19 Ando Electric Co., Ltd. Apparatus for generating address bit patterns for testing semiconductor memory devices
US5588111A (en) * 1988-12-09 1996-12-24 Tandem Computers, Incorporated Fault-tolerant computer system having switchable I/O bus interface modules
US5615159A (en) * 1995-11-28 1997-03-25 Micron Quantum Devices, Inc. Memory system with non-volatile data storage unit and method of initializing same
US5659551A (en) * 1995-05-31 1997-08-19 International Business Machines Corporation Programmable computer system element with built-in self test method and apparatus for repair during power-on
US5661732A (en) * 1995-05-31 1997-08-26 International Business Machines Corporation Programmable ABIST microprocessor for testing arrays with two logical views

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4817093A (en) * 1987-06-18 1989-03-28 International Business Machines Corporation Method of partitioning, testing and diagnosing a VLSI multichip package and associated structure
KR0141432B1 (ko) * 1993-10-01 1998-07-15 기다오까 다까시 반도체 기억장치
US5617531A (en) * 1993-11-02 1997-04-01 Motorola, Inc. Data Processor having a built-in internal self test controller for testing a plurality of memories internal to the data processor
US5805789A (en) * 1995-12-14 1998-09-08 International Business Machines Corporation Programmable computer system element with built-in self test method and apparatus for repair during power-on

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5588111A (en) * 1988-12-09 1996-12-24 Tandem Computers, Incorporated Fault-tolerant computer system having switchable I/O bus interface modules
US5258986A (en) * 1990-09-19 1993-11-02 Vlsi Technology, Inc. Tightly coupled, low overhead RAM built-in self-test logic with particular applications for embedded memories
EP0492624A1 (de) * 1990-12-27 1992-07-01 Kabushiki Kaisha Toshiba Integrierte Halbleiterschaltung
US5477494A (en) * 1992-05-26 1995-12-19 Ando Electric Co., Ltd. Apparatus for generating address bit patterns for testing semiconductor memory devices
US5659551A (en) * 1995-05-31 1997-08-19 International Business Machines Corporation Programmable computer system element with built-in self test method and apparatus for repair during power-on
US5661732A (en) * 1995-05-31 1997-08-26 International Business Machines Corporation Programmable ABIST microprocessor for testing arrays with two logical views
US5615159A (en) * 1995-11-28 1997-03-25 Micron Quantum Devices, Inc. Memory system with non-volatile data storage unit and method of initializing same

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of WO0011674A1 *

Also Published As

Publication number Publication date
WO2000011674A1 (en) 2000-03-02
KR100589532B1 (ko) 2006-06-13
EP1105876A1 (de) 2001-06-13
KR20010052985A (ko) 2001-06-25
JP2002523854A (ja) 2002-07-30

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