EP1818971A4 - Verfahren zur herstellung eines direktkontakt-wafers und direktkontakt-wafer - Google Patents
Verfahren zur herstellung eines direktkontakt-wafers und direktkontakt-waferInfo
- Publication number
- EP1818971A4 EP1818971A4 EP05811712A EP05811712A EP1818971A4 EP 1818971 A4 EP1818971 A4 EP 1818971A4 EP 05811712 A EP05811712 A EP 05811712A EP 05811712 A EP05811712 A EP 05811712A EP 1818971 A4 EP1818971 A4 EP 1818971A4
- Authority
- EP
- European Patent Office
- Prior art keywords
- direct bond
- bond wafer
- manufacturing
- wafer
- manufacturing direct
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title 1
- 238000000034 method Methods 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
- H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
- H01L21/2007—Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2004346235A JP4830290B2 (ja) | 2004-11-30 | 2004-11-30 | 直接接合ウェーハの製造方法 |
| PCT/JP2005/021841 WO2006059586A1 (ja) | 2004-11-30 | 2005-11-29 | 直接接合ウェーハの製造方法及び直接接合ウェーハ |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| EP1818971A1 EP1818971A1 (de) | 2007-08-15 |
| EP1818971A4 true EP1818971A4 (de) | 2008-01-23 |
| EP1818971B1 EP1818971B1 (de) | 2016-04-27 |
Family
ID=36565020
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| EP05811712.8A Active EP1818971B1 (de) | 2004-11-30 | 2005-11-29 | Verfahren zur herstellung eines direktgebondeten-wafers |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US7521334B2 (de) |
| EP (1) | EP1818971B1 (de) |
| JP (1) | JP4830290B2 (de) |
| WO (1) | WO2006059586A1 (de) |
Families Citing this family (280)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7066234B2 (en) | 2001-04-25 | 2006-06-27 | Alcove Surfaces Gmbh | Stamping tool, casting mold and methods for structuring a surface of a work piece |
| CN1922732B (zh) * | 2004-02-25 | 2010-06-09 | S.O.I.Tec绝缘体上硅技术公司 | 光电检测装置 |
| JP2008060355A (ja) * | 2006-08-31 | 2008-03-13 | Sumco Corp | 貼り合わせウェーハの製造方法および貼り合わせウェーハ |
| JP2008072049A (ja) * | 2006-09-15 | 2008-03-27 | Sumco Corp | 貼り合わせウェーハの製造方法 |
| JP2008177530A (ja) * | 2006-12-21 | 2008-07-31 | Covalent Materials Corp | 半導体基板およびその製造方法 |
| EP2095415B1 (de) * | 2006-12-26 | 2010-10-27 | S.O.I.Tec Silicon on Insulator Technologies | Verfahren zum herstellen einer halbleiter-auf-isolator-struktur |
| JP4820801B2 (ja) * | 2006-12-26 | 2011-11-24 | 株式会社Ｓｕｍｃｏ | 貼り合わせウェーハの製造方法 |
| WO2008114099A1 (en) | 2007-03-19 | 2008-09-25 | S.O.I.Tec Silicon On Insulator Technologies | Patterned thin soi |
| JP2008235776A (ja) * | 2007-03-23 | 2008-10-02 | Sumco Corp | 貼り合わせウェーハの製造方法 |
| EP1986229A1 (de) * | 2007-04-27 | 2008-10-29 | S.O.I.T.E.C. Silicon on Insulator Technologies | Herstellungsverfahren für Wafer aus Verbundmaterial und entsprechender Wafer aus Verbundmaterial |
| JP2011504655A (ja) | 2007-11-23 | 2011-02-10 | エス． オー． アイ． テック シリコン オン インシュレーター テクノロジーズ | 精密な酸化物の溶解 |
| JP2009176860A (ja) * | 2008-01-23 | 2009-08-06 | Sumco Corp | 貼り合わせウェーハの製造方法 |
| JP5040682B2 (ja) * | 2008-01-28 | 2012-10-03 | 信越半導体株式会社 | 直接接合ウェーハの検査方法 |
| JP5572914B2 (ja) * | 2008-03-26 | 2014-08-20 | 信越半導体株式会社 | 直接接合ウェーハの製造方法 |
| JP5493345B2 (ja) | 2008-12-11 | 2014-05-14 | 信越半導体株式会社 | Ｓｏｉウェーハの製造方法 |
| EP2305026B1 (de) * | 2008-12-25 | 2014-01-22 | Sharp Kabushiki Kaisha | Aquarium |
| US9394608B2 (en) | 2009-04-06 | 2016-07-19 | Asm America, Inc. | Semiconductor processing reactor and components thereof |
| US8802201B2 (en) | 2009-08-14 | 2014-08-12 | Asm America, Inc. | Systems and methods for thin-film deposition of metal oxides using excited nitrogen-oxygen species |
| CN102498667A (zh) * | 2009-09-18 | 2012-06-13 | 住友电气工业株式会社 | 基板、基板的制造方法、saw器件以及器件 |
| JP5549167B2 (ja) * | 2009-09-18 | 2014-07-16 | 住友電気工業株式会社 | Ｓａｗデバイス |
| WO2012033125A1 (ja) | 2010-09-07 | 2012-03-15 | 住友電気工業株式会社 | 基板、基板の製造方法およびｓａｗデバイス |
| FR2972564B1 (fr) | 2011-03-08 | 2016-11-04 | S O I Tec Silicon On Insulator Tech | Procédé de traitement d'une structure de type semi-conducteur sur isolant |
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Also Published As
| Publication number | Publication date |
|---|---|
| JP2006156770A (ja) | 2006-06-15 |
| WO2006059586A1 (ja) | 2006-06-08 |
| EP1818971A1 (de) | 2007-08-15 |
| US20080102603A1 (en) | 2008-05-01 |
| US7521334B2 (en) | 2009-04-21 |
| JP4830290B2 (ja) | 2011-12-07 |
| EP1818971B1 (de) | 2016-04-27 |
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