EP1020905B1 - Verfahren zur Herstellung einer integrierten Schaltungsanordnung mit Doppeldamaszen-Kontaktstruktur und Metallelektroden-Kondensator - Google Patents

Verfahren zur Herstellung einer integrierten Schaltungsanordnung mit Doppeldamaszen-Kontaktstruktur und Metallelektroden-Kondensator Download PDF

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EP1020905B1
EP1020905B1 EP00300072A EP00300072A EP1020905B1 EP 1020905 B1 EP1020905 B1 EP 1020905B1 EP 00300072 A EP00300072 A EP 00300072A EP 00300072 A EP00300072 A EP 00300072A EP 1020905 B1 EP1020905 B1 EP 1020905B1
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opening
capacitor
metal
layer
dielectric layer
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EP1020905A1 (de
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Sung Chun-Yung
Yen Allen
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Nokia of America Corp
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Lucent Technologies Inc
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    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
    • H01L23/5223—Capacitor integral with wiring layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/022—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
    • H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
    • H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
    • H01L21/31604—Deposition from a gas or vapour
    • H01L21/31608—Deposition of SiO2
    • H01L21/31612—Deposition of SiO2 on a silicon body
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
    • H01L21/318—Inorganic layers composed of nitrides
    • H01L21/3185—Inorganic layers composed of nitrides of siliconnitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the present invention relates to the field of integrated circuits, and, more particularly, to integrated circuit devices having capacitors.
  • Capacitors are used in semiconductor devices such as integrated circuits (ICs) for storing electrical charge.
  • ICs such as dynamic random access memory (DRAM)
  • capacitors are used for storage in the memory cells.
  • capacitors formed in ICs include a lower electrode made of, e.g., polycrystalline silicon (polysilicon), a dielectric layer made of, e.g., tantalum pentoxide and/or barium strontium titantate, and an upper electrode made of, e.g., titanium nitride, titanium, tungsten, platinum or polysilicon.
  • the development of the semiconductor memory device has required higher packing density, the area occupied by a capacitor of a DRAM storage cell shrinks, thus decreasing the capacitance of the capacitor because of its smaller electrode surface area.
  • a relatively large capacitance is required to achieve a high signal-to-noise ratio in reading the memory cell. Therefore, it is desirable to reduce the cell dimension and yet obtain a high capacitance. This can be accomplished with a metal electrode capacitor, for example, which also may include a high-k dielectric.
  • a plug structure such as a tungsten plug, for example, for an electrical connection between first and second metal lines.
  • Such structures require three separate processing steps including one for the formation of each of the two conductors and one for the formation of the tungsten plug structure.
  • greater interest has been shown by manufacturers of semiconductor devices in the use of copper and copper alloys for metallization patterns, such as in conductive vias and interconnects. Copper, compared to aluminum, has both good electromigration resistance and a relatively low electrical resistivity of about 1.7 ohm cm. Unfortunately, copper is difficult to etch. Consequently, dual damascene processes have been developed to simplify the process steps and eliminate a metal etch step to form copper interconnects. Dual damascene processes are also used with aluminum interconnects.
  • a dual damascene structure has a bottom portion or via that contacts an underlying conductor and replaces the function of a plug structure in a traditional interconnect structure.
  • the dual damascene structure also has a top portion or inlaid trench that is used for the formation of a second conductor. Because the bottom and top portions of a dual damascene structure are in contact with each other, they can be filled simultaneously with the same conductive material, e.g. copper. This eliminates the need to form a plug structure and an overlying conductive layer in separate processing steps.
  • capacitors are usually formed in a separate level by depositing a first conductive layer, forming the dielectric therebetween, forming a second conductive layer, and then patterning and etching the layered structure.
  • the conductive layers are typically formed of poly-silicon or titanium nitride, for example.
  • an oxide is formed over the capacitors and results in surface topographies above the capacitors. This requires chemical mechanical polishing (CMP) to planarise the oxide layer before subsequent layers are formed.
  • CMP chemical mechanical polishing
  • the conventional process of making capacitors requires additional time due to the etching of the conductive layers as well as the CMP step.
  • the metal etch step required is not fully compatible with the dual damascene process.
  • the dual damascene process is used specifically to avoid metal etching; therefore, using a metal etch step within a dual damascene process is undesirable.
  • EP-A-0 771 022 discloses a technique for forming a precision metal-metal capacitor for an analog circuit.
  • a trench is formed in an insulation layer, and metal deposited therein. This forms a first capacitor plate.
  • the device is then planarised.
  • a thin dielectric is then deposited and patterned.
  • a second insulator is deposited and discrete openings etched therein to expose the insulation layer and the first metal plate.
  • Metal is deposited within the openings and planarised.
  • U.S. Patent No. 4,958,318 discloses a dynamic RAM including a storage capacitor.
  • the first electrode of the capacitor consists of a thick conductive layer whose vertical sidewalls provide an extra surface area.
  • the second electrode is used to partially planarise the surface topology. Further examples of prior art can be found in U.S. Patent No. 5,459,100 , U.S. Patent No. 5,151,168 , and JP 02 143456 .
  • the first conductive layer is formed while masking the second opening, may be formed by electroplating copper, and may also include a barrier metal layer to at least line the first opening.
  • the barrier metal layer preferably comprises tantalum nitride
  • the step of simultaneously forming the first opening and the second opening may comprise: simultaneously forming an upper portion of the first opening and an upper portion of the second opening; and simultaneously forming a lower portion of the first opening and a lower portion of the second opening.
  • the upper portion of the first opening may have a greater width than the lower portion of the first opening, and the upper portion of the second opening may have substantially a same width as the lower portion of the second opening.
  • the dielectric layer may be formed of a lower dielectric layer portion, an etch stop layer and an upper dielectric layer portion.
  • the upper portion of the first opening and the upper portion of the second opening may be formed simultaneously in the upper dielectric layer portion and the etch stop layer.
  • the lower portion of the first opening and the lower portion of the second opening may be formed simultaneously in the lower dielectric layer portion.
  • the capacitor may be formed by depositing a lower metal layer to at least line the second opening and to form the lower metal electrode, forming the capacitor dielectric layer on the lower metal layer, depositing an upper metal layer on the capacitor dielectric layer to form the upper metal electrode.
  • a second conductive layer may be selectively deposited to fill a remaining portion of the second opening.
  • This second conductive layer preferably comprises copper, and the upper and lower metal electrodes of the capacitor preferably comprise tantalum nitride.
  • the capacitor dielectric may be a high-k dielectric having, e.g., a dielectric constant greater than about 25.
  • an integrated circuit device including a dielectric layer adjacent a semiconductor substrate having first and second openings therein, an interconnect structure in the first opening and comprising a metal line and a metal contact depending therefrom, and a capacitor in the second opening and comprising upper and lower metal electrodes with a capacitor dielectric layer therebetween.
  • the capacitor may have a substantially planar upper surface substantially flush with adjacent upper surface portions of the dielectric layer. Also, the edges of the lower electrode and the capacitor dielectric layer may terminate at the upper surface of the capacitor.
  • the dielectric layer may comprise a lower dielectric layer portion, an etch stop layer, and an upper dielectric layer portion.
  • the metal line of the interconnect structure is preferably in the upper dielectric layer portion and the etch stop layer of the dielectric layer, and the contact of the interconnect structure is preferably in the lower dielectric layer portion of the dielectric layer.
  • the capacitor is preferably in the upper dielectric layer portion, the etch stop layer, and the lower dielectric layer portion of the dielectric layer.
  • the semiconductor substrate 30 is preferably silicon, or may be silicon or a polysilicon layer or structure formed on the substrate.
  • a plurality of devices, such as transistors (not shown), are formed in the substrate 30 using well known techniques.
  • the integrated circuit device 20 includes a first dielectric layer 32 adjacent the substrate 30 .
  • the first dielectric layer is formed from any suitable dielectric, e.g., silicon dioxide, silicon nitride and/or any material or alloy of material having a desired dielectric constant.
  • suitable materials include tantalum pentoxide and barium strontium titantate, for example, as long as the dielectric does not affect the formation of the interconnect structure and the capacitor.
  • This first dielectric layer 32 is shown in FIG. 1 with interconnects 34 and 36 .
  • the first dielectric layer 32 and the interconnects 34 and 36 illustrate an example of an underlying level of the integrated circuit device.
  • a via is an opening formed in an interlevel dielectric layer to expose a certain portion of an underlying metal line to allow electrical contact to be made to the line.
  • a conductive contact is then formed in the via to connect the underlying metal line with a subsequently formed overlying metal line.
  • the integrated circuit device 20 further includes a second dielectric layer 38 and a third dielectric layer 42 .
  • the second and third dielectric layers 38 and 42 are preferably separated by an etch stop layer 40 .
  • the second and third dielectric layers 38 and 42 are formed from any suitable dielectric having a desired dielectric constant, as would readily be appreciated by the skilled artisan.
  • the etch stop layer 40 is typically formed from silicon nitride and deposited by conventional techniques.
  • the interconnect structure 22 includes a metal line 27 and a contact 2 6 .
  • the metal line 27 is formed in the third dielectric layer 42 and the etch stop layer 40 .
  • the contact is formed in the second dielectric layer 38 .
  • the interconnect structure 22 comprises a barrier metal layer 52 and a metal conductive layer 54 .
  • the barrier metal layer may be formed of any suitable metal layer, e.g., tantalum nitride, titanium nitride or tungsten nitride, which will substantially prohibit diffusion of the metal from the metal conductive layer 54 into the dielectric layers 38 and 42 .
  • the conductive metal layer 54 is preferably copper but may include aluminum or tungsten, for example.
  • a copper seed layer (not shown) is also typically formed on the barrier metal layer 52 , as will be readily appreciated by those skilled in the art.
  • the capacitor 24 includes a lower electrode 44 , a dielectric 46 , and an upper electrode 49 .
  • the lower electrode 44 is formed of at least one layer of a conductive metal such as tantalum nitride, for example.
  • the lower electrode 44 illustratively includes two metal layers 52 , 53 , such as formed of tantalum nitride.
  • a copper seed layer, not shown, may also be formed between the two tantalum nitride layers 52 , 53 when copper is used as the interconnection metal as will be understood by those skilled in the art.
  • the capacitor dielectric 46 is formed of a suitable dielectric material, e.g. silicon oxide, silicon nitride or tantalum oxide, having a desired dielectric constant.
  • a suitable dielectric material e.g. silicon oxide, silicon nitride or tantalum oxide, having a desired dielectric constant.
  • the capacitor dielectric 46 has a dielectric constant greater than about 25 to achieve desired capacitor characteristics.
  • the upper electrode 49 illustratively comprises conductive metal layer 48 and conductive metal layer 50 .
  • the conductive metal layer 48 may be formed of tantalum nitride, for example, and the conductive metal layer 50 may be formed of copper. Of course, a copper seed layer, not shown, may be between the two layers 48 , 50 .
  • the conductive metal layer 48 may also act as a barrier layer to prohibit diffusion of the metal, e.g. copper, from the metal conductive layer 50 into the dielectric 46 .
  • the capacitor 24 has a substantially planar upper surface substantially flush with adjacent upper surface portions of the third dielectric layer 42 . Also, edges of the lower metal 44 electrode and the capacitor dielectric 46 terminate at the upper surface of the capacitor 24 .
  • the integrated circuit device 20 provides a high-density capacitor 24 having metal electrodes 44 , 49 and which is compatible and integrated with dual damascene structures. As such, the capacitor 24 is situated in a same level as the dual damascene interconnect structure 22 .
  • a dual damascene process for making the integrated circuit device 20 including an interconnect structure 22 and metal electrode capacitor 24 formed on a semiconductor substrate 30 in accordance with the present invention will now be described.
  • a semiconductor substrate 30 is provided, and a first dielectric layer 32 is formed adjacent the semiconductor substrate by conventional techniques.
  • the semiconductor substrate 30 is preferably silicon.
  • a plurality of devices are formed in the substrate 30 using well known techniques.
  • the semiconductor substrate 30 and other associated layers form a semiconductor wafer as known to those skilled in the art.
  • the first dielectric layer 32 can be formed of silicon dioxide as well as other known dielectrics. Of course, the first dielectric layer 32 may be deposited or grown. Further, the first dielectric layer 32 includes interconnects 34 and 36 .
  • the interconnects 34 and 36 are formed by depositing a conductive metal, e.g. aluminum and/or copper, in trenches which have been etched in the first dielectric layer 32 .
  • the first dielectric layer 32 and the interconnects 34 and 36 illustrate an example of an underlying level of the integrated circuit device.
  • a second dielectric layer 38 is formed adjacent the first dielectric layer 32 and the interconnects 34 and 36 .
  • An etch stop layer 40 is formed over the second oxide layer 38 as illustrated.
  • a third dielectric layer 42 is formed adjacent the etch stop layer 40 .
  • the second and third dielectric layers 38 and 42 are formed from any suitable dielectric having a desired dielectric constant, and are deposited or grown as would readily be appreciated by the skilled artisan.
  • the etch stop layer 40 is typically formed from silicon nitride and deposited by conventional techniques. This nonconductive silicon nitride etch stop layer 40 is typically deposited on the associated dielectric layer, e.g. the second dielectric layer 38, using CVD at temperatures between about 600 C and 900 C.
  • a first set of openings 56 and 57 are selectively formed through the third dielectric layer 42 and also through the etch stop layer 40 .
  • the present description proceeds with the etching of the third dielectric layer 42 followed by the etching of the etch stop layer 40 , other etching steps for etching the third dielectric layer and the etch stop layer can be used as would readily be appreciated by those skilled in the art.
  • the openings, e.g., trenches 56 and 57 will later be used to form a metallization conductor or a capacitor as will be explained below.
  • the opening 62 is for forming a via between different layers, as is well known to those skilled in the art.
  • the opening 60 has been illustrated, as an example, as being substantially the same width as the above opening 56 in the third dielectric layer 42 , this opening 60 may also be more narrow than the above opening 56 as is the case with openings 61 and 57 .
  • a photo resist 62 is formed over the openings 56 and 60 .
  • a barrier metal layer 52 is preferably formed to line openings 56 , 57 , 60 and 61 before the photo resist 62 is formed.
  • a conductive metal layer 54 e.g. aluminum and/or copper, is selectively deposited over the third dielectric layer 42 , such that the conductive metal layer 54 is deposited within the openings 57 and 61 and over at least portions of the third dielectric layer 42 adjacent the opening 57 .
  • the conductive metal layer 54 can be deposited by electrodeposition, electroplating or chemical vapor deposition techniques well known to those skilled in the art. Of course if copper is used as the conductive metal layer 54 , a copper seed layer (not shown) may be formed on the barrier metal layer 52 .
  • the photo resist 62 is then removed and the openings 56 and 60 are cleaned by techniques known to those skilled in the art.
  • a barrier metal layer 53 such as tantalum nitride, titanium nitride or tungsten nitride, for example, is then deposited to complete the lower electrode 44 .
  • the capacitor dielectric 46 is formed by deposition or epitaxial growth.
  • the capacitor dielectric 46 is formed of a suitable dielectric material, e.g. silicon oxide, silicon nitride or tantalum oxide, having a desired dielectric constant.
  • the capacitor dielectric 46 has a dielectric constant greater than about 25 to achieve the desired capacitor characteristics.
  • a barrier metal layer 48 such as tantalum nitride, titanium nitride or tungsten nitride, for example, is then deposited to form part of the upper electrode 49 .
  • a barrier metal layer 48 such as tantalum nitride, titanium nitride or tungsten nitride, for example, is then deposited to form part of the upper electrode 49 .
  • the materials forming the electrodes 44 and 49 as well as the dielectric 46 have been blanket deposited over the upper surface of the integrated circuit device 20 .
  • a conductive metal layer 50 e.g. aluminum and/or copper, is deposited to form part the upper electrode 49 , such that the conductive metal layer 50 is deposited within a remaining portion of the openings 56 and 60 .
  • This deposition step may involve selective deposition including a photo resist 64 formed over the interconnect structure 22 , as illustrated. However, the conductive metal layer 50 may also be blanket deposited over the entire upper surface of the integrated circuit device 20 .
  • the conductive metal layer 50 can be deposited by electrodeposition, electroplating or chemical vapor deposition techniques well known to those skilled in the art. Of course if copper is used as the conductive metal layer 50 , a copper seed layer (not shown) may be formed on the upper electrode 48 .
  • an upper surface of the integrated circuit device is then planarized using CMP, for example, as shown in FIG. 8 .
  • the capacitor 24 has a substantially planar upper surface substantially flush with adjacent upper surface portions of the third dielectric layer 42 .
  • edges of the lower metal 44 electrode and the capacitor dielectric 46 terminate at the upper surface of the capacitor 24 .
  • a dual damascene process is provided for making the integrated circuit device 20 with a high-density capacitor 24 having metal electrodes 44 , 49 , and which is compatible and integrated with dual damascene structures such as the interconnect structure 22 .
  • the process of the present invention does not require etching metal layers or CMP of oxides to form a capacitor having metal electrodes.
  • FIG. 9 another example for an integrated circuit device 20 is described. Because the lower electrode 44 surrounds the capacitor 24 , a contact 66 may be formed in a side trench 68 to connect the capacitor 24 to an associated metal line such as the conductive layer 54 . In this embodiment, an interconnect 34 ( FIG. 1 ) would not be necessary to contact the lower electrode 44 . This may also eliminate a layer and allow reduction of the dimensions of the integrated circuit 20 . Furthermore, the trench 68 may be formed during the dielectric etch which forms the openings 56 and 57 . This would also reduce the number of steps required in making the integrated circuit device 20 .
  • the thicknesses of the various layers may vary as would be appreciated by those skilled in the art.
  • the first dielectric layer 32 can be deposited over the substrate by chemical vapor deposition (CVD) from a TEOS source gas and could have a thickness of about 400 to 600 nanometers or greater.
  • the second and third dielectric layers 38 and 42 can also be formed in a similar thickness range.
  • the appropriate silicon nitride etch stop layer 40 can have a thickness between about 200 to 1,500 angstroms, for example. Naturally, this is only a range of thickness, which can vary depending on the thickness desired and the end use of the semiconductor devices.

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Claims (10)

  1. Verfahren zur Herstellung eines integrierten Schaltungsbauelements (20) einschließlich einer Kontaktstruktur (22) und eines Kondensators (24), wobei die Kontaktstruktur eine Metallleiterbahn (27) und einen Metallkontakt (26) umfasst und der Kondensator obere (49) und untere (44) Metallelektroden umfasst, wobei das Verfahren folgende Schritte umfasst:
    Bildung einer Isolierschicht (38; 42), die an ein Halbleitersubstrat (30) angrenzt;
    gleichzeitige Bildung einer ersten Öffnung (57; 61) für die Kontaktstruktur und einer zweiten Öffnung (56; 60) für den Kondensator in der Isolierschicht;
    Bildung einer Maske (62) über der zweiten Öffnung;
    selektives Aufbringen einer ersten leitenden Metallschicht (54), um die erste Öffnung zu füllen, wobei die Maske die zweite Öffnung schützt;
    Entfernen der Maske von der zweiten Öffnung;
    Aufbringen einer unteren Metallschicht (52 oder 53), um zumindest die zweite Öffnung auszukleiden und um die untere Elektrode des Kondensators zu bilden;
    Bildung einer Kondensator-Isolierschicht (46) auf der unteren Metallschicht, um den Kondensator-Isolator des Kondensators zu bilden;
    Aufbringen einer oberen Metallschicht (48) auf die Kondensator-Isolierschicht, um Teil der oberen Metallelektrode des Kondensators zu bilden;
    Aufbringen einer zweiten leitenden Schicht (50), um einen restlichen Teil der zweiten Öffnung zu füllen und Teil der oberen Metallelektrode des Kondensators zu bilden; und
    Planarisieren einer oberen Fläche des integrierten Schaltungsbauelements.
  2. Verfahren nach Anspruch 1, wobei der Schritt gleichzeitige Bildung der ersten Öffnung und der zweiten Öffnung umfasst:
    gleichzeitige Bildung eines oberen Teils (57) der ersten Öffnung und eines oberen Teils (56) der zweiten Öffnung; und
    gleichzeitige Bildung eines unteren Teils (61) der ersten Öffnung und eines unteren Teils (60) der zweiten Öffnung;
    wobei der obere Teil der ersten Öffnung eine größere Breite als der untere Teil der ersten Öffnung aufweist und der obere Teil der zweiten Öffnung im Wesentlichen eine gleiche Breite wie der untere Teil der zweiten Öffnung aufweist.
  3. Verfahren nach Anspruch 1, wobei der Schritt Bildung der Isolierschicht umfasst:
    Bildung eines unteren Isolierschichtteils (38), der an das Halbleitersubstrat angrenzt;
    Bildung einer Ätzstoppschicht (40) auf dem unteren Isolierschichtteil; und
    Bildung eines oberen Isolierschichtteils (42) auf der Ätzstoppschicht.
  4. Verfahren nach Anspruch 1, wobei der Schritt Aufbringen der ersten leitenden Metallschicht in die erste Öffnung galvanisches Aufbringen von Kupfer umfasst.
  5. Verfahren nach Anspruch 1, wobei der Schritt selektives Aufbringen der ersten leitenden Metallschicht in die erste Öffnung umfasst:
    Aufbringen einer Sperrmetallschicht (52), um zumindest die erste Öffnung auszukleiden; und
    galvanisches Aufbringen von Kupfer, um die ausgekleidete erste Öffnung zu füllen.
  6. Verfahren nach Anspruch 5, wobei die Sperrmetallschicht Tantalnitrid umfasst.
  7. Verfahren nach Anspruch 1, wobei die unteren und oberen Metallelektroden Tantalnitrid umfassen.
  8. Verfahren nach Anspruch 1, wobei die Kondensator-Isolierschicht eine Dielektrizitätskonstante größer als 25 hat.
  9. Verfahren nach Anspruch 1, wobei die zweite leitende Schicht Kupfer umfasst.
  10. Verfahren nach Anspruch 1, das weiter den Schritt Bildung eines Kondensatorkontakts (66) in der Isolierschicht und elektrisches Verbinden der Metallleiterbahn der Kontaktstruktur und der unteren Metallelektrode des Kondensators umfasst.
EP00300072A 1999-01-12 2000-01-06 Verfahren zur Herstellung einer integrierten Schaltungsanordnung mit Doppeldamaszen-Kontaktstruktur und Metallelektroden-Kondensator Expired - Lifetime EP1020905B1 (de)

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US383806 1999-08-26

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VEREMEY V.; MITTRA R.: "A Technique for Fast Calculation of Capacitance Matrices of Interconnect Structures", IEEE TRANSACTIONS ON COMPONENTS, PACKAGING, AND MANUFACTURING TECHNOLOGY, vol. 21, no. 3, August 1998 (1998-08-01), pages 241 - 249, XP011002104 *

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US6346454B1 (en) 2002-02-12
JP2000208745A (ja) 2000-07-28
KR20000053453A (ko) 2000-08-25
TW455990B (en) 2001-09-21
EP1020905A1 (de) 2000-07-19
JP2010226132A (ja) 2010-10-07
JP4558876B2 (ja) 2010-10-06
JP5296010B2 (ja) 2013-09-25
DE60044990D1 (de) 2010-11-04
KR100721690B1 (ko) 2007-05-28

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