JP2010226132A - デュアル・ダマーシン相互接続構造および金属電極コンデンサを有する集積回路デバイスとその製造方法 - Google Patents
デュアル・ダマーシン相互接続構造および金属電極コンデンサを有する集積回路デバイスとその製造方法 Download PDFInfo
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Abstract
【解決手段】集積回路デバイスおよびその製造方法は、相互接続構造およびコンデンサを含む。相互接続構造は、金属線および接点を含み、コンデンサは上部および下部金属電極を含む。この方法は、半導体基板に隣接する誘電体層を形成することと、第一誘電体層において相互接続構造の第一開口部およびコンデンサの第二開口部を同時に形成することとを含む。この方法は、相互接続構造を形成するために、第一導電層を選択的にデポジットさせて、第一開口部を充填することと、第二開口部にコンデンサを形成するために、その間にコンデンサ誘電体を有する上部および下部金属電極を形成することとを含む。集積回路デバイスは、金属電極を有し、デュアル・ダマシーン構造にも使用でき、統合される高密度コンデンサを提供する。この様に、コンデンサは、デュアル・ダマシーン相互接続構造と同一レベルに位置される。
【選択図】図1
Description
本出願は、1999年1月12日付けの同時係属仮出願第60/115,703号に基づいている。
Claims (11)
- 金属線および接点を含む相互接続構造および上部および下部金属電極を含むコンデンサとを含む集積回路デバイスの製造方法であって、
半導体基板に隣接する誘電体層を形成するステップと、
前記誘電体層内に前記相互接続構造の第一開口部と、前記コンデンサの第二開口部とを同時に形成するステップと、
前記第一開口部を充填させ、前記相互接続構造を形成するために第一導電層を選択的に堆積させるステップと、
前記第二開口部に前記コンデンサを形成するために、前記上部および下部金属電極をその間にコンデンサ誘電体を入れた状態で形成するステップとを含む方法。 - 金属線および金属接点を含む相互接続構造および上部および下部金属電極を含むコンデンサとを含む集積回路デバイスを製造する方法であって、
半導体基板に隣接する誘電体層を形成するステップと、
前記誘電体層内に、前記相互接続構造用の第一開口部および前記コンデンサ用の第二開口部を同時に形成するステップと、
前記第二開口部上をマスキングするステップと、
前記第一開口部を充填するために、第一金属導電層を選択的にデポジットさせるステップと、
前記第二開口部からマスキングを除去するステップと、
少なくとも前記第二開口部の表面を整列させて、前記コンデンサの下部金属電極を形成するために下部金属層を堆積させるステップと、
前記コンデンサのコンデンサ誘電体を形成するために、前記下部金属層上にコンデンサ誘電体層を形成するステップと、
前記コンデンサの上部金属電極の一部を形成するために、前記コンデンサ誘電体層上に上部金属層を堆積させるステップと、
前記第二開口部の残りの部分を充填し、前記コンデンサの上部金属電極の一部を形成するために、第二導電層を堆積させるステップと、
前記集積回路デバイスの上部表面を平面化するステップとを含む方法。 - 請求項2に記載の方法において、前記第一開口部および第二開口部を同時に形成するステップが、
前記第一開口部の上部部分および前記第二開口部の上部部分を同時に形成することと、
前記第一開口部の下部部分および前記第二開口部の下部部分を同時に形成することと、
前記第一開口部の前記上部部分が、前記第一開口部の前記下部部分より幅が広く、前記第二開口部の前記上部部分が、前記第二開口部の前記下部部分とほぼ同じ幅であることとを含む方法。 - 請求項2に記載の方法において、前記誘電体層を形成するステップが、
前記半導体基板に隣接した下部誘電体層部分を形成することと、
前記下部誘電体層部分の上にエッチング・ストップ層を形成することと、
前記エッチング・ストップ層上に上部誘電体層部分を形成することとを含む方法。 - 請求項4に記載の方法において、前記第一開口部および第二開口部を同時に形成するステップが、
前記上部誘電体層部分および前記エッチング・ストップ層において前記第一開口部の上部部分および前記第二開口部の上部部分を同時に形成することと、
前記下部誘電体層において前記第一開口部の下部部分および前記第二開口部の下部部分を同時に形成することと、
前記第一開口部の前記上部部分が、前記第一開口部の前記下部部分より幅が広く、前記第二開口部の前記上部部分が前記第二開口部の前記下部部分とほぼ同じ幅であることとを含む方法。 - 請求項2に記載の方法において、前記第一開口部において導電層を選択的に堆積させるステップが、銅を電着させることを含む方法。
- 請求項2に記載の方法において、前記第一開口部において導電層を選択的に堆積させるステップが、
少なくとも前記第一開口部の表面を整列させるために、バリヤ金属層を堆積させることと、
前記整列させた第一開口部を充填させるために、銅を電着させることとを含む方法。 - 請求項7に記載の方法において、前記バリヤ金属層が窒化タンタルを含む方法。
- 請求項2に記載の方法において、前記上部および下部金属電極が窒化タンタルを含む方法。
- 請求項2に記載の方法において、前記第二導電層が銅を含む方法。
- 請求項2に記載の方法において、前記誘電体層内にコンデンサ接点を形成し、前記相互接続構造の金属線と、前記コンデンサの下部金属電極を電気的に接続するステップとをさらに含む方法。
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US11570399P | 1999-01-12 | 1999-01-12 | |
US60/115703 | 1999-01-12 | ||
US09/383806 | 1999-08-26 | ||
US09/383,806 US6346454B1 (en) | 1999-01-12 | 1999-08-26 | Method of making dual damascene interconnect structure and metal electrode capacitor |
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JP2000006225A Division JP4558876B2 (ja) | 1999-01-12 | 2000-01-12 | デュアル・ダマーシン相互接続構造および金属電極コンデンサを有する集積回路デバイスとその製造方法 |
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JP2010226132A true JP2010226132A (ja) | 2010-10-07 |
JP5296010B2 JP5296010B2 (ja) | 2013-09-25 |
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JP2010125463A Expired - Fee Related JP5296010B2 (ja) | 1999-01-12 | 2010-06-01 | デュアル・ダマーシン相互接続構造および金属電極コンデンサを有する集積回路デバイスとその製造方法 |
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US (1) | US6346454B1 (ja) |
EP (1) | EP1020905B1 (ja) |
JP (2) | JP4558876B2 (ja) |
KR (1) | KR100721690B1 (ja) |
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KR100313506B1 (ko) * | 1999-03-16 | 2001-11-07 | 김영환 | 고유전막을 이용한 반도체 소자의 커패시터 및 그 제조방법 |
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KR100326253B1 (ko) * | 1999-12-28 | 2002-03-08 | 박종섭 | 반도체 소자의 캐패시터 형성방법 |
US6384468B1 (en) * | 2000-02-07 | 2002-05-07 | International Business Machines Corporation | Capacitor and method for forming same |
US6452251B1 (en) * | 2000-03-31 | 2002-09-17 | International Business Machines Corporation | Damascene metal capacitor |
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GB2368721A (en) * | 2000-06-16 | 2002-05-08 | Agere Syst Guardian Corp | Integrated circuit with damascene structure and capacitor |
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JP2002009248A (ja) * | 2000-06-26 | 2002-01-11 | Oki Electric Ind Co Ltd | キャパシタおよびその製造方法 |
US6329234B1 (en) * | 2000-07-24 | 2001-12-11 | Taiwan Semiconductor Manufactuirng Company | Copper process compatible CMOS metal-insulator-metal capacitor structure and its process flow |
TW451449B (en) * | 2000-08-17 | 2001-08-21 | United Microelectronics Corp | Manufacturing method of dual damascene structure |
FR2813145B1 (fr) | 2000-08-18 | 2002-11-29 | St Microelectronics Sa | Procede de fabrication d'un condensateur au sein d'un circuit integre, et circuit integre correspondant |
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JP2000208745A (ja) | 2000-07-28 |
KR100721690B1 (ko) | 2007-05-28 |
JP4558876B2 (ja) | 2010-10-06 |
TW455990B (en) | 2001-09-21 |
EP1020905B1 (en) | 2010-09-22 |
US6346454B1 (en) | 2002-02-12 |
JP5296010B2 (ja) | 2013-09-25 |
EP1020905A1 (en) | 2000-07-19 |
KR20000053453A (ko) | 2000-08-25 |
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