JPS6441262A - Memory cell - Google Patents

Memory cell

Info

Publication number
JPS6441262A
JPS6441262A JP62196185A JP19618587A JPS6441262A JP S6441262 A JPS6441262 A JP S6441262A JP 62196185 A JP62196185 A JP 62196185A JP 19618587 A JP19618587 A JP 19618587A JP S6441262 A JPS6441262 A JP S6441262A
Authority
JP
Japan
Prior art keywords
groove
interlayer insulating
mos transistor
diffusion layer
insulating film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62196185A
Other languages
Japanese (ja)
Inventor
Yuzuru Oji
Katsuhiro Shimohigashi
Kiichiro Mukai
Tokuo Kure
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP62196185A priority Critical patent/JPS6441262A/en
Publication of JPS6441262A publication Critical patent/JPS6441262A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B12/00Dynamic random access memory [DRAM] devices
    • H10B12/30DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor

Abstract

PURPOSE:To increase capacitance, by forming a capacitor on the wall of a groove dug so as to reach a diffusion layer, said groove being formed in a comparatively thick interlayer insulating film formed so as to cover a MOS transistor in a memory cell. CONSTITUTION:In a comparatively thick interlayer insulating film 103 formed so as to cover a MOS transistor 100, a groove 201 is formed so as to reach the diffusion layer 110 (drain or source) of a MOS transistor 100. On the inner wall of the groove 201, a capacitor 200 composed of upper and lower electrodes 200, 210 of, e.g., polycrystalline silicon and a thin dielectric film 203 is formed. The lower electrode 210 is connected to the diffusion layer 120. By increasing adequately the thickness of the interlayer insulating film 103, a sufficient electrostatic capacitance can be obtained even if a cell area is made small.
JP62196185A 1987-08-07 1987-08-07 Memory cell Pending JPS6441262A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62196185A JPS6441262A (en) 1987-08-07 1987-08-07 Memory cell

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62196185A JPS6441262A (en) 1987-08-07 1987-08-07 Memory cell

Publications (1)

Publication Number Publication Date
JPS6441262A true JPS6441262A (en) 1989-02-13

Family

ID=16353607

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62196185A Pending JPS6441262A (en) 1987-08-07 1987-08-07 Memory cell

Country Status (1)

Country Link
JP (1) JPS6441262A (en)

Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01262658A (en) * 1988-04-13 1989-10-19 Nec Corp Dynamic random access memory device
JPH02254751A (en) * 1989-03-29 1990-10-15 Fujitsu Ltd Semiconductor memory cell
JPH03116965A (en) * 1989-09-29 1991-05-17 Mitsubishi Electric Corp Memory cell structure
JPH05243517A (en) * 1992-02-25 1993-09-21 Nec Corp Semiconductor device
US5248628A (en) * 1989-09-08 1993-09-28 Kabushiki Kaisha Toshiba Method of fabricating a semiconductor memory device
JPH07202019A (en) * 1993-12-28 1995-08-04 Nec Corp Semiconductor integrated circuit device and its manufacture
JPH0846152A (en) * 1994-07-29 1996-02-16 Nec Corp Semiconductor memory and manufacture
WO1996026544A1 (en) * 1995-02-22 1996-08-29 Micron Technology, Inc. Method of forming a dram bit line contact
US5686747A (en) * 1993-02-12 1997-11-11 Micron Technology, Inc. Integrated circuits comprising interconnecting plugs
US5705838A (en) * 1993-02-12 1998-01-06 Micron Technology, Inc. Array of bit line over capacitor array of memory cells
JP2000208745A (en) * 1999-01-12 2000-07-28 Lucent Technol Inc Dual damascene mutual connection structure, integrated circuit device having metal electrode capacitor, and its manufacture
US6653230B2 (en) 1999-02-10 2003-11-25 Nec Corporation Semiconductor device having concave electrode and convex electrode and method of manufacturing thereof
JP2004533106A (en) * 2000-10-05 2004-10-28 モトローラ・インコーポレイテッド Semiconductor component manufacturing method and semiconductor component
CN105529329A (en) * 2014-09-29 2016-04-27 中芯国际集成电路制造(上海)有限公司 Embedded DRAM device and formation method thereof

Cited By (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01262658A (en) * 1988-04-13 1989-10-19 Nec Corp Dynamic random access memory device
JPH02254751A (en) * 1989-03-29 1990-10-15 Fujitsu Ltd Semiconductor memory cell
US5248628A (en) * 1989-09-08 1993-09-28 Kabushiki Kaisha Toshiba Method of fabricating a semiconductor memory device
JPH03116965A (en) * 1989-09-29 1991-05-17 Mitsubishi Electric Corp Memory cell structure
JPH05243517A (en) * 1992-02-25 1993-09-21 Nec Corp Semiconductor device
US5686747A (en) * 1993-02-12 1997-11-11 Micron Technology, Inc. Integrated circuits comprising interconnecting plugs
US5705838A (en) * 1993-02-12 1998-01-06 Micron Technology, Inc. Array of bit line over capacitor array of memory cells
US5821140A (en) * 1993-02-12 1998-10-13 Micron Technology, Inc. Method of forming a bit line over capacitor array of memory cells and an array of bit line over capacitor array of memory cells
US5900660A (en) * 1993-02-12 1999-05-04 Micron Technology, Inc. Method of forming a bit line over capacitor array of memory cells and an array of bit line over capacitor array of memory calls
US6110774A (en) * 1993-02-12 2000-08-29 Micron Technology, Inc. Method of forming a bit line over capacitor array of memory cells and an array of bit line over capacitor array of memory cells
JPH07202019A (en) * 1993-12-28 1995-08-04 Nec Corp Semiconductor integrated circuit device and its manufacture
JPH0846152A (en) * 1994-07-29 1996-02-16 Nec Corp Semiconductor memory and manufacture
WO1996026544A1 (en) * 1995-02-22 1996-08-29 Micron Technology, Inc. Method of forming a dram bit line contact
JP2000208745A (en) * 1999-01-12 2000-07-28 Lucent Technol Inc Dual damascene mutual connection structure, integrated circuit device having metal electrode capacitor, and its manufacture
US6653230B2 (en) 1999-02-10 2003-11-25 Nec Corporation Semiconductor device having concave electrode and convex electrode and method of manufacturing thereof
JP2004533106A (en) * 2000-10-05 2004-10-28 モトローラ・インコーポレイテッド Semiconductor component manufacturing method and semiconductor component
CN105529329A (en) * 2014-09-29 2016-04-27 中芯国际集成电路制造(上海)有限公司 Embedded DRAM device and formation method thereof

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