DE69915158D1 - Halbleiterspeicheranordnung - Google Patents

Halbleiterspeicheranordnung

Info

Publication number
DE69915158D1
DE69915158D1 DE69915158T DE69915158T DE69915158D1 DE 69915158 D1 DE69915158 D1 DE 69915158D1 DE 69915158 T DE69915158 T DE 69915158T DE 69915158 T DE69915158 T DE 69915158T DE 69915158 D1 DE69915158 D1 DE 69915158D1
Authority
DE
Germany
Prior art keywords
memory device
semiconductor memory
semiconductor
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69915158T
Other languages
English (en)
Other versions
DE69915158T2 (de
Inventor
Tomoko Nobutoki
Kouji Mine
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Micron Memory Japan Ltd
Original Assignee
NEC Electronics Corp
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Electronics Corp, NEC Corp filed Critical NEC Electronics Corp
Application granted granted Critical
Publication of DE69915158D1 publication Critical patent/DE69915158D1/de
Publication of DE69915158T2 publication Critical patent/DE69915158T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/10—Decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/025—Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
  • Static Random-Access Memory (AREA)
  • Semiconductor Memories (AREA)
DE69915158T 1998-04-23 1999-04-22 Halbleiterspeicheranordnung Expired - Lifetime DE69915158T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP11374398 1998-04-23
JP10113743A JPH11306763A (ja) 1998-04-23 1998-04-23 半導体記憶装置

Publications (2)

Publication Number Publication Date
DE69915158D1 true DE69915158D1 (de) 2004-04-08
DE69915158T2 DE69915158T2 (de) 2005-04-07

Family

ID=14620009

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69915158T Expired - Lifetime DE69915158T2 (de) 1998-04-23 1999-04-22 Halbleiterspeicheranordnung

Country Status (7)

Country Link
US (1) US6181631B1 (de)
EP (1) EP0952586B1 (de)
JP (1) JPH11306763A (de)
KR (1) KR100314109B1 (de)
CN (1) CN100392761C (de)
DE (1) DE69915158T2 (de)
TW (1) TW421800B (de)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10102350B4 (de) * 2001-01-19 2004-09-23 Infineon Technologies Ag Integrierter Speicher mit mehreren Speicherzellenfeldern sowie Verfahren zum Betrieb des integrierten Speichers
KR100400311B1 (ko) 2001-06-29 2003-10-01 주식회사 하이닉스반도체 반도체 메모리 소자의 신호 지연 제어 장치
JP2013021528A (ja) * 2011-07-12 2013-01-31 Elpida Memory Inc 半導体装置、及び出力バッファのインピーダンスを調整する方法
KR20140113117A (ko) * 2013-03-15 2014-09-24 삼성전자주식회사 비대칭 액세스 타임을 가진 반도체 메모리 장치
JP6896597B2 (ja) * 2017-12-20 2021-06-30 ルネサスエレクトロニクス株式会社 半導体記憶装置
CN112397133B (zh) * 2020-12-11 2023-05-30 西安紫光国芯半导体有限公司 存储器、阵列单元模块及其存储方法、构建方法

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4425633A (en) * 1980-10-06 1984-01-10 Mostek Corporation Variable delay circuit for emulating word line delay
JPH01166398A (ja) * 1987-12-23 1989-06-30 Hitachi Ltd 半導体記憶装置
KR900015148A (ko) * 1989-03-09 1990-10-26 미다 가쓰시게 반도체장치
JPH03176892A (ja) * 1989-12-04 1991-07-31 Hitachi Ltd 半導体集積回路装置
US5150330A (en) * 1990-01-24 1992-09-22 Vlsi Technology, Inc. Interblock dispersed-word memory architecture
JP2519593B2 (ja) * 1990-10-24 1996-07-31 三菱電機株式会社 半導体記憶装置
JPH06325575A (ja) * 1993-05-12 1994-11-25 Hitachi Ltd 半導体集積回路装置
JP3279787B2 (ja) * 1993-12-07 2002-04-30 株式会社日立製作所 半導体記憶装置
JPH07211075A (ja) * 1994-01-24 1995-08-11 Hitachi Ltd 半導体集積回路装置
JP2647023B2 (ja) * 1994-10-27 1997-08-27 日本電気株式会社 半導体記憶装置
JPH08195083A (ja) * 1995-01-17 1996-07-30 Toshiba Microelectron Corp 半導体記憶装置
JPH08263985A (ja) * 1995-03-24 1996-10-11 Nec Corp 半導体記憶装置
JPH1050958A (ja) * 1996-08-05 1998-02-20 Toshiba Corp 半導体記憶装置、半導体記憶装置のレイアウト方法、半導体記憶装置の動作方法および半導体記憶装置の回路配置パターン

Also Published As

Publication number Publication date
KR100314109B1 (ko) 2001-11-17
DE69915158T2 (de) 2005-04-07
EP0952586A3 (de) 2000-07-26
US6181631B1 (en) 2001-01-30
CN1233057A (zh) 1999-10-27
KR19990083405A (ko) 1999-11-25
EP0952586B1 (de) 2004-03-03
TW421800B (en) 2001-02-11
EP0952586A2 (de) 1999-10-27
JPH11306763A (ja) 1999-11-05
CN100392761C (zh) 2008-06-04

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Legal Events

Date Code Title Description
8332 No legal effect for de
8370 Indication related to discontinuation of the patent is to be deleted
8327 Change in the person/name/address of the patent owner

Owner name: ELPIDA MEMORY, INC., TOKIO/TOKYO, JP

8364 No opposition during term of opposition