DE69902712T2 - Halbleiterspeicheranordnung - Google Patents

Halbleiterspeicheranordnung

Info

Publication number
DE69902712T2
DE69902712T2 DE69902712T DE69902712T DE69902712T2 DE 69902712 T2 DE69902712 T2 DE 69902712T2 DE 69902712 T DE69902712 T DE 69902712T DE 69902712 T DE69902712 T DE 69902712T DE 69902712 T2 DE69902712 T2 DE 69902712T2
Authority
DE
Germany
Prior art keywords
memory device
semiconductor memory
semiconductor
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69902712T
Other languages
English (en)
Other versions
DE69902712D1 (de
Inventor
Yoshihiro Takaishi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Electronics Corp
Original Assignee
NEC Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Electronics Corp filed Critical NEC Electronics Corp
Application granted granted Critical
Publication of DE69902712D1 publication Critical patent/DE69902712D1/de
Publication of DE69902712T2 publication Critical patent/DE69902712T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Memories (AREA)
DE69902712T 1998-04-09 1999-04-09 Halbleiterspeicheranordnung Expired - Fee Related DE69902712T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10097801A JP3137185B2 (ja) 1998-04-09 1998-04-09 半導体記憶装置

Publications (2)

Publication Number Publication Date
DE69902712D1 DE69902712D1 (de) 2002-10-10
DE69902712T2 true DE69902712T2 (de) 2003-08-07

Family

ID=14201895

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69902712T Expired - Fee Related DE69902712T2 (de) 1998-04-09 1999-04-09 Halbleiterspeicheranordnung

Country Status (6)

Country Link
US (1) US6185120B1 (de)
EP (1) EP0949681B1 (de)
JP (1) JP3137185B2 (de)
KR (1) KR100332012B1 (de)
CN (1) CN1126176C (de)
DE (1) DE69902712T2 (de)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4063450B2 (ja) * 1999-06-14 2008-03-19 エルピーダメモリ株式会社 半導体集積回路装置
US6522579B2 (en) * 2001-01-24 2003-02-18 Infineon Technologies, Ag Non-orthogonal MRAM device
US6549476B2 (en) * 2001-04-09 2003-04-15 Micron Technology, Inc. Device and method for using complementary bits in a memory array
KR100401513B1 (ko) * 2001-06-29 2003-10-17 주식회사 하이닉스반도체 반도체 소자의 배선 형성방법
KR100891249B1 (ko) * 2002-05-31 2009-04-01 주식회사 하이닉스반도체 6ｆ2 ｄｒａｍ 셀을 구비한 반도체 메모리 소자
KR100574981B1 (ko) 2004-05-31 2006-05-02 삼성전자주식회사 트랜지스터의 리세스 채널을 위한 트렌치를 형성하는 방법및 이를 위한 레이아웃
KR100720251B1 (ko) 2005-12-30 2007-05-22 주식회사 하이닉스반도체 노광 마스크 및 이를 이용한 반도체 소자의 제조방법
JP5694625B2 (ja) * 2006-04-13 2015-04-01 ピーエスフォー ルクスコ エスエイアールエルＰＳ４ Ｌｕｘｃｏ Ｓ．ａ．ｒ．ｌ． 半導体記憶装置
JP2010161173A (ja) * 2009-01-07 2010-07-22 Renesas Electronics Corp 半導体記憶装置
KR101102764B1 (ko) * 2009-07-31 2012-01-03 주식회사 하이닉스반도체 반도체 소자의 레이아웃 및 반도체 소자의 형성방법
CN109427787A (zh) * 2017-08-30 2019-03-05 联华电子股份有限公司 半导体存储装置
US10818729B2 (en) * 2018-05-17 2020-10-27 Macronix International Co., Ltd. Bit cost scalable 3D phase change cross-point memory
CN112366203B (zh) * 2020-10-23 2023-01-03 福建省晋华集成电路有限公司 图案布局以及其形成方法

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5194752A (en) * 1989-05-23 1993-03-16 Kabushiki Kaisha Toshiba Semiconductor memory device
JPH07120714B2 (ja) 1989-05-23 1995-12-20 株式会社東芝 半導体記憶装置
JP2974252B2 (ja) * 1989-08-19 1999-11-10 富士通株式会社 半導体記憶装置
JP3013458B2 (ja) 1990-02-26 2000-02-28 日本電気株式会社 半導体記憶装置
DE69025926T2 (de) 1990-07-06 1996-07-25 Fujitsu Ltd Dynamischer Speicher mit wahlfreiem Zugriff mit verbessertem Layout und Methode zur Anordnung des Speicherzellenmusters
JP3344485B2 (ja) 1990-11-09 2002-11-11 富士通株式会社 半導体装置の製造方法
JP2825031B2 (ja) 1991-08-06 1998-11-18 日本電気株式会社 半導体メモリ装置
JP3179638B2 (ja) 1993-10-25 2001-06-25 日本電信電話株式会社 光学素子の形成方法
JPH0878640A (ja) 1994-08-31 1996-03-22 Nippon Steel Corp 半導体記憶装置及びその製造方法
JP3520144B2 (ja) 1995-10-26 2004-04-19 株式会社ルネサステクノロジ 半導体記憶装置およびその製造方法
JP2950265B2 (ja) * 1996-07-30 1999-09-20 日本電気株式会社 半導体記憶装置
US6060351A (en) * 1997-12-24 2000-05-09 Micron Technology, Inc. Process for forming capacitor over bit line memory cell

Also Published As

Publication number Publication date
EP0949681A1 (de) 1999-10-13
JP3137185B2 (ja) 2001-02-19
KR19990083078A (ko) 1999-11-25
US6185120B1 (en) 2001-02-06
CN1231514A (zh) 1999-10-13
CN1126176C (zh) 2003-10-29
KR100332012B1 (ko) 2002-04-10
DE69902712D1 (de) 2002-10-10
EP0949681B1 (de) 2002-09-04
JPH11297954A (ja) 1999-10-29

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Legal Events

Date Code Title Description
8327 Change in the person/name/address of the patent owner

Owner name: NEC ELECTRONICS CORP., KAWASAKI, KANAGAWA, JP

8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee