DE69829618D1 - Platzeffizienter Halbleiterspeicher mit hierarchischer Spaltenauswahlleitungsarchitektur - Google Patents

Platzeffizienter Halbleiterspeicher mit hierarchischer Spaltenauswahlleitungsarchitektur

Info

Publication number
DE69829618D1
DE69829618D1 DE69829618T DE69829618T DE69829618D1 DE 69829618 D1 DE69829618 D1 DE 69829618D1 DE 69829618 T DE69829618 T DE 69829618T DE 69829618 T DE69829618 T DE 69829618T DE 69829618 D1 DE69829618 D1 DE 69829618D1
Authority
DE
Germany
Prior art keywords
space
semiconductor memory
selection line
column selection
line architecture
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69829618T
Other languages
English (en)
Other versions
DE69829618T2 (de
Inventor
Gerhard Mueller
Heinz Hoenigschmid
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Qimonda AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Publication of DE69829618D1 publication Critical patent/DE69829618D1/de
Application granted granted Critical
Publication of DE69829618T2 publication Critical patent/DE69829618T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/10—Decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G11C11/4087—Address decoders, e.g. bit - or word line decoders; Multiple line decoders

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
  • Semiconductor Memories (AREA)
  • Static Random-Access Memory (AREA)
DE69829618T 1997-09-29 1998-07-30 Platzeffizienter Halbleiterspeicher mit hierarchischer Spaltenauswahlleitungsarchitektur Expired - Lifetime DE69829618T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/940,861 US5923605A (en) 1997-09-29 1997-09-29 Space-efficient semiconductor memory having hierarchical column select line architecture
US940861 1997-09-29

Publications (2)

Publication Number Publication Date
DE69829618D1 true DE69829618D1 (de) 2005-05-12
DE69829618T2 DE69829618T2 (de) 2006-04-27

Family

ID=25475548

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69829618T Expired - Lifetime DE69829618T2 (de) 1997-09-29 1998-07-30 Platzeffizienter Halbleiterspeicher mit hierarchischer Spaltenauswahlleitungsarchitektur

Country Status (7)

Country Link
US (1) US5923605A (de)
EP (1) EP0905705B1 (de)
JP (1) JPH11185468A (de)
KR (1) KR100574242B1 (de)
CN (1) CN1174428C (de)
DE (1) DE69829618T2 (de)
TW (1) TW411478B (de)

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US6137746A (en) * 1999-07-28 2000-10-24 Alliance Semiconductor Corporation High performance random access memory with multiple local I/O lines
GB2363231B (en) * 1999-09-24 2002-05-08 Clearspeed Technology Ltd Memory devices
KR100352766B1 (ko) * 2000-03-07 2002-09-16 삼성전자 주식회사 반도체 메모리 디바이스에서 컬럼 경로 레이아웃 구조 및방법
US6327215B1 (en) 2000-09-28 2001-12-04 Vanguard International Semiconductor Corporation Local bit switch decode circuit and method
JP3937752B2 (ja) 2001-05-10 2007-06-27 株式会社日立製作所 携帯電話機および基地局
US20030206479A1 (en) * 2001-06-21 2003-11-06 Chun Shiah High area efficient data line architecture
US6606275B2 (en) * 2001-08-23 2003-08-12 Jeng-Jye Shau High performance semiconductor memory devices
KR100403348B1 (ko) * 2001-10-08 2003-11-01 주식회사 하이닉스반도체 계층적 구조를 갖는 비트라인 선택 회로
US6768692B2 (en) * 2002-07-29 2004-07-27 International Business Machines Corporation Multiple subarray DRAM having a single shared sense amplifier
KR20040017468A (ko) * 2002-08-21 2004-02-27 엘지전자 주식회사 듀얼 시간 표시 기능을 갖는 휴대폰 및 듀얼 시간 표시설정방법
US7054178B1 (en) * 2002-09-06 2006-05-30 Etron Technology, Inc. Datapath architecture for high area efficiency
JP2004326974A (ja) * 2003-04-25 2004-11-18 Toshiba Corp 半導体集積回路装置及びｉｃカード
JP4989847B2 (ja) * 2003-12-12 2012-08-01 株式会社半導体エネルギー研究所 半導体装置
CN1661721B (zh) * 2004-02-26 2010-09-15 钰创科技股份有限公司 高阶区域效能的资料线路结构
US7082075B2 (en) 2004-03-18 2006-07-25 Micron Technology, Inc. Memory device and method having banks of different sizes
JP4470159B2 (ja) * 2004-06-03 2010-06-02 エルピーダメモリ株式会社 ペアトランジスタの配列を高密度とする半導体記憶装置
KR100630694B1 (ko) * 2004-08-03 2006-10-02 삼성전자주식회사 전류 모드 시그널링 방식의 싱글 비트 버스 구조를 갖는메모리 장치
JP2006134469A (ja) * 2004-11-05 2006-05-25 Elpida Memory Inc 半導体記憶装置
US7516264B2 (en) * 2005-02-09 2009-04-07 International Business Machines Corporation Programmable bank/timer address folding in memory devices
US7893813B2 (en) * 2005-07-28 2011-02-22 Intermec Ip Corp. Automatic data collection device, method and article
US7310257B2 (en) * 2005-11-10 2007-12-18 Micron Technology, Inc. Local digit line architecture and method for memory devices having multi-bit or low capacitance memory cells
DE102007012902B3 (de) * 2007-03-19 2008-07-10 Qimonda Ag Kopplungsoptimierte Anschlusskonfiguration von Signalleitungen und Verstärkern
JP5339541B2 (ja) 2007-05-25 2013-11-13 マーベル ワールド トレード リミテッド ビット線デコーダ及び集積回路
KR100878313B1 (ko) * 2007-06-11 2009-01-14 주식회사 하이닉스반도체 데이터 입출력 라인 제어 회로 및 이를 포함하는 반도체집적 회로
US20090013148A1 (en) * 2007-07-03 2009-01-08 Micron Technology, Inc. Block addressing for parallel memory arrays
KR20090029140A (ko) * 2007-09-17 2009-03-20 삼성전자주식회사 휴대 방송 서비스에서 표준 시각 제공 방법 및 시스템
US8159898B2 (en) * 2008-01-18 2012-04-17 Hynix Semiconductor Inc. Architecture of highly integrated semiconductor memory device
KR101476773B1 (ko) 2008-04-08 2014-12-29 삼성전자주식회사 가변 저항 메모리 장치를 포함하는 반도체 메모리 장치 및메모리 시스템
US8194492B2 (en) 2008-04-08 2012-06-05 Samsung Electronics Co., Ltd. Variable resistance memory device and system
KR20090117189A (ko) * 2008-05-09 2009-11-12 삼성전자주식회사 멀티 라이트를 위한 효율적인 코아 구조를 갖는 반도체메모리 장치
US7692975B2 (en) * 2008-05-09 2010-04-06 Micron Technology, Inc. System and method for mitigating reverse bias leakage
US7907468B2 (en) * 2008-05-28 2011-03-15 Micron Technology, Inc. Memory device having data paths permitting array/port consolidation and swapping
US8482981B2 (en) * 2008-05-30 2013-07-09 Qimonda Ag Method of forming an integrated circuit with NAND flash array segments and intra array multiplexers and corresponding integrated circuit with NAND flash array segments and intra array multiplexers
CN101452740B (zh) * 2008-12-26 2013-11-06 复旦大学 一种用于同时选中多条位线的列译码器
US9116781B2 (en) * 2011-10-17 2015-08-25 Rambus Inc. Memory controller and memory device command protocol
US8693236B2 (en) 2011-12-09 2014-04-08 Gsi Technology, Inc. Systems and methods of sectioned bit line memory arrays, including hierarchical and/or other features
US8593860B2 (en) 2011-12-09 2013-11-26 Gsi Technology, Inc. Systems and methods of sectioned bit line memory arrays
KR102193444B1 (ko) 2014-04-28 2020-12-21 삼성전자주식회사 반도체 메모리 장치 및 이를 포함하는 메모리 시스템
US9275686B2 (en) 2014-05-28 2016-03-01 Avago Technologies General Ip (Singapore) Pte. Ltd. Memory banks with shared input/output circuitry
US11443795B2 (en) * 2017-07-12 2022-09-13 Ambiq Micro, Inc. SRAM with address dependent power usage
CN114155896B (zh) * 2020-09-04 2024-03-29 长鑫存储技术有限公司 半导体装置

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KR0142962B1 (ko) * 1995-05-12 1998-08-17 김광호 계급적 컬럼선택라인구조를 가지는 반도체 메모리 장치
KR100350700B1 (ko) * 1995-12-27 2003-01-24 삼성전자 주식회사 반도체 메모리장치
KR100211760B1 (ko) * 1995-12-28 1999-08-02 윤종용 멀티뱅크 구조를 갖는 반도체 메모리 장치의 데이타 입출력 경로 제어회로
US5822268A (en) * 1997-09-11 1998-10-13 International Business Machines Corporation Hierarchical column select line architecture for multi-bank DRAMs

Also Published As

Publication number Publication date
US5923605A (en) 1999-07-13
TW411478B (en) 2000-11-11
KR100574242B1 (ko) 2006-07-21
CN1215893A (zh) 1999-05-05
EP0905705A2 (de) 1999-03-31
DE69829618T2 (de) 2006-04-27
CN1174428C (zh) 2004-11-03
EP0905705A3 (de) 1999-07-28
JPH11185468A (ja) 1999-07-09
EP0905705B1 (de) 2005-04-06
KR19990029329A (ko) 1999-04-26

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Legal Events

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8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: QIMONDA AG, 81739 MUENCHEN, DE