DE69518793D1 - Herstellungsverfahren für eine Halbleitervorrichtung - Google Patents

Herstellungsverfahren für eine Halbleitervorrichtung

Info

Publication number
DE69518793D1
DE69518793D1 DE69518793T DE69518793T DE69518793D1 DE 69518793 D1 DE69518793 D1 DE 69518793D1 DE 69518793 T DE69518793 T DE 69518793T DE 69518793 T DE69518793 T DE 69518793T DE 69518793 D1 DE69518793 D1 DE 69518793D1
Authority
DE
Germany
Prior art keywords
manufacturing
semiconductor device
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69518793T
Other languages
English (en)
Other versions
DE69518793T2 (de
Inventor
Masahiro Konishi
Masako Yabe
Toshiro Hida
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Application granted granted Critical
Publication of DE69518793D1 publication Critical patent/DE69518793D1/de
Publication of DE69518793T2 publication Critical patent/DE69518793T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/52—Encapsulations
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B3/00—Simple or compound lenses
    • G02B3/0006—Arrays
    • G02B3/0037—Arrays characterized by the distribution or form of lenses
    • G02B3/005—Arrays characterized by the distribution or form of lenses arranged along a single direction only, e.g. lenticular sheets
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B3/00—Simple or compound lenses
    • G02B3/0006—Arrays
    • G02B3/0037—Arrays characterized by the distribution or form of lenses
    • G02B3/0056—Arrays characterized by the distribution or form of lenses arranged along two different directions in a plane, e.g. honeycomb arrangement of lenses
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
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    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
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    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
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    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
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    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
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    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
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    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
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    • H01L2924/181—Encapsulation
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    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/483—Containers
    • H01L33/486—Containers adapted for surface mounting

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Optics & Photonics (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Led Device Packages (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Compositions Of Macromolecular Compounds (AREA)
  • Non-Metallic Protective Coatings For Printed Circuits (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
DE69518793T 1994-05-24 1995-05-24 Herstellungsverfahren für eine Halbleitervorrichtung Expired - Lifetime DE69518793T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP10982894 1994-05-24
JP6310352A JP2994219B2 (ja) 1994-05-24 1994-12-14 半導体デバイスの製造方法

Publications (2)

Publication Number Publication Date
DE69518793D1 true DE69518793D1 (de) 2000-10-19
DE69518793T2 DE69518793T2 (de) 2001-02-08

Family

ID=26449542

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69518793T Expired - Lifetime DE69518793T2 (de) 1994-05-24 1995-05-24 Herstellungsverfahren für eine Halbleitervorrichtung

Country Status (7)

Country Link
US (1) US5635115A (de)
EP (1) EP0684648B1 (de)
JP (1) JP2994219B2 (de)
KR (1) KR0180931B1 (de)
CN (1) CN1100347C (de)
DE (1) DE69518793T2 (de)
MY (1) MY114173A (de)

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US5851449A (en) * 1995-09-27 1998-12-22 Kabushiki Kaisha Toshiba Method for manufacturing a surface-mounted type optical semiconductor device
US6274890B1 (en) 1997-01-15 2001-08-14 Kabushiki Kaisha Toshiba Semiconductor light emitting device and its manufacturing method
WO1998041071A1 (en) * 1997-03-11 1998-09-17 Xemod, Inc. Hybrid module assembling method and apparatus
JP3391282B2 (ja) * 1998-07-02 2003-03-31 株式会社村田製作所 電子部品の製造方法
JP2001168400A (ja) * 1999-12-09 2001-06-22 Rohm Co Ltd ケース付チップ型発光装置およびその製造方法
US6856006B2 (en) * 2002-03-28 2005-02-15 Siliconix Taiwan Ltd Encapsulation method and leadframe for leadless semiconductor packages
KR20020079087A (ko) * 2001-04-13 2002-10-19 주식회사한영전자 표시등의 발광다이오드 보호 구조
CN1980948B (zh) * 2002-11-27 2011-08-10 Dmi生物科学公司 治疗由增强磷酸化介导的疾病和病况
CA2523544A1 (en) 2003-04-30 2004-11-18 Cree, Inc. High powered light emitter packages with compact optics
TWI263403B (en) * 2004-01-22 2006-10-01 Murata Manufacturing Co Electronic component manufacturing method
JP2005259847A (ja) * 2004-03-10 2005-09-22 Nitto Denko Corp 光半導体装置の製造方法
JP2005294733A (ja) 2004-04-05 2005-10-20 Nitto Denko Corp 光半導体素子封止用シートおよび該シートを用いた光半導体装置の製造方法
JP5004410B2 (ja) * 2004-04-26 2012-08-22 Ｔｏｗａ株式会社 光素子の樹脂封止成形方法および樹脂封止成形装置
DE102004021927B4 (de) * 2004-05-04 2008-07-03 Semikron Elektronik Gmbh & Co. Kg Verfahren zur inneren elektrischen Isolation eines Substrats für ein Leistungshalbleitermodul
JP4793263B2 (ja) * 2004-06-18 2011-10-12 東レ株式会社 直下型バックライト
US7534633B2 (en) 2004-07-02 2009-05-19 Cree, Inc. LED with substrate modifications for enhanced light extraction and method of making same
JP4031784B2 (ja) * 2004-07-28 2008-01-09 シャープ株式会社 発光モジュールおよびその製造方法
JP5128047B2 (ja) * 2004-10-07 2013-01-23 Ｔｏｗａ株式会社 光デバイス及び光デバイスの生産方法
JP4627177B2 (ja) * 2004-11-10 2011-02-09 スタンレー電気株式会社 Ｌｅｄの製造方法
JP2006140362A (ja) * 2004-11-15 2006-06-01 Nitto Denko Corp 光半導体素子封止用シートおよび該シートを用いた光半導体装置の製造方法
JP2007079526A (ja) * 2004-11-26 2007-03-29 Hasegawa Kagaku Kogyo Kk Ｉｃタグ及びその製造方法
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