DE69500007D1 - Speicherredundanzschaltung - Google Patents

Speicherredundanzschaltung

Info

Publication number
DE69500007D1
DE69500007D1 DE69500007T DE69500007T DE69500007D1 DE 69500007 D1 DE69500007 D1 DE 69500007D1 DE 69500007 T DE69500007 T DE 69500007T DE 69500007 T DE69500007 T DE 69500007T DE 69500007 D1 DE69500007 D1 DE 69500007D1
Authority
DE
Germany
Prior art keywords
memory
addresses
principal
inhibiting
cam
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69500007T
Other languages
English (en)
Other versions
DE69500007T2 (de
Inventor
Jean Devin
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SA
Original Assignee
SGS Thomson Microelectronics SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SGS Thomson Microelectronics SA filed Critical SGS Thomson Microelectronics SA
Application granted granted Critical
Publication of DE69500007D1 publication Critical patent/DE69500007D1/de
Publication of DE69500007T2 publication Critical patent/DE69500007T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/84—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved access time or stability
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G11C29/24—Accessing extra cells, e.g. dummy cells or redundant cells
DE69500007T 1994-02-28 1995-02-27 Speicherredundanzschaltung Expired - Fee Related DE69500007T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR9402282A FR2716743B1 (fr) 1994-02-28 1994-02-28 Circuit de redondance de mémoire.

Publications (2)

Publication Number Publication Date
DE69500007D1 true DE69500007D1 (de) 1996-07-25
DE69500007T2 DE69500007T2 (de) 1996-12-12

Family

ID=9460504

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69500007T Expired - Fee Related DE69500007T2 (de) 1994-02-28 1995-02-27 Speicherredundanzschaltung

Country Status (5)

Country Link
US (1) US5579265A (de)
EP (1) EP0669576B1 (de)
JP (1) JPH07254297A (de)
DE (1) DE69500007T2 (de)
FR (1) FR2716743B1 (de)

Families Citing this family (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE69626625T2 (de) * 1996-04-18 2003-10-02 St Microelectronics Srl Verfahren, um redundante fehlerhafte Adressen in einer Speicheranordnung mit Redundanz zu erkennen
US5793682A (en) * 1996-11-01 1998-08-11 Cypress Semiconductor Corp. Circuit and method for disabling a bitline load
FR2758645B1 (fr) * 1997-01-22 2001-12-14 Sgs Thomson Microelectronics Dispositif et procede de programmation d'une memoire
JP2000123593A (ja) * 1998-08-13 2000-04-28 Toshiba Corp 半導体記憶装置及びその製造方法
US6484271B1 (en) 1999-09-16 2002-11-19 Koninklijke Philips Electronics N.V. Memory redundancy techniques
DE10002139A1 (de) * 2000-01-19 2001-08-02 Infineon Technologies Ag Datenspeicher
EP1126372B1 (de) * 2000-02-14 2005-05-18 STMicroelectronics S.r.l. Nichtflüchtige Speicheranordnung mit konfigurierbarer Zeilenredundanz
US6396749B2 (en) * 2000-05-31 2002-05-28 Advanced Micro Devices, Inc. Dual-ported CAMs for a simultaneous operation flash memory
KR100399435B1 (ko) * 2001-02-27 2003-09-29 주식회사 하이닉스반도체 반도체 메모리 장치와 그의 리페어 해석 방법
DE10126301A1 (de) 2001-05-30 2002-12-12 Infineon Technologies Ag Speicherbaustein mit einem Testmodus und Vefahren zum Überprüfen von Speicherzellen eines reparierten Speicherbausteins
US7219271B2 (en) * 2001-12-14 2007-05-15 Sandisk 3D Llc Memory device and method for redundancy/self-repair
US6868022B2 (en) * 2003-03-28 2005-03-15 Matrix Semiconductor, Inc. Redundant memory structure using bad bit pointers
DE10338022A1 (de) 2003-08-19 2005-03-31 Infineon Technologies Ag Verfahren zum Adressieren eines regulären und eines redundanten Speicherbereiches in einer Speicherschaltung sowie eine Adressdecodierschaltung hierfür
DE10343388A1 (de) * 2003-09-19 2005-02-10 Infineon Technologies Ag Integrierte Schaltung mit einem Fuse-Speicher und Verfahren zum Betreiben einer integrierten Schaltung mit einem Fuse-Speicher
WO2005104136A1 (ja) * 2004-04-21 2005-11-03 Spansion Llc 不揮発性半導体装置および不揮発性半導体装置の消去動作不良自動救済方法
KR100624287B1 (ko) * 2004-05-11 2006-09-18 에스티마이크로일렉트로닉스 엔.브이. 낸드 플래시 메모리 소자의 리던던시 회로
DE102004027423A1 (de) * 2004-06-04 2006-07-20 Infineon Technologies Ag Speicherschaltung mit redundanten Speicherbereichen
DE602004002947T2 (de) 2004-07-14 2007-06-28 Stmicroelectronics S.R.L., Agrate Brianza NAND Flash Speicher mit Speicherredundanz
US7277336B2 (en) * 2004-12-28 2007-10-02 Sandisk 3D Llc Method and apparatus for improving yield in semiconductor devices by guaranteeing health of redundancy information
US7212454B2 (en) * 2005-06-22 2007-05-01 Sandisk 3D Llc Method and apparatus for programming a memory array
US7286380B2 (en) * 2005-09-29 2007-10-23 Intel Corporation Reconfigurable memory block redundancy to repair defective input/output lines
US7301832B2 (en) * 2005-11-03 2007-11-27 Atmel Corporation Compact column redundancy CAM architecture for concurrent read and write operations in multi-segment memory arrays
US7966518B2 (en) * 2007-05-15 2011-06-21 Sandisk Corporation Method for repairing a neighborhood of rows in a memory array using a patch table
US7958390B2 (en) * 2007-05-15 2011-06-07 Sandisk Corporation Memory device for repairing a neighborhood of rows in a memory array using a patch table
WO2009141849A1 (ja) * 2008-05-21 2009-11-26 株式会社アドバンテスト パターン発生器

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4744060A (en) * 1984-10-19 1988-05-10 Fujitsu Limited Bipolar-transistor type random access memory having redundancy configuration
JPS6238599A (ja) * 1985-08-13 1987-02-19 Mitsubishi Electric Corp 半導体記憶装置
JPS6433800A (en) * 1987-07-29 1989-02-03 Toshiba Corp Semiconductor memory
JP2773271B2 (ja) * 1989-07-26 1998-07-09 日本電気株式会社 半導体記憶装置
JPH05114300A (ja) * 1991-05-21 1993-05-07 Citizen Watch Co Ltd 半導体記憶装置
JP2829156B2 (ja) * 1991-07-25 1998-11-25 株式会社東芝 不揮発性半導体記憶装置の冗長回路
JPH05314789A (ja) * 1992-05-14 1993-11-26 Fujitsu Ltd 冗長アドレス記憶回路
US5347484A (en) * 1992-06-19 1994-09-13 Intel Corporation Nonvolatile memory with blocked redundant columns and corresponding content addressable memory sets
US5381370A (en) * 1993-08-24 1995-01-10 Cypress Semiconductor Corporation Memory with minimized redundancy access delay
US5438546A (en) * 1994-06-02 1995-08-01 Intel Corporation Programmable redundancy scheme suitable for single-bit state and multibit state nonvolatile memories

Also Published As

Publication number Publication date
EP0669576B1 (de) 1996-06-19
DE69500007T2 (de) 1996-12-12
JPH07254297A (ja) 1995-10-03
FR2716743A1 (fr) 1995-09-01
FR2716743B1 (fr) 1996-09-27
US5579265A (en) 1996-11-26
EP0669576A1 (de) 1995-08-30

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8328 Change in the person/name/address of the agent

Representative=s name: PATENTANWALTSKANZLEI LIERMANN-CASTELL, 52349 DUEREN

8339 Ceased/non-payment of the annual fee