GB2352069B - Memory data and address checking - Google Patents

Abstract

An integrated solid state memory device 22 (and Fig. 8) includes addressable memory locations 33, and receives an address identifying at least one memory location, and associated verification information (e.g. parity or error correcting information). Within the device, decoding logic 31, 32 decodes the received address, and verification logic 30 verifies the received address. The verification logic can be configured to prevent access to, or modification of, the memory locations, and/or prevent output of the content of an addressed memory location, where address verification is negative, under which circumstances an error signal can be generated and used to report a fault to the memory controller (20, Fig.2) and/or processor (12, Fig. 1), or to cause a retry of the addressing operation. The address verification can be performed at memory bank level if the device includes separate memory banks (Fig. 7). The verification logic 30 can also verify data supplied to the data buffer, such that storage of the data is prevented where data verification is negative: the independent claim relates to this data verification aspect.