DE60212982D1 - Dynamische spaltenblockauswahl - Google Patents

Dynamische spaltenblockauswahl

Info

Publication number
DE60212982D1
DE60212982D1 DE60212982T DE60212982T DE60212982D1 DE 60212982 D1 DE60212982 D1 DE 60212982D1 DE 60212982 T DE60212982 T DE 60212982T DE 60212982 T DE60212982 T DE 60212982T DE 60212982 D1 DE60212982 D1 DE 60212982D1
Authority
DE
Germany
Prior art keywords
memory cells
selecting circuits
data
strobe
columns
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60212982T
Other languages
English (en)
Other versions
DE60212982T2 (de
Inventor
Raul Adrian Cernea
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SanDisk Corp
Original Assignee
SanDisk Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SanDisk Corp filed Critical SanDisk Corp
Publication of DE60212982D1 publication Critical patent/DE60212982D1/de
Application granted granted Critical
Publication of DE60212982T2 publication Critical patent/DE60212982T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1048Data bus control circuits, e.g. precharging, presetting, equalising
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1036Read-write modes for single port memories, i.e. having either a random port or a serial port using data shift registers
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/106Data output latches
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1087Data input latches
DE60212982T 2001-09-17 2002-09-17 Dynamische spaltenblockauswahl Expired - Lifetime DE60212982T2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/956,416 US6560146B2 (en) 2001-09-17 2001-09-17 Dynamic column block selection
US956416 2001-09-17
PCT/US2002/029527 WO2003025939A2 (en) 2001-09-17 2002-09-17 Dynamic column block selection

Publications (2)

Publication Number Publication Date
DE60212982D1 true DE60212982D1 (de) 2006-08-17
DE60212982T2 DE60212982T2 (de) 2007-02-15

Family

ID=25498221

Family Applications (2)

Application Number Title Priority Date Filing Date
DE60230551T Expired - Lifetime DE60230551D1 (de) 2001-09-17 2002-09-17 Dynamische Spaltenblockauswahl
DE60212982T Expired - Lifetime DE60212982T2 (de) 2001-09-17 2002-09-17 Dynamische spaltenblockauswahl

Family Applications Before (1)

Application Number Title Priority Date Filing Date
DE60230551T Expired - Lifetime DE60230551D1 (de) 2001-09-17 2002-09-17 Dynamische Spaltenblockauswahl

Country Status (9)

Country Link
US (2) US6560146B2 (de)
EP (2) EP1428220B1 (de)
JP (1) JP2005504404A (de)
KR (1) KR100918592B1 (de)
CN (1) CN100476986C (de)
AT (2) ATE418782T1 (de)
DE (2) DE60230551D1 (de)
TW (1) TW580702B (de)
WO (1) WO2003025939A2 (de)

Families Citing this family (33)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7170802B2 (en) * 2003-12-31 2007-01-30 Sandisk Corporation Flexible and area efficient column redundancy for non-volatile memories
US6560146B2 (en) * 2001-09-17 2003-05-06 Sandisk Corporation Dynamic column block selection
US6985388B2 (en) * 2001-09-17 2006-01-10 Sandisk Corporation Dynamic column block selection
US20030154331A1 (en) * 2002-02-13 2003-08-14 Globespanvirata Incorporated System and method for shared use of common GPIO line
US6879526B2 (en) * 2002-10-31 2005-04-12 Ring Technology Enterprises Llc Methods and apparatus for improved memory access
US7707351B2 (en) * 2002-10-31 2010-04-27 Ring Technology Enterprises Of Texas, Llc Methods and systems for an identifier-based memory section
US20050007858A1 (en) * 2003-07-10 2005-01-13 Smith Kenneth K. Method and system for reducing power when writing information to MRAM
TWI286764B (en) * 2005-01-20 2007-09-11 Himax Tech Ltd Memory architecture of display device and memory writing method for the same
WO2006106577A1 (ja) * 2005-03-31 2006-10-12 Spansion Llc 半導体装置及びその制御方法
US7447066B2 (en) * 2005-11-08 2008-11-04 Sandisk Corporation Memory with retargetable memory cell redundancy
US8218349B2 (en) * 2009-05-26 2012-07-10 Crocus Technology Sa Non-volatile logic devices using magnetic tunnel junctions
US8102705B2 (en) 2009-06-05 2012-01-24 Sandisk Technologies Inc. Structure and method for shuffling data within non-volatile memory devices
US8027195B2 (en) * 2009-06-05 2011-09-27 SanDisk Technologies, Inc. Folding data stored in binary format into multi-state format within non-volatile memory devices
US7974124B2 (en) * 2009-06-24 2011-07-05 Sandisk Corporation Pointer based column selection techniques in non-volatile memories
US20110002169A1 (en) 2009-07-06 2011-01-06 Yan Li Bad Column Management with Bit Information in Non-Volatile Memory Systems
US8144512B2 (en) 2009-12-18 2012-03-27 Sandisk Technologies Inc. Data transfer flows for on-chip folding
US8468294B2 (en) * 2009-12-18 2013-06-18 Sandisk Technologies Inc. Non-volatile memory with multi-gear control using on-chip folding of data
US8725935B2 (en) 2009-12-18 2014-05-13 Sandisk Technologies Inc. Balanced performance for on-chip folding of non-volatile memories
US9342446B2 (en) 2011-03-29 2016-05-17 SanDisk Technologies, Inc. Non-volatile memory system allowing reverse eviction of data updates to non-volatile binary cache
US8842473B2 (en) 2012-03-15 2014-09-23 Sandisk Technologies Inc. Techniques for accessing column selecting shift register with skipped entries in non-volatile memories
US8681548B2 (en) 2012-05-03 2014-03-25 Sandisk Technologies Inc. Column redundancy circuitry for non-volatile memory
KR20140031554A (ko) * 2012-09-04 2014-03-13 에스케이하이닉스 주식회사 불휘발성 메모리 장치 및 그것의 동작 방법
US9490035B2 (en) 2012-09-28 2016-11-08 SanDisk Technologies, Inc. Centralized variable rate serializer and deserializer for bad column management
US8897080B2 (en) 2012-09-28 2014-11-25 Sandisk Technologies Inc. Variable rate serial to parallel shift register
US9076506B2 (en) 2012-09-28 2015-07-07 Sandisk Technologies Inc. Variable rate parallel to serial shift register
US9934872B2 (en) 2014-10-30 2018-04-03 Sandisk Technologies Llc Erase stress and delta erase loop count methods for various fail modes in non-volatile memory
US9224502B1 (en) 2015-01-14 2015-12-29 Sandisk Technologies Inc. Techniques for detection and treating memory hole to local interconnect marginality defects
US10032524B2 (en) 2015-02-09 2018-07-24 Sandisk Technologies Llc Techniques for determining local interconnect defects
US9564219B2 (en) 2015-04-08 2017-02-07 Sandisk Technologies Llc Current based detection and recording of memory hole-interconnect spacing defects
US9269446B1 (en) 2015-04-08 2016-02-23 Sandisk Technologies Inc. Methods to improve programming of slow cells
US10170166B1 (en) * 2017-09-08 2019-01-01 Winbond Electronics Corp. Data transmission apparatus for memory and data transmission method thereof
US10971202B1 (en) 2020-04-15 2021-04-06 Sandisk Technologies Llc Low latency data transfer
JP7002807B1 (ja) * 2021-03-04 2022-01-20 茉美 安平 草抜き装置

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1268283A (en) * 1970-04-02 1972-03-29 Ibm Connect module
US3895360A (en) * 1974-01-29 1975-07-15 Westinghouse Electric Corp Block oriented random access memory
JPS61265798A (ja) * 1985-05-20 1986-11-25 Fujitsu Ltd 半導体記憶装置
JPS61292747A (ja) * 1985-06-20 1986-12-23 Nec Corp バツフアレジスタ
JPS62287497A (ja) * 1986-06-06 1987-12-14 Fujitsu Ltd 半導体記憶装置
US5095344A (en) 1988-06-08 1992-03-10 Eliyahou Harari Highly compact eprom and flash eeprom devices
US5268870A (en) 1988-06-08 1993-12-07 Eliyahou Harari Flash EEPROM system and intelligent programming and erasing methods therefor
DE69033262T2 (de) 1989-04-13 2000-02-24 Sandisk Corp EEPROM-Karte mit Austauch von fehlerhaften Speicherzellen und Zwischenspeicher
US5172338B1 (en) 1989-04-13 1997-07-08 Sandisk Corp Multi-state eeprom read and write circuits and techniques
US5343063A (en) 1990-12-18 1994-08-30 Sundisk Corporation Dense vertical programmable read only memory cell structure and processes for making them
US5270979A (en) 1991-03-15 1993-12-14 Sundisk Corporation Method for optimum erasing of EEPROM
US6230233B1 (en) 1991-09-13 2001-05-08 Sandisk Corporation Wear leveling techniques for flash EEPROM systems
US6222762B1 (en) 1992-01-14 2001-04-24 Sandisk Corporation Multi-state memory
JP2554816B2 (ja) * 1992-02-20 1996-11-20 株式会社東芝 半導体記憶装置
JPH06150666A (ja) * 1992-11-12 1994-05-31 Sanyo Electric Co Ltd 入力回路
US5783958A (en) * 1996-01-19 1998-07-21 Sgs-Thomson Microelectronics, Inc. Switching master slave circuit
US6091666A (en) * 1996-10-04 2000-07-18 Sony Corporation Nonvolatile flash memory with fast data programming operation
JP3317187B2 (ja) * 1997-04-25 2002-08-26 日本電気株式会社 半導体記憶装置
JPH11162183A (ja) 1997-11-28 1999-06-18 New Core Technology Kk 不揮発性半導体多値メモリ装置
KR200257595Y1 (ko) * 2001-07-20 2001-12-24 배호영 식물이 활착 된 식생 롤
US6560146B2 (en) * 2001-09-17 2003-05-06 Sandisk Corporation Dynamic column block selection

Also Published As

Publication number Publication date
US6560146B2 (en) 2003-05-06
KR20040058183A (ko) 2004-07-03
EP1428220A2 (de) 2004-06-16
US6822911B2 (en) 2004-11-23
ATE418782T1 (de) 2009-01-15
EP1428220B1 (de) 2006-07-05
US20030223274A1 (en) 2003-12-04
ATE332563T1 (de) 2006-07-15
EP1681680B1 (de) 2008-12-24
EP1681680A2 (de) 2006-07-19
WO2003025939A3 (en) 2003-11-13
DE60230551D1 (de) 2009-02-05
CN1568522A (zh) 2005-01-19
WO2003025939A2 (en) 2003-03-27
US20030058691A1 (en) 2003-03-27
TW580702B (en) 2004-03-21
KR100918592B1 (ko) 2009-09-24
CN100476986C (zh) 2009-04-08
DE60212982T2 (de) 2007-02-15
JP2005504404A (ja) 2005-02-10
EP1681680A3 (de) 2006-08-02

Similar Documents

Publication Publication Date Title
ATE418782T1 (de) Dynamische spaltenblockauswahl
US20030147299A1 (en) Semiconductor memory device capable of making switch between synchronizing signals for operation on data generated by different circuit configurations
KR0154586B1 (ko) 반도체 기억장치
US11625196B2 (en) Semiconductor memory device and operating method thereof
US7349289B2 (en) Two-bit per I/O line write data bus for DDR1 and DDR2 operating modes in a DRAM
JP4152308B2 (ja) 半導体集積回路装置
US6982923B2 (en) Semiconductor memory device adaptive for use circumstance
KR100578233B1 (ko) 동기식메모리장치의 데이터 입출력 가변제어장치
KR20020040111A (ko) 쿼드 데이터 레이트 싱크로노스 에스램의 리드/라이트를위한 워드라인 및 비트라인 구동 방법 및 그 회로
JP5016888B2 (ja) 不揮発性半導体記憶装置
KR960042730A (ko) 반도체기억장치
US7016235B2 (en) Data sorting in memories
KR100524944B1 (ko) 고속의 기입 및 독출동작을 가능하게 하는 입출력 구조를갖는 반도체 메모리장치
TW349226B (en) A test method of high speed memory devices in which limit conditions for the clock signals are defined
US6735101B2 (en) Semiconductor memory
KR920702574A (ko) 반도체 집적회로
KR100673128B1 (ko) 어드레스 전송 장치
KR970060223A (ko) 반도체 기억 장치 및 그 제어 방법
US7184357B2 (en) Decoding circuit for memory device
KR20070036593A (ko) 반도체메모리소자의 데이터 입력장치
JPS6150285A (ja) シリアルメモリ装置
JP4568522B2 (ja) 半導体記憶装置
KR20040002116A (ko) 반도체 테스트 회로
JP3580266B2 (ja) 半導体記憶装置
KR100451462B1 (ko) 컴프레스 테스트 장치

Legal Events

Date Code Title Description
8327 Change in the person/name/address of the patent owner

Owner name: SANDISK CORP., MILPITAS, CALIF., US

8364 No opposition during term of opposition
R082 Change of representative

Ref document number: 1428220

Country of ref document: EP

Representative=s name: PATENTANWAELTE MAXTON LANGMAACK & PARTNER, DE