DE60230551D1 - Dynamische Spaltenblockauswahl - Google Patents

Dynamische Spaltenblockauswahl

Info

Publication number
DE60230551D1
DE60230551D1 DE60230551T DE60230551T DE60230551D1 DE 60230551 D1 DE60230551 D1 DE 60230551D1 DE 60230551 T DE60230551 T DE 60230551T DE 60230551 T DE60230551 T DE 60230551T DE 60230551 D1 DE60230551 D1 DE 60230551D1
Authority
DE
Germany
Prior art keywords
memory cells
selecting circuits
data
strobe
columns
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60230551T
Other languages
English (en)
Inventor
Paul Adrian Cernea
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SanDisk Corp
Original Assignee
SanDisk Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SanDisk Corp filed Critical SanDisk Corp
Application granted granted Critical
Publication of DE60230551D1 publication Critical patent/DE60230551D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1048—Data bus control circuits, e.g. precharging, presetting, equalising
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1036—Read-write modes for single port memories, i.e. having either a random port or a serial port using data shift registers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/106—Data output latches
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1087—Data input latches

Landscapes

  • Static Random-Access Memory (AREA)
  • Read Only Memory (AREA)
  • Supplying Of Containers To The Packaging Station (AREA)
  • Oscillators With Electromechanical Resonators (AREA)
  • Transition And Organic Metals Composition Catalysts For Addition Polymerization (AREA)
  • Storage Device Security (AREA)
DE60230551T 2001-09-17 2002-09-17 Dynamische Spaltenblockauswahl Expired - Lifetime DE60230551D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US09/956,416 US6560146B2 (en) 2001-09-17 2001-09-17 Dynamic column block selection

Publications (1)

Publication Number Publication Date
DE60230551D1 true DE60230551D1 (de) 2009-02-05

Family

ID=25498221

Family Applications (2)

Application Number Title Priority Date Filing Date
DE60212982T Expired - Lifetime DE60212982T2 (de) 2001-09-17 2002-09-17 Dynamische spaltenblockauswahl
DE60230551T Expired - Lifetime DE60230551D1 (de) 2001-09-17 2002-09-17 Dynamische Spaltenblockauswahl

Family Applications Before (1)

Application Number Title Priority Date Filing Date
DE60212982T Expired - Lifetime DE60212982T2 (de) 2001-09-17 2002-09-17 Dynamische spaltenblockauswahl

Country Status (9)

Country Link
US (2) US6560146B2 (de)
EP (2) EP1428220B1 (de)
JP (1) JP2005504404A (de)
KR (1) KR100918592B1 (de)
CN (1) CN100476986C (de)
AT (2) ATE332563T1 (de)
DE (2) DE60212982T2 (de)
TW (1) TW580702B (de)
WO (1) WO2003025939A2 (de)

Families Citing this family (33)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7170802B2 (en) * 2003-12-31 2007-01-30 Sandisk Corporation Flexible and area efficient column redundancy for non-volatile memories
US6560146B2 (en) * 2001-09-17 2003-05-06 Sandisk Corporation Dynamic column block selection
US6985388B2 (en) * 2001-09-17 2006-01-10 Sandisk Corporation Dynamic column block selection
US20030154331A1 (en) * 2002-02-13 2003-08-14 Globespanvirata Incorporated System and method for shared use of common GPIO line
US7707351B2 (en) * 2002-10-31 2010-04-27 Ring Technology Enterprises Of Texas, Llc Methods and systems for an identifier-based memory section
US6879526B2 (en) * 2002-10-31 2005-04-12 Ring Technology Enterprises Llc Methods and apparatus for improved memory access
US20050007858A1 (en) * 2003-07-10 2005-01-13 Smith Kenneth K. Method and system for reducing power when writing information to MRAM
TWI286764B (en) * 2005-01-20 2007-09-11 Himax Tech Ltd Memory architecture of display device and memory writing method for the same
JP4896011B2 (ja) * 2005-03-31 2012-03-14 スパンション エルエルシー 半導体装置及びその制御方法
US7447066B2 (en) * 2005-11-08 2008-11-04 Sandisk Corporation Memory with retargetable memory cell redundancy
US8218349B2 (en) * 2009-05-26 2012-07-10 Crocus Technology Sa Non-volatile logic devices using magnetic tunnel junctions
US8102705B2 (en) 2009-06-05 2012-01-24 Sandisk Technologies Inc. Structure and method for shuffling data within non-volatile memory devices
US8027195B2 (en) * 2009-06-05 2011-09-27 SanDisk Technologies, Inc. Folding data stored in binary format into multi-state format within non-volatile memory devices
US7974124B2 (en) * 2009-06-24 2011-07-05 Sandisk Corporation Pointer based column selection techniques in non-volatile memories
US20110002169A1 (en) * 2009-07-06 2011-01-06 Yan Li Bad Column Management with Bit Information in Non-Volatile Memory Systems
US8468294B2 (en) * 2009-12-18 2013-06-18 Sandisk Technologies Inc. Non-volatile memory with multi-gear control using on-chip folding of data
US8144512B2 (en) 2009-12-18 2012-03-27 Sandisk Technologies Inc. Data transfer flows for on-chip folding
US8725935B2 (en) 2009-12-18 2014-05-13 Sandisk Technologies Inc. Balanced performance for on-chip folding of non-volatile memories
US9342446B2 (en) 2011-03-29 2016-05-17 SanDisk Technologies, Inc. Non-volatile memory system allowing reverse eviction of data updates to non-volatile binary cache
US8842473B2 (en) 2012-03-15 2014-09-23 Sandisk Technologies Inc. Techniques for accessing column selecting shift register with skipped entries in non-volatile memories
US8681548B2 (en) 2012-05-03 2014-03-25 Sandisk Technologies Inc. Column redundancy circuitry for non-volatile memory
KR20140031554A (ko) * 2012-09-04 2014-03-13 에스케이하이닉스 주식회사 불휘발성 메모리 장치 및 그것의 동작 방법
US9076506B2 (en) 2012-09-28 2015-07-07 Sandisk Technologies Inc. Variable rate parallel to serial shift register
US9490035B2 (en) 2012-09-28 2016-11-08 SanDisk Technologies, Inc. Centralized variable rate serializer and deserializer for bad column management
US8897080B2 (en) 2012-09-28 2014-11-25 Sandisk Technologies Inc. Variable rate serial to parallel shift register
US9934872B2 (en) 2014-10-30 2018-04-03 Sandisk Technologies Llc Erase stress and delta erase loop count methods for various fail modes in non-volatile memory
US9224502B1 (en) 2015-01-14 2015-12-29 Sandisk Technologies Inc. Techniques for detection and treating memory hole to local interconnect marginality defects
US10032524B2 (en) 2015-02-09 2018-07-24 Sandisk Technologies Llc Techniques for determining local interconnect defects
US9269446B1 (en) 2015-04-08 2016-02-23 Sandisk Technologies Inc. Methods to improve programming of slow cells
US9564219B2 (en) 2015-04-08 2017-02-07 Sandisk Technologies Llc Current based detection and recording of memory hole-interconnect spacing defects
US10170166B1 (en) * 2017-09-08 2019-01-01 Winbond Electronics Corp. Data transmission apparatus for memory and data transmission method thereof
US10971202B1 (en) 2020-04-15 2021-04-06 Sandisk Technologies Llc Low latency data transfer
JP7002807B1 (ja) * 2021-03-04 2022-01-20 茉美 安平 草抜き装置

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1268283A (en) * 1970-04-02 1972-03-29 Ibm Connect module
US3895360A (en) * 1974-01-29 1975-07-15 Westinghouse Electric Corp Block oriented random access memory
JPS61265798A (ja) * 1985-05-20 1986-11-25 Fujitsu Ltd 半導体記憶装置
JPS61292747A (ja) * 1985-06-20 1986-12-23 Nec Corp バツフアレジスタ
JPS62287497A (ja) * 1986-06-06 1987-12-14 Fujitsu Ltd 半導体記憶装置
US5095344A (en) 1988-06-08 1992-03-10 Eliyahou Harari Highly compact eprom and flash eeprom devices
US5268870A (en) 1988-06-08 1993-12-07 Eliyahou Harari Flash EEPROM system and intelligent programming and erasing methods therefor
US5172338B1 (en) 1989-04-13 1997-07-08 Sandisk Corp Multi-state eeprom read and write circuits and techniques
DE69033438T2 (de) 1989-04-13 2000-07-06 Sandisk Corp., Santa Clara Austausch von fehlerhaften Speicherzellen einer EEprommatritze
US5343063A (en) 1990-12-18 1994-08-30 Sundisk Corporation Dense vertical programmable read only memory cell structure and processes for making them
US5270979A (en) 1991-03-15 1993-12-14 Sundisk Corporation Method for optimum erasing of EEPROM
US6230233B1 (en) 1991-09-13 2001-05-08 Sandisk Corporation Wear leveling techniques for flash EEPROM systems
US6222762B1 (en) 1992-01-14 2001-04-24 Sandisk Corporation Multi-state memory
JP2554816B2 (ja) * 1992-02-20 1996-11-20 株式会社東芝 半導体記憶装置
JPH06150666A (ja) * 1992-11-12 1994-05-31 Sanyo Electric Co Ltd 入力回路
US5783958A (en) * 1996-01-19 1998-07-21 Sgs-Thomson Microelectronics, Inc. Switching master slave circuit
US6091666A (en) * 1996-10-04 2000-07-18 Sony Corporation Nonvolatile flash memory with fast data programming operation
JP3317187B2 (ja) * 1997-04-25 2002-08-26 日本電気株式会社 半導体記憶装置
JPH11162183A (ja) 1997-11-28 1999-06-18 New Core Technology Kk 不揮発性半導体多値メモリ装置
KR200257595Y1 (ko) * 2001-07-20 2001-12-24 배호영 식물이 활착 된 식생 롤
US6560146B2 (en) * 2001-09-17 2003-05-06 Sandisk Corporation Dynamic column block selection

Also Published As

Publication number Publication date
CN100476986C (zh) 2009-04-08
ATE418782T1 (de) 2009-01-15
EP1681680A3 (de) 2006-08-02
CN1568522A (zh) 2005-01-19
DE60212982D1 (de) 2006-08-17
EP1428220A2 (de) 2004-06-16
KR20040058183A (ko) 2004-07-03
EP1681680A2 (de) 2006-07-19
EP1428220B1 (de) 2006-07-05
US20030223274A1 (en) 2003-12-04
WO2003025939A2 (en) 2003-03-27
DE60212982T2 (de) 2007-02-15
US6822911B2 (en) 2004-11-23
EP1681680B1 (de) 2008-12-24
WO2003025939A3 (en) 2003-11-13
JP2005504404A (ja) 2005-02-10
TW580702B (en) 2004-03-21
ATE332563T1 (de) 2006-07-15
US20030058691A1 (en) 2003-03-27
US6560146B2 (en) 2003-05-06
KR100918592B1 (ko) 2009-09-24

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