DE602005017651D1 - Mehrspalten-adressierungsmodus-speichersystem mit einem integrierten schaltungsspeicherbaustein - Google Patents

Mehrspalten-adressierungsmodus-speichersystem mit einem integrierten schaltungsspeicherbaustein

Info

Publication number
DE602005017651D1
DE602005017651D1 DE602005017651T DE602005017651T DE602005017651D1 DE 602005017651 D1 DE602005017651 D1 DE 602005017651D1 DE 602005017651 T DE602005017651 T DE 602005017651T DE 602005017651 T DE602005017651 T DE 602005017651T DE 602005017651 D1 DE602005017651 D1 DE 602005017651D1
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DE
Germany
Prior art keywords
storage cells
integrated circuit
column
row
accessible
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
DE602005017651T
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English (en)
Inventor
Frederick A Ware
Lawrence Lai
Chad A Bellows
Wayne S Richardson
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Rambus Inc
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Rambus Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
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Application filed by Rambus Inc filed Critical Rambus Inc
Publication of DE602005017651D1 publication Critical patent/DE602005017651D1/de
Active legal-status Critical Current
Anticipated expiration legal-status Critical

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/10—Decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/16—Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Dram (AREA)
  • Static Random-Access Memory (AREA)
DE602005017651T 2004-09-30 2005-09-12 Mehrspalten-adressierungsmodus-speichersystem mit einem integrierten schaltungsspeicherbaustein Active DE602005017651D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/955,193 US7280428B2 (en) 2004-09-30 2004-09-30 Multi-column addressing mode memory system including an integrated circuit memory device
PCT/US2005/032770 WO2006039106A1 (en) 2004-09-30 2005-09-12 Multi-column addressing mode memory system including an intergrated circuit memory device

Publications (1)

Publication Number Publication Date
DE602005017651D1 true DE602005017651D1 (de) 2009-12-24

Family

ID=35520698

Family Applications (1)

Application Number Title Priority Date Filing Date
DE602005017651T Active DE602005017651D1 (de) 2004-09-30 2005-09-12 Mehrspalten-adressierungsmodus-speichersystem mit einem integrierten schaltungsspeicherbaustein

Country Status (5)

Country Link
US (7) US7280428B2 (de)
EP (1) EP1800311B1 (de)
AT (1) ATE448548T1 (de)
DE (1) DE602005017651D1 (de)
WO (1) WO2006039106A1 (de)

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US7280428B2 (en) 2007-10-09
US20120170399A1 (en) 2012-07-05
US8050134B2 (en) 2011-11-01
EP1800311A1 (de) 2007-06-27
US8154947B2 (en) 2012-04-10
US8908466B2 (en) 2014-12-09
US20110153932A1 (en) 2011-06-23
US20060072366A1 (en) 2006-04-06
US7907470B2 (en) 2011-03-15
US7505356B2 (en) 2009-03-17
US20090193202A1 (en) 2009-07-30
US20080062807A1 (en) 2008-03-13
US8432766B2 (en) 2013-04-30
ATE448548T1 (de) 2009-11-15

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