DE60037251D1 - Anordnung zur Herstellung von Löthöckern auf Halbleitersubstraten unter Generierung elektrischer Ladung, Methode und Anordnung zum Entfernen dieser Ladungen, und elektrische Ladung generierendes Halbleitersubstrat - Google Patents

Anordnung zur Herstellung von Löthöckern auf Halbleitersubstraten unter Generierung elektrischer Ladung, Methode und Anordnung zum Entfernen dieser Ladungen, und elektrische Ladung generierendes Halbleitersubstrat

Info

Publication number
DE60037251D1
DE60037251D1 DE60037251T DE60037251T DE60037251D1 DE 60037251 D1 DE60037251 D1 DE 60037251D1 DE 60037251 T DE60037251 T DE 60037251T DE 60037251 T DE60037251 T DE 60037251T DE 60037251 D1 DE60037251 D1 DE 60037251D1
Authority
DE
Germany
Prior art keywords
charge
wafer
arrangement
electrical charge
semiconductor substrates
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE60037251T
Other languages
English (en)
Other versions
DE60037251T2 (de
Inventor
Shoriki Narita
Yasutaka Tsuboi
Masahiko Ikeya
Takaharu Mae
Shinji Kanayama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP30885599A external-priority patent/JP3655787B2/ja
Priority claimed from JP2000184467A external-priority patent/JP4570210B2/ja
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Application granted granted Critical
Publication of DE60037251D1 publication Critical patent/DE60037251D1/de
Publication of DE60037251T2 publication Critical patent/DE60037251T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67144—Apparatus for mounting on conductive members, e.g. leadframes or conductors on insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67138—Apparatus for wiring semiconductor or solid state device
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/974—Substrate surface preparation

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
  • Light Receiving Elements (AREA)
  • Solid State Image Pick-Up Elements (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Micromachines (AREA)
DE60037251T 1999-07-02 2000-06-29 Anordnung zur Herstellung von Löthöckern auf Halbleitersubstraten unter Generierung elektrischer Ladung, Methode und Anordnung zum Entfernen dieser Ladungen, und elektrische Ladung generierendes Halbleitersubstrat Expired - Fee Related DE60037251T2 (de)

Applications Claiming Priority (11)

Application Number Priority Date Filing Date Title
JP18905399 1999-07-02
JP18905399 1999-07-02
JP29370299 1999-10-15
JP29370299 1999-10-15
JP30885599A JP3655787B2 (ja) 1999-07-02 1999-10-29 電荷発生基板用バンプ形成装置及び電荷発生基板の除電方法
JP30885599 1999-10-29
JP32397999 1999-11-15
JP32397999 1999-11-15
JP2000184467 2000-06-20
JP2000184467A JP4570210B2 (ja) 1999-07-02 2000-06-20 電荷発生基板用バンプ形成装置
PCT/JP2000/004280 WO2001003176A1 (fr) 1999-07-02 2000-06-29 Dispositif de formation de bosses sur substrat semi-conducteur generateur de charge electrique, procede de suppression de la charge electrique d'un substrat generateur de charge electrique, dispositif de suppression de la charge electrique d'un substrat generateur de charge electrique et substrat semi-conducteur generateur

Publications (2)

Publication Number Publication Date
DE60037251D1 true DE60037251D1 (de) 2008-01-10
DE60037251T2 DE60037251T2 (de) 2008-10-09

Family

ID=27528983

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60037251T Expired - Fee Related DE60037251T2 (de) 1999-07-02 2000-06-29 Anordnung zur Herstellung von Löthöckern auf Halbleitersubstraten unter Generierung elektrischer Ladung, Methode und Anordnung zum Entfernen dieser Ladungen, und elektrische Ladung generierendes Halbleitersubstrat

Country Status (7)

Country Link
US (3) US6818975B1 (de)
EP (1) EP1202336B1 (de)
KR (1) KR100446262B1 (de)
CN (1) CN100382261C (de)
AT (1) ATE379847T1 (de)
DE (1) DE60037251T2 (de)
WO (1) WO2001003176A1 (de)

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* Cited by examiner, † Cited by third party
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JP4456234B2 (ja) * 2000-07-04 2010-04-28 パナソニック株式会社 バンプ形成方法
US20030209310A1 (en) * 2002-05-13 2003-11-13 Fuentes Anastacio C. Apparatus, system and method to reduce wafer warpage
JP4206320B2 (ja) * 2003-09-19 2009-01-07 株式会社ルネサステクノロジ 半導体集積回路装置の製造方法
US8020281B2 (en) * 2008-08-19 2011-09-20 Silverbrook Research Pty Ltd Printed circuit board bonding device
US8296933B2 (en) * 2008-08-19 2012-10-30 Zamtec Limited Fastening apparatus with authentication system
CN102426412A (zh) * 2011-07-12 2012-04-25 上海华力微电子有限公司 一种掩模板表面微尘去除的方法
US8324783B1 (en) 2012-04-24 2012-12-04 UltraSolar Technology, Inc. Non-decaying electric power generation from pyroelectric materials
WO2015073808A2 (en) 2013-11-15 2015-05-21 Greenlee Textron Inc. Automated bender and systems and methods for providing data to operate an automated bender
JP6077023B2 (ja) * 2015-01-09 2017-02-08 株式会社伸興 静電気除去装置及び静電気除去方法
JP6456768B2 (ja) * 2015-05-18 2019-01-23 株式会社ディスコ 加工装置
KR102355419B1 (ko) * 2016-07-13 2022-01-24 어플라이드 머티어리얼스, 인코포레이티드 개선된 기판 지지부
JP2022510960A (ja) * 2018-12-03 2022-01-28 アプライド マテリアルズ インコーポレイテッド マランゴニ乾燥の方法及び装置
JP7489865B2 (ja) * 2020-08-24 2024-05-24 東京エレクトロン株式会社 基板処理方法及び基板処理装置

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5925370B2 (ja) 1978-12-26 1984-06-16 富士通株式会社 半導体装置の製造方法
JPS62173428A (ja) * 1986-01-28 1987-07-30 Fujitsu Ltd 導波路光デバイス
JPS6477111A (en) * 1987-09-18 1989-03-23 Fujikura Ltd Removal of static electricity of wafer
JPH02203180A (ja) * 1989-02-02 1990-08-13 Sawafuji Electric Co Ltd 冷却装置
JPH03293808A (ja) * 1990-04-11 1991-12-25 Fujitsu Ltd 弾性表面波素子の製造方法
JPH0491422A (ja) * 1990-08-01 1992-03-24 Mitsubishi Electric Corp 半導体装置の製造方法
JPH06232132A (ja) 1993-02-02 1994-08-19 Toshiba Corp バンプ形成装置
US5665167A (en) * 1993-02-16 1997-09-09 Tokyo Electron Kabushiki Kaisha Plasma treatment apparatus having a workpiece-side electrode grounding circuit
US5341979A (en) * 1993-09-03 1994-08-30 Motorola, Inc. Method of bonding a semiconductor substrate to a support substrate and structure therefore
US5719739A (en) * 1994-01-13 1998-02-17 Horiguchi; Noboru Static eliminator
JP3339164B2 (ja) 1994-02-16 2002-10-28 東レ株式会社 樹脂硬化ｔａｂテープの製造装置および製造方法
JP3415283B2 (ja) * 1994-08-31 2003-06-09 株式会社東芝 バンプ形成装置、バンプ形成方法および半導体素子の製造方法
JP3079921B2 (ja) * 1994-11-28 2000-08-21 松下電器産業株式会社 半田ボールの搭載装置および搭載方法
JPH1116874A (ja) 1997-06-26 1999-01-22 Nec Kansai Ltd 遠心乾燥装置
JPH1187392A (ja) 1997-09-09 1999-03-30 Oki Electric Ind Co Ltd バンプ形成方法
JPH11168074A (ja) 1997-12-03 1999-06-22 Hitachi Denshi Ltd 圧電体基板のダイシング方法
US6198616B1 (en) * 1998-04-03 2001-03-06 Applied Materials, Inc. Method and apparatus for supplying a chucking voltage to an electrostatic chuck within a semiconductor wafer processing system
US6056191A (en) * 1998-04-30 2000-05-02 International Business Machines Corporation Method and apparatus for forming solder bumps
JPH11330573A (ja) 1998-05-11 1999-11-30 Toyo Commun Equip Co Ltd バンプ形成方法及びバンプ形成装置
JP2000059165A (ja) * 1998-08-06 2000-02-25 Toshiba Corp 弾性表面波装置およびその製造方法
JP4203152B2 (ja) * 1998-09-11 2008-12-24 株式会社日立メディアエレクトロニクス 弾性表面波装置
WO2000022898A1 (fr) * 1998-10-13 2000-04-20 Matsushita Electric Industrial Co., Ltd. Dispositif de chauffage et procede de chauffage
JP2002009569A (ja) * 2000-06-26 2002-01-11 Toshiba Corp 弾性表面波装置の製造方法
JP2002203995A (ja) * 2000-12-27 2002-07-19 Toshiba Corp 基板加熱方法、基板冷却方法、及びそれらの装置

Also Published As

Publication number Publication date
EP1202336A1 (de) 2002-05-02
CN100382261C (zh) 2008-04-16
US20040035849A1 (en) 2004-02-26
KR100446262B1 (ko) 2004-09-01
EP1202336A4 (de) 2004-06-23
CN1359534A (zh) 2002-07-17
ATE379847T1 (de) 2007-12-15
DE60037251T2 (de) 2008-10-09
US6818975B1 (en) 2004-11-16
US7005368B1 (en) 2006-02-28
EP1202336B1 (de) 2007-11-28
US7014092B2 (en) 2006-03-21
WO2001003176A1 (fr) 2001-01-11
KR20020022076A (ko) 2002-03-23

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: PANASONIC CORP., KADOMA, OSAKA, JP

8320 Willingness to grant licences declared (paragraph 23)
8339 Ceased/non-payment of the annual fee