DE3884859D1 - Dynamische Speicherschaltung mit einem Abfühlschema. - Google Patents
Dynamische Speicherschaltung mit einem Abfühlschema.Info
- Publication number
- DE3884859D1 DE3884859D1 DE88108948T DE3884859T DE3884859D1 DE 3884859 D1 DE3884859 D1 DE 3884859D1 DE 88108948 T DE88108948 T DE 88108948T DE 3884859 T DE3884859 T DE 3884859T DE 3884859 D1 DE3884859 D1 DE 3884859D1
- Authority
- DE
- Germany
- Prior art keywords
- memory circuit
- dynamic memory
- sensing scheme
- sensing
- scheme
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/408—Address circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4091—Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14081187 | 1987-06-04 |
Publications (2)
Publication Number | Publication Date |
---|---|
DE3884859D1 true DE3884859D1 (de) | 1993-11-18 |
DE3884859T2 DE3884859T2 (de) | 1994-02-03 |
Family
ID=15277289
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE88108948T Expired - Fee Related DE3884859T2 (de) | 1987-06-04 | 1988-06-03 | Dynamische Speicherschaltung mit einem Abfühlschema. |
Country Status (5)
Country | Link |
---|---|
US (1) | US4879692A (de) |
EP (1) | EP0293933B1 (de) |
JP (1) | JPH0793002B2 (de) |
KR (1) | KR910009550B1 (de) |
DE (1) | DE3884859T2 (de) |
Families Citing this family (32)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5280448A (en) * | 1987-11-18 | 1994-01-18 | Sony Corporation | Dynamic memory with group bit lines and associated bit line group selector |
JPH0770212B2 (ja) * | 1988-07-19 | 1995-07-31 | 日本電気株式会社 | 半導体メモリ回路 |
JPH07101554B2 (ja) * | 1988-11-29 | 1995-11-01 | 三菱電機株式会社 | 半導体記憶装置およびそのデータ転送方法 |
NL8802973A (nl) * | 1988-12-02 | 1990-07-02 | Philips Nv | Geintegreerde geheugenschakeling. |
US5251177A (en) * | 1989-01-23 | 1993-10-05 | Matsushita Electric Industrial Co., Ltd. | Semiconductor memory device having an improved refresh operation |
DE69020384T2 (de) * | 1989-02-27 | 1996-03-21 | Nec Corp | Integrierte Halbleiterspeicherschaltung mit Möglichkeit zum Maskieren des Schreibens im Speicher. |
EP0617363B1 (de) * | 1989-04-13 | 2000-01-26 | SanDisk Corporation | Austausch von fehlerhaften Speicherzellen einer EEprommatritze |
JP2608140B2 (ja) * | 1989-05-17 | 1997-05-07 | 三菱電機株式会社 | 半導体ダイナミックram |
DE69129603T2 (de) * | 1990-03-12 | 1999-02-11 | Nec Corp | Halbleiterspeicheranordnung mit einem verbesserten Schreibmodus |
JPH0430388A (ja) * | 1990-05-25 | 1992-02-03 | Oki Electric Ind Co Ltd | 半導体記憶回路 |
US5119331A (en) * | 1990-09-04 | 1992-06-02 | Nec Electronics Inc. | Segmented flash write |
DE59103725D1 (de) * | 1990-09-20 | 1995-01-12 | Siemens Ag | Dynamischer halbleiterspeicher mit lokalen und hinsichtlich ihrer ansteuerfunktion optimierten leseverstärker-treiberschaltungen. |
JPH04268287A (ja) * | 1991-02-22 | 1992-09-24 | Nec Ic Microcomput Syst Ltd | 半導体メモリ回路 |
JPH04278288A (ja) * | 1991-03-07 | 1992-10-02 | Toshiba Corp | 半導体記憶装置 |
JPH04298883A (ja) * | 1991-03-26 | 1992-10-22 | Nec Ic Microcomput Syst Ltd | 半導体記憶回路 |
JP3178859B2 (ja) * | 1991-06-05 | 2001-06-25 | 株式会社東芝 | ランダムアクセスメモリ装置およびそのパイプライン・ページモード制御方法 |
US5655113A (en) * | 1994-07-05 | 1997-08-05 | Monolithic System Technology, Inc. | Resynchronization circuit for a memory system and method of operating same |
US5559749A (en) * | 1995-05-11 | 1996-09-24 | Micron Technology, Inc. | Multi-bit block write in a random access memory |
DE19536486C2 (de) * | 1995-09-29 | 1997-08-07 | Siemens Ag | Bewerter- und Verstärkerschaltung |
DE69724327T2 (de) * | 1996-05-17 | 2004-06-17 | Hyundai Electronics America Inc., San Jose | Leistungsreduzierung während eines Blockschreibens |
JPH1031886A (ja) * | 1996-07-17 | 1998-02-03 | Nec Corp | ランダムアクセスメモリ |
US5896339A (en) * | 1996-09-23 | 1999-04-20 | Micron Technology, Inc. | Multi-bit block write in a random access memory |
US6256249B1 (en) * | 1999-12-30 | 2001-07-03 | Cypress Semiconductor Corp. | Method for hidden DRAM refresh |
KR20040003924A (ko) * | 2002-07-04 | 2004-01-13 | 조강균 | 고분자 유기화합물 식물발효를 이용한 야채재배방법과해저저온 발효방법을 이용한 발효김치 제조방법 |
US7596050B2 (en) * | 2006-07-31 | 2009-09-29 | Sandisk 3D Llc | Method for using a hierarchical bit line bias bus for block selectable memory array |
US7570523B2 (en) | 2006-07-31 | 2009-08-04 | Sandisk 3D Llc | Method for using two data busses for memory array block selection |
US7463536B2 (en) * | 2006-07-31 | 2008-12-09 | Sandisk 3D Llc | Memory array incorporating two data busses for memory array block selection |
US8279704B2 (en) * | 2006-07-31 | 2012-10-02 | Sandisk 3D Llc | Decoder circuitry providing forward and reverse modes of memory array operation and method for biasing same |
JP5279139B2 (ja) * | 2006-07-31 | 2013-09-04 | サンディスク・スリー・ディ・リミテッド・ライアビリティ・カンパニー | メモリアレイブロック選択のための2本のデータバスを組込んだメモリアレイのための方法および装置 |
US7633828B2 (en) * | 2006-07-31 | 2009-12-15 | Sandisk 3D Llc | Hierarchical bit line bias bus for block selectable memory array |
US7499366B2 (en) | 2006-07-31 | 2009-03-03 | Sandisk 3D Llc | Method for using dual data-dependent busses for coupling read/write circuits to a memory array |
JP2010509704A (ja) | 2006-11-14 | 2010-03-25 | ラムバス・インコーポレーテッド | 低エネルギーメモリコンポーネント |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4222112A (en) * | 1979-02-09 | 1980-09-09 | Bell Telephone Laboratories, Incorporated | Dynamic RAM organization for reducing peak current |
US4494222A (en) * | 1980-03-28 | 1985-01-15 | Texas Instruments Incorporated | Processor system using on-chip refresh address generator for dynamic memory |
JPS5785255A (en) * | 1980-11-17 | 1982-05-27 | Nec Corp | Memory storage for integrated circuit |
JPS58147884A (ja) * | 1982-02-26 | 1983-09-02 | Toshiba Corp | ダイナミック型半導体記憶装置 |
JPS58155597A (ja) * | 1982-03-10 | 1983-09-16 | Hitachi Ltd | 半導体メモリの書き込み制御方式 |
JPH0787034B2 (ja) * | 1984-05-07 | 1995-09-20 | 株式会社日立製作所 | 半導体集積回路装置 |
DE3582376D1 (de) * | 1984-08-03 | 1991-05-08 | Toshiba Kawasaki Kk | Halbleiterspeicheranordnung. |
JPS6168797A (ja) * | 1984-09-11 | 1986-04-09 | Nec Corp | ダイナミックメモリ回路 |
JPH0793009B2 (ja) * | 1984-12-13 | 1995-10-09 | 株式会社東芝 | 半導体記憶装置 |
JPH0778993B2 (ja) * | 1985-11-05 | 1995-08-23 | 株式会社日立製作所 | 半導体メモリ |
JPH0642313B2 (ja) * | 1985-12-20 | 1994-06-01 | 日本電気株式会社 | 半導体メモリ |
-
1988
- 1988-06-03 EP EP88108948A patent/EP0293933B1/de not_active Expired - Lifetime
- 1988-06-03 JP JP63137734A patent/JPH0793002B2/ja not_active Expired - Fee Related
- 1988-06-03 DE DE88108948T patent/DE3884859T2/de not_active Expired - Fee Related
- 1988-06-04 KR KR1019880006712A patent/KR910009550B1/ko not_active IP Right Cessation
- 1988-06-06 US US07/202,847 patent/US4879692A/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
EP0293933A2 (de) | 1988-12-07 |
JPH0793002B2 (ja) | 1995-10-09 |
EP0293933A3 (de) | 1991-02-06 |
US4879692A (en) | 1989-11-07 |
JPH0198193A (ja) | 1989-04-17 |
DE3884859T2 (de) | 1994-02-03 |
EP0293933B1 (de) | 1993-10-13 |
KR890001090A (ko) | 1989-03-18 |
KR910009550B1 (ko) | 1991-11-21 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
DE3884859D1 (de) | Dynamische Speicherschaltung mit einem Abfühlschema. | |
DE3580566D1 (de) | Verzahnter teilassoziativspeicher. | |
DE3867964D1 (de) | Speicherchip mit pipelinewirkung. | |
DE3885651T2 (de) | Kondensator mit niedriger Eigeninduktivität. | |
DE3771288D1 (de) | Dynamischer speicher mit wahlfreiem zugriff. | |
DE3883865T2 (de) | Halbleiterspeicheranordnung mit einem Register. | |
DE3885594T2 (de) | Speicherprüfgerät. | |
DE3854037D1 (de) | Speicheraddressierungsfehlererkennung. | |
DE3779705T2 (de) | Integrierte speicherschaltung mit blockadressierung. | |
DE3586840T2 (de) | Speichersystem mit integriertem schaltkreis. | |
DE3869158D1 (de) | Speicher-leseschaltung. | |
DE3887284D1 (de) | Halbleiterspeicherschaltung mit einem verbesserten Rückschreibschema. | |
DE3776049D1 (de) | Elektronische gedaechtnisstuetze. | |
DE3677150D1 (de) | Dynamischer speicher mit erhoehter datengueltigkeitszeitdauer. | |
DE3581596D1 (de) | Festwertspeicherschaltung. | |
DE68928839T2 (de) | System mit einem synchronen DRAM-Speicher | |
DE3883935T2 (de) | Halbleiterspeicheranordnung mit einem seriellen Zugriffsspeicher. | |
DE3750175D1 (de) | Mikroprozessor mit einem Cache-Speicher. | |
DE3685576D1 (de) | Halbleiterspeicheranordnung mit seriellem adressierungsschema. | |
DE3680728D1 (de) | Halbleiterspeicherschaltung mit einem vorspannungsgenerator. | |
DE68920118D1 (de) | Josephson-Speicherschaltung. | |
DE69021273T2 (de) | Integrierte Speicherschaltung mit einem Leseverstärker. | |
DE3381064D1 (de) | Pufferspeicher mit einem swappingschaltkreis. | |
DE68925616D1 (de) | Adressenübergangsabfühlschaltung | |
DE69014189T2 (de) | Speicher mit verbesserter Lesezeit. |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8339 | Ceased/non-payment of the annual fee |