DE3580566D1 - Verzahnter teilassoziativspeicher. - Google Patents

Verzahnter teilassoziativspeicher.

Info

Publication number
DE3580566D1
DE3580566D1 DE8585901854T DE3580566T DE3580566D1 DE 3580566 D1 DE3580566 D1 DE 3580566D1 DE 8585901854 T DE8585901854 T DE 8585901854T DE 3580566 T DE3580566 T DE 3580566T DE 3580566 D1 DE3580566 D1 DE 3580566D1
Authority
DE
Germany
Prior art keywords
interlocked
associative memory
partial
partial associative
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE8585901854T
Other languages
English (en)
Inventor
Michael Patrick
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
AT&T Corp
Original Assignee
American Telephone and Telegraph Co Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by American Telephone and Telegraph Co Inc filed Critical American Telephone and Telegraph Co Inc
Application granted granted Critical
Publication of DE3580566D1 publication Critical patent/DE3580566D1/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
    • G06F12/0846—Cache with multiple tag or data arrays being simultaneously accessible
    • G06F12/0851—Cache with interleaved addressing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0864—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using pseudo-associative means, e.g. set-associative or hashing

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
DE8585901854T 1984-04-11 1985-03-29 Verzahnter teilassoziativspeicher. Expired - Fee Related DE3580566D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US06/599,644 US4736293A (en) 1984-04-11 1984-04-11 Interleaved set-associative memory
PCT/US1985/000539 WO1985004737A1 (en) 1984-04-11 1985-03-29 Interleaved set-associative memory

Publications (1)

Publication Number Publication Date
DE3580566D1 true DE3580566D1 (de) 1990-12-20

Family

ID=24400473

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8585901854T Expired - Fee Related DE3580566D1 (de) 1984-04-11 1985-03-29 Verzahnter teilassoziativspeicher.

Country Status (5)

Country Link
US (1) US4736293A (de)
EP (1) EP0179811B1 (de)
CA (1) CA1223974A (de)
DE (1) DE3580566D1 (de)
WO (1) WO1985004737A1 (de)

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US5276850A (en) * 1988-12-27 1994-01-04 Kabushiki Kaisha Toshiba Information processing apparatus with cache memory and a processor which generates a data block address and a plurality of data subblock addresses simultaneously
JPH077355B2 (ja) * 1988-12-27 1995-01-30 株式会社東芝 情報処理装置
US5019965A (en) * 1989-02-03 1991-05-28 Digital Equipment Corporation Method and apparatus for increasing the data storage rate of a computer system having a predefined data path width
US5073950A (en) * 1989-04-13 1991-12-17 Personnel Identification & Entry Access Control, Inc. Finger profile identification system
US5091851A (en) * 1989-07-19 1992-02-25 Hewlett-Packard Company Fast multiple-word accesses from a multi-way set-associative cache memory
US5307477A (en) * 1989-12-01 1994-04-26 Mips Computer Systems, Inc. Two-level cache memory system
US5014195A (en) * 1990-05-10 1991-05-07 Digital Equipment Corporation, Inc. Configurable set associative cache with decoded data element enable lines
DE69128107T2 (de) * 1990-05-25 1998-02-26 At & T Corp Busanordnung für Speicherzugriff
ATE170642T1 (de) * 1990-06-15 1998-09-15 Compaq Computer Corp Mehrstufeneinschluss in mehrstufigen cache- speicherhierarchien
US5235697A (en) * 1990-06-29 1993-08-10 Digital Equipment Set prediction cache memory system using bits of the main memory address
US5434990A (en) * 1990-08-06 1995-07-18 Ncr Corporation Method for serially or concurrently addressing n individually addressable memories each having an address latch and data latch
JP2646854B2 (ja) * 1990-12-18 1997-08-27 三菱電機株式会社 マイクロプロセッサ
US5341485A (en) * 1991-05-07 1994-08-23 International Business Machines Corporation Multiple virtual address translation per computer cycle
US5428758A (en) * 1991-05-10 1995-06-27 Unisys Corporation Method and system for remapping memory from one physical configuration to another physical configuration
US5325504A (en) * 1991-08-30 1994-06-28 Compaq Computer Corporation Method and apparatus for incorporating cache line replacement and cache write policy information into tag directories in a cache system
US5367659A (en) * 1991-09-30 1994-11-22 Intel Corporation Tag initialization in a controller for two-way set associative cache
US5367653A (en) * 1991-12-26 1994-11-22 International Business Machines Corporation Reconfigurable multi-way associative cache memory
JP2839060B2 (ja) * 1992-03-02 1998-12-16 インターナショナル・ビジネス・マシーンズ・コーポレイション データ処理システムおよびデータ処理方法
JPH06131244A (ja) * 1992-10-20 1994-05-13 Fujitsu Ltd 共有メモリの非同期アクセス方式
US5430857A (en) * 1993-01-04 1995-07-04 Intel Corporation Method and apparatus for translating logical addresses into physical addresses using odd/even translation tables
US5689680A (en) * 1993-07-15 1997-11-18 Unisys Corp. Cache memory system and method for accessing a coincident cache with a bit-sliced architecture
US5553259A (en) * 1993-07-16 1996-09-03 Unisys Corporation Apparatus and method for synchronizing the simultaneous loading of cache program word addresses in dual slice registers
US5581734A (en) * 1993-08-02 1996-12-03 International Business Machines Corporation Multiprocessor system with shared cache and data input/output circuitry for transferring data amount greater than system bus capacity
US5905997A (en) * 1994-04-29 1999-05-18 Amd Inc. Set-associative cache memory utilizing a single bank of physical memory
EP0803095A1 (de) * 1994-10-14 1997-10-29 Silicon Graphics, Inc. Indexierung und mulitplizierung von verschachtelten cache-speichermatrixen
US5897662A (en) * 1995-08-18 1999-04-27 International Business Machines Corporation Pseudo-random address generation mechanism that reduces address translation time
US5701432A (en) * 1995-10-13 1997-12-23 Sun Microsystems, Inc. Multi-threaded processing system having a cache that is commonly accessible to each thread
US6212601B1 (en) * 1996-08-30 2001-04-03 Texas Instruments Incorporated Microprocessor system with block move circuit disposed between cache circuits
US5815107A (en) * 1996-12-19 1998-09-29 International Business Machines Corporation Current source referenced high speed analog to digitial converter
US5923276A (en) * 1996-12-19 1999-07-13 International Business Machines Corporation Current source based multilevel bus driver and converter
GB2325321B (en) * 1997-05-12 2001-06-06 Applied Marketing & Technology Associative memories
US6256709B1 (en) * 1997-06-26 2001-07-03 Sun Microsystems, Inc. Method for storing data in two-way set associative odd and even banks of a cache memory
US6101561A (en) * 1998-02-06 2000-08-08 International Business Machines Corporation System for providing an increase in digital data transmission rate over a parallel bus by converting binary format voltages to encoded analog format currents
US6112319A (en) * 1998-02-20 2000-08-29 Micron Electronics, Inc. Method and system for verifying the accuracy of stored data
US6237086B1 (en) 1998-04-22 2001-05-22 Sun Microsystems, Inc. 1 Method to prevent pipeline stalls in superscalar stack based computing systems
US6275903B1 (en) 1998-04-22 2001-08-14 Sun Microsystems, Inc. Stack cache miss handling
US6170050B1 (en) 1998-04-22 2001-01-02 Sun Microsystems, Inc. Length decoder for variable length data
US6108768A (en) * 1998-04-22 2000-08-22 Sun Microsystems, Inc. Reissue logic for individually reissuing instructions trapped in a multiissue stack based computing system
US6233655B1 (en) * 1998-04-30 2001-05-15 International Business Machines Corporation Method for Quad-word Storing into 2-way interleaved L1 cache
US6173367B1 (en) * 1999-05-19 2001-01-09 Ati Technologies, Inc. Method and apparatus for accessing graphics cache memory
JP3620473B2 (ja) * 2001-06-14 2005-02-16 日本電気株式会社 共有キャッシュメモリのリプレイスメント制御方法及びその装置
US20040199723A1 (en) * 2003-04-03 2004-10-07 Shelor Charles F. Low-power cache and method for operating same
JP4810542B2 (ja) * 2005-12-28 2011-11-09 富士通株式会社 メモリ制御方法、プログラム及び装置

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US3967247A (en) * 1974-11-11 1976-06-29 Sperry Rand Corporation Storage interface unit
US4056845A (en) * 1975-04-25 1977-11-01 Data General Corporation Memory access technique
US4195340A (en) * 1977-12-22 1980-03-25 Honeywell Information Systems Inc. First in first out activity queue for a cache store
US4195342A (en) * 1977-12-22 1980-03-25 Honeywell Information Systems Inc. Multi-configurable cache store system
US4208716A (en) * 1978-12-11 1980-06-17 Honeywell Information Systems Inc. Cache arrangement for performing simultaneous read/write operations
US4317168A (en) * 1979-11-23 1982-02-23 International Business Machines Corporation Cache organization enabling concurrent line castout and line fetch transfers with main storage
US4315312A (en) * 1979-12-19 1982-02-09 Ncr Corporation Cache memory having a variable data block size
US4371928A (en) * 1980-04-15 1983-02-01 Honeywell Information Systems Inc. Interface for controlling information transfers between main data processing systems units and a central subsystem
US4371929A (en) * 1980-05-05 1983-02-01 Ibm Corporation Multiprocessor system with high density memory set architecture including partitionable cache store interface to shared disk drive memory
US4381541A (en) * 1980-08-28 1983-04-26 Sperry Corporation Buffer memory referencing system for two data words
US4392201A (en) * 1980-12-31 1983-07-05 Honeywell Information Systems Inc. Diagnostic subsystem for a cache memory
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US4439829A (en) * 1981-01-07 1984-03-27 Wang Laboratories, Inc. Data processing machine with improved cache memory management
US4525780A (en) * 1981-05-22 1985-06-25 Data General Corporation Data processing system having a memory using object-based information and a protection scheme for determining access rights to such information
US4493026A (en) * 1982-05-26 1985-01-08 International Business Machines Corporation Set associative sector cache

Also Published As

Publication number Publication date
CA1223974A (en) 1987-07-07
EP0179811B1 (de) 1990-11-14
US4736293A (en) 1988-04-05
WO1985004737A1 (en) 1985-10-24
EP0179811A1 (de) 1986-05-07

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8328 Change in the person/name/address of the agent

Free format text: BLUMBACH, KRAMER & PARTNER, 65193 WIESBADEN

8339 Ceased/non-payment of the annual fee