DE3685576D1 - Halbleiterspeicheranordnung mit seriellem adressierungsschema. - Google Patents
Halbleiterspeicheranordnung mit seriellem adressierungsschema.Info
- Publication number
- DE3685576D1 DE3685576D1 DE8686117730T DE3685576T DE3685576D1 DE 3685576 D1 DE3685576 D1 DE 3685576D1 DE 8686117730 T DE8686117730 T DE 8686117730T DE 3685576 T DE3685576 T DE 3685576T DE 3685576 D1 DE3685576 D1 DE 3685576D1
- Authority
- DE
- Germany
- Prior art keywords
- semiconductor memory
- addressing scheme
- memory arrangement
- serial addressing
- serial
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 title 1
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
- G11C7/103—Read-write modes for single port memories, i.e. having either a random port or a serial port using serially addressed read-write data registers
Landscapes
- Engineering & Computer Science (AREA)
- Databases & Information Systems (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Dram (AREA)
- Static Random-Access Memory (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP60288729A JPH0642313B2 (ja) | 1985-12-20 | 1985-12-20 | 半導体メモリ |
Publications (2)
Publication Number | Publication Date |
---|---|
DE3685576D1 true DE3685576D1 (de) | 1992-07-09 |
DE3685576T2 DE3685576T2 (de) | 1993-01-07 |
Family
ID=17733928
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE8686117730T Expired - Lifetime DE3685576T2 (de) | 1985-12-20 | 1986-12-19 | Halbleiterspeicheranordnung mit seriellem adressierungsschema. |
Country Status (4)
Country | Link |
---|---|
US (1) | US4802134A (de) |
EP (1) | EP0233363B1 (de) |
JP (1) | JPH0642313B2 (de) |
DE (1) | DE3685576T2 (de) |
Families Citing this family (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5222047A (en) * | 1987-05-15 | 1993-06-22 | Mitsubishi Denki Kabushiki Kaisha | Method and apparatus for driving word line in block access memory |
JPH0793002B2 (ja) * | 1987-06-04 | 1995-10-09 | 日本電気株式会社 | メモリ集積回路 |
JPS6468851A (en) * | 1987-09-09 | 1989-03-14 | Nippon Electric Ic Microcomput | Semiconductor integrated circuit |
US5280448A (en) * | 1987-11-18 | 1994-01-18 | Sony Corporation | Dynamic memory with group bit lines and associated bit line group selector |
FR2667688B1 (fr) * | 1990-10-05 | 1994-04-29 | Commissariat Energie Atomique | Circuit d'acquisition ultrarapide. |
US5526316A (en) * | 1994-04-29 | 1996-06-11 | Winbond Electronics Corp. | Serial access memory device |
US5694546A (en) * | 1994-05-31 | 1997-12-02 | Reisman; Richard R. | System for automatic unattended electronic information transport between a server and a client by a vendor provided transport software with a manifest list |
JPH08153387A (ja) * | 1994-11-30 | 1996-06-11 | Mitsubishi Electric Corp | Fifoメモリ |
US6167486A (en) | 1996-11-18 | 2000-12-26 | Nec Electronics, Inc. | Parallel access virtual channel memory system with cacheable channels |
DE59810778D1 (de) | 1997-09-18 | 2004-03-25 | Infineon Technologies Ag | Anordnung mit einem Umlaufspeicher und mit eine Einrichtung, welche ein auf den Umlaufspeicher zugreifendes Programm ausführt |
US6034921A (en) * | 1997-11-26 | 2000-03-07 | Motorola, Inc. | Method, apparatus, pager, and cellular telephone for accessing information from a memory unit utilizing a sequential select unit |
US6708254B2 (en) | 1999-11-10 | 2004-03-16 | Nec Electronics America, Inc. | Parallel access virtual channel memory system |
KR101095736B1 (ko) * | 2010-06-24 | 2011-12-21 | 주식회사 하이닉스반도체 | 비휘발성 메모리 장치 |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4141081A (en) * | 1978-01-03 | 1979-02-20 | Sperry Rand Corporation | MNOS BORAM sense amplifier/latch |
US4330852A (en) * | 1979-11-23 | 1982-05-18 | Texas Instruments Incorporated | Semiconductor read/write memory array having serial access |
US4498155A (en) * | 1979-11-23 | 1985-02-05 | Texas Instruments Incorporated | Semiconductor integrated circuit memory device with both serial and random access arrays |
JPS5727477A (en) * | 1980-07-23 | 1982-02-13 | Nec Corp | Memory circuit |
JPS57117168A (en) * | 1981-01-08 | 1982-07-21 | Nec Corp | Memory circuit |
US4412313A (en) * | 1981-01-19 | 1983-10-25 | Bell Telephone Laboratories, Incorporated | Random access memory system having high-speed serial data paths |
JPS6054471A (ja) * | 1983-09-05 | 1985-03-28 | Hitachi Ltd | 半導体メモリ |
JPS5862893A (ja) * | 1981-10-09 | 1983-04-14 | Mitsubishi Electric Corp | Mosダイナミツクメモリ |
US4611299A (en) * | 1982-02-22 | 1986-09-09 | Hitachi, Ltd. | Monolithic storage device |
JPH0670880B2 (ja) * | 1983-01-21 | 1994-09-07 | 株式会社日立マイコンシステム | 半導体記憶装置 |
JPS6072020A (ja) * | 1983-09-29 | 1985-04-24 | Nec Corp | デュアルポ−トメモリ回路 |
US4688197A (en) * | 1983-12-30 | 1987-08-18 | Texas Instruments Incorporated | Control of data access to memory for improved video system |
US4667313A (en) * | 1985-01-22 | 1987-05-19 | Texas Instruments Incorporated | Serially accessed semiconductor memory with tapped shift register |
-
1985
- 1985-12-20 JP JP60288729A patent/JPH0642313B2/ja not_active Expired - Lifetime
-
1986
- 1986-12-19 EP EP86117730A patent/EP0233363B1/de not_active Expired - Lifetime
- 1986-12-19 DE DE8686117730T patent/DE3685576T2/de not_active Expired - Lifetime
- 1986-12-22 US US06/944,115 patent/US4802134A/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
JPS62146481A (ja) | 1987-06-30 |
EP0233363B1 (de) | 1992-06-03 |
EP0233363A3 (en) | 1988-06-08 |
US4802134A (en) | 1989-01-31 |
EP0233363A2 (de) | 1987-08-26 |
JPH0642313B2 (ja) | 1994-06-01 |
DE3685576T2 (de) | 1993-01-07 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8327 | Change in the person/name/address of the patent owner |
Owner name: NEC ELECTRONICS CORP., KAWASAKI, KANAGAWA, JP |