CN1977375A - 堆叠模块系统和方法 - Google Patents

堆叠模块系统和方法 Download PDF

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CN1977375A
CN1977375A CNA200580021591XA CN200580021591A CN1977375A CN 1977375 A CN1977375 A CN 1977375A CN A200580021591X A CNA200580021591X A CN A200580021591XA CN 200580021591 A CN200580021591 A CN 200580021591A CN 1977375 A CN1977375 A CN 1977375A
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csp
standard component
circuit
shaping standard
flex circuit
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茱利安·帕特里奇
道格拉斯·小韦尔利
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Entorian Technologies Inc
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Abstract

本发明涉及将芯片级封装的集成电路(CSP)堆叠成模块，它们节省PWB或其它电路板表面积。在根据发明的优选实施例中，与一个或多个CSP相关联的成形标准件提供了这样的实体形状，其有利地使用在宽广族的CSP封装中建立的多个不同的封装尺寸，而同时采用标准连接柔性电路结构。在优选实施例中，较低CSP的触头在柔性电路结构附着至所述CSP与成形标准件的组合件之前将被压缩，以在所述CSP与所述柔性电路结构之间形成较低外形的触头。

Description

堆叠模块系统和方法
技术领域
本发明涉及集合集成电路，更具体地讲涉及在芯片级封装中堆叠集成电路。
背景技术
很多种技术被用来堆叠封装好的集成电路。有些方法需要特殊的封装，而其它技术堆叠传统封装。
在已经过去的时间中使用的最主要的封装结构已经将集成电路(IC)包封在大体具有矩形结构的塑料封体中。所包封的集成电路通过从塑料封体的周缘伸出的引线与应用环境相连。这种“引线封装”已经是用于堆叠封装好的集成电路的技术中最常用的组成因素了。
引线封装在电子学中起着很重要的作用，但使电子零件和组件最小化的努力已经推动了保持电路板表面积技术的发展。因为引线封装结构具有从封装的外周侧部伸出的引线，所以引线封装占用的面积大于电路板表面积的最小量。因此，引线封装结构的替代品也就是公知的芯片级封装或“CSP”近来已经占有了一定的市场份额。
CSP大致是指通过横跨封装体的主体表面布置的一组触头(通常为“凸缘”或“球”)提供与集成电路的连接。不同于从封装体的外周侧部伸出的引线，触头设置在主体表面上，并且大体从封装体的平坦底面伸出。封装体侧部上的“引线”缺失弥补了多数专门设计用于引线封装而不适于CSP堆叠的堆叠技术。
用于堆叠CSP的以前的多种技术通常具有复杂的结构布局和热学或高频性能问题。例如，热学性能是CSP堆叠中的一个很重要的特征。
因此，现在需要的是一种用于堆叠CSP的技术和系统，其能够提供高热效率、可靠的结构，能够在高频下工作良好，但又不给堆叠体增加额外高度，而允许利用容易理解且管理的材料和方法以合理的成本进行生产。
发明内容
本发明涉及将芯片级封装的集成电路(CSP)堆叠成模块，它们节省PWB或其它电路板表面积。虽然本发明通常更多地被用于包含一个芯片的芯片级封装中，但它可以用于包括不止一个的集成电路芯片的芯片级封装中。根据本发明，更多数量的CSP可以被堆叠。根据本发明构造的堆叠模块中所采用的CSP与柔性电路结构相连。这种柔性电路结构可具有一个或两个或更多个导电层。
在本发明中，至少一个成形标准件被用于提供这样的实体形状，其有利地使用在宽广族的CSP封装中建立的多个不同的封装尺寸，而同时采用标准连接柔性电路结构。在优选实施例中，成形标准件将由传导热的材料构成，以改进散热性能，例如，诸如铜的金属将是优选的。
在根据本发明的一些优选方式的模块构造过程中，CSP的触头高度被减小以形成低外形的模块。利用本发明的一些优选方法，受压缩的触头与锡膏混和，并有利地设定为较小直径的触头。这形成了本发明的模块的低外形的实施例。
附图说明
图1为根据本发明的优选双高实施例构造的高密度电路模块的正视图。
图2以放大视图的方式示出了图1中被标记为“A”的区域。
图3A示出了结合进入本发明的模块或单元之前的示例CSP的一部分。
图3B示出了示例CSP的一部分，这是在其触头中的一个的高度已经根据本发明的优选方式被减小后的情况。
图4示出了优选构造方法，其可被用于制造根据本发明优选实施例而构造的高密度模块。
图5示出了优选构造方法，其可被用于制造根据本发明优选实施例而构造的高密度模块。
图6示出了可以被用于根据本发明的优选实施例构造的模块中的单元。
具体实施方式
图1示出了根据本发明的优选实施例构造的双高模块10。图1具有标记为“A”的区域，其随后在图2中以放大方式示出。模块10包括两个CSP：CSP 16和CSP 18。每个CSP具有上侧表面20和下侧表面22以及相反的横向边缘24和26，并大体包括被塑料本体27包围的至少一个集成电路。所述本体不必为塑料，但是CSP技术中大多数封装体都是塑料。本领域技术人员清楚，本发明可被用于形成具有不同尺寸CSP的模块，并且组成的CSP在同一模块10内可具有不同的类型。例如，组成的CSP中的其中一个可以是具有横向边缘24和26的典型的CSP，其中边缘24和26具有可测量的高度以提供“侧部”，而同一模块10内的其它组成CSP可以被构造在具有横向边缘24和26的封装体内，其中所述横向边缘24和26的主要特征在于边缘，而不是具有可测量的高度的侧部。
在本申请的上下文中，术语CSP应被广义理解。共同地，这些在此处被理解为芯片级封装的集成电路(CSP)，并且优选实施例将针对CSP被说明，但是，在示意性附图中所使用的特定结构不应被认为是限制。例如，正视图示出了本领域技术人员公知具体形式的CSP，但是应该理解的是，这些附图仅仅是示意性的。本发明可有利地应用于可用在本技术领域内的广阔范围的CSP结构，其中一组连接元件可来自至少一个主体表面。本发明可有利地应用于包含存储电路的CSP，但有利地应用于逻辑和计算电路，其中期望增加容量，而不用相当的PWB或其它板表面积消耗。
典型的CSP，例如，球栅阵列封装(“BGA”)、微型球栅阵列封装、和细间距球栅阵列封装(“FBGA”)具有一组连接触头，例如它们具体为引线、凸缘、锡球(焊球)、或球体，它们以多种图案和间距中的任一一种的方式从塑料壳体的下侧表面22伸出。连接触头的外部通常设有锡球。图1示出了为沿所示组成的CSP 16和18的下侧表面22的触头28。触头28在相应的封装体内提供对于集成电路或电路的连接。
在图1中，柔性电路结构(“柔板”，“柔性电路”或“柔性电路结构体”)被示出连接组成的CSP 16和18。单个柔性电路结构可以被用于两个所示的柔性电路30和32所在的适当位置内。柔性电路结构的整体可以是柔性的或，如本领域技术人员将清楚的那样，这样一种PCB结构可被用作为本发明中的可选的柔性电路结构，其中所述PCB结构在特定区域内被制成柔性以允许围绕CSP的一致性并且在其它区域内被制成刚硬以便沿CSP表面的平坦性。例如，可采用公知为软硬板的结构。
第一成形标准件34被示出与CSP 18的上侧表面20相邻安置。还示出了与CSP 16相关的第二成形标准件。成形标准件34可以通过优选具有热传导性的粘合剂36被固定至相应的CSP的上侧表面20。在可选实施例中，成形标准件34还可以仅仅安放在上侧表面20上或通过空气间隙或诸如散热片或非热层的介质与上侧表面20分隔开。成形标准件可以被用于模块10中的每个CSP上，以改进散热性，如图1所示，其是本发明的优选实施方式，其中高优先级散热。在其它实施例中，成形标准件34可以相对于对应的CSP被颠倒，这样，例如，所述成形标准件可以在CSP 18的上侧表面20上方开口。
在优选实施例中，成形标准件34是由铜构成，如图1中的优选实施例所示，以形成模芯(mandrel)，其减轻热量积聚，同时提供柔性电路结构绕其安置的标准尺寸的成形结构。在优选实施例中，成形标准件34还可以由镀镍铜构成。成形标准件34还可以采取其它形状和形式，例如，斜角“盖”，其坐靠在对应的CSP本体上。无需改进散热，尽管这种品质是优选的。成形标准件34允许本发明用于不同尺寸的CSP，同时连接单独一组这样的连接结构，它们可与不同尺寸的CSP一起使用。这样，单独一组连接结构，例如柔性电路30和32(或者单个柔性电路，在这种情况中，单个柔板被用于如图5所示柔性电路对30和32所在的部位)通过在此所公开的方法和/或系统被构造并与所述成形标准件34一起使用，以用具有不同尺寸封装的CSP形成堆叠的模块。允许同一柔性电路结构的设定结构被用于从具有横贯特征Y(其中，例如Y可以是封装宽度)的第一任意尺寸X的组成的CSP反复形成堆叠的模块10，并通过具有横贯同一特征Y的第二任意尺寸X的组成的CSP反复形成模块10。这样，不同尺寸的CSP可以用同一组连接结构(也就是柔性电路结构)堆叠到模块10中。此外，本领域技术人员将会明白，混和尺寸的CSP可应用到同一模块10中，这例如对于堆叠系统的实施例是有用的，如2003年9月15日提交的未决专利申请PCT/US03/29000中所公开的那样，其中所述专利申请结合在此引作参考，并且由本发明申请的受让人拥有。
在一个优选实施例中，柔性电路30和32的对应部分通过结合部35被固定，以产生成形标准件34，其中在一些优选实施例中，所述结合部35是通过将诸如锡的第一金属层安置在成形标准件34上而被形成的冶金结合部，例如所述第一金属层在被熔化时与安置在所述柔性电路结构上或者为所述柔性电路结构的一部分的第二金属结合在一起，从而形成高熔点的金属间的结合部，其中所述高熔点的金属间的结合部在随后的回流操作的过程中将不熔化，如以下所述。
图2以放大视图的方式示出了图1中标记为“A”的区域。图2以优选实施例的方式示出了双高模块10中成形标准件34和其相对于柔性电路结构32关系的结构，其中将成形标准件34应用于每个CSP 16和18。柔性电路结构32的内层结构没有在该图中示出。与图1相比，更加详细地示出了结合部35，其参看后图将被说明。图2中还示出了成形标准件34与CSP 18和16之间的粘合剂36的应用。在优选实施例中，粘合剂33还可应用于同CSP 16相关的成形标准件34与柔性电路结构32之间。粘合剂33优选为导热粘合剂。
尽管本领域技术人员清楚附图不成比例，但是CSP 16和18的触头28已经示出(尽管在每个实施例中无需示出)具有位于相应的CSP的下侧表面22之上的限制高度。图3A示出了CSP 18的触头28，其中为所述触头28经受随后将详细说明的高度减小步骤之前的情况。如图所示，触头28在CSP 18的表面22之上升高了高度Dx。图3B示出了触头28，其中为随后将详细说明的高度减小步骤之后的情况。在图3B中，在将成形标准件34附着至CSP18之前完成高度减小。如后所述，可在将成形标准件34附着至CSP 18之前或之后出现触头28的高度减小。如图所示，触头28在CSP 18的表面22之上升高了高度Dc。参看图2，在某些实施例中，在CSP 18结合进入模块10或如后所示的单元39(图6)中之后，触头28可在所述表面22之上升高高度D1。高度D1大于高度Dc，这样，在完成触头高度被减小的步骤之后，但在完成如图3B、图4和图5中所示的柔性电路结构的附着之前，触头显现出来了。即使这样，在优选实施例中，触头28的高度D1，在CSP 18结合进入模块10(例如图2中所示)或单元39(例如图6中所示)中之后，小于高度Dx，其中Dx为，在CSP 18结合进入单元39(图6中所示)或模块10中的任一个之前、以及在根据本发明的优选模式触头高度减小之前，由CSP触头28所体现的表面22之上的高度。如图2所示，模块触头38从柔性电路结构32升高了高度Dm，并且，在模块10的优选实施例中，D1小于Dm。
参看图4，组合件37被示出包括附着至CSP 18的成形标准件34，其中所述CSP 18在被附着至柔性电路结构时，适于应用于模块10中。可以通过由附图标记36所表示的粘合剂实现成形标准件34附着至CSP 18，其中粘合剂36优选为薄膜粘合剂，其可通过热粘结的方式被施加至成形标准件34或CSP 18。很多其它方法可以被用来将成形标准件34粘接到CSP 18上，并且在一些实施例中，可以不使用粘合剂。
如图4进一步所示，通过以下方式，制备柔性电路30和32以便附着至组合件37，将焊膏41施加至对应于将连接至柔性电路结构的CSP 18的触头28的部位。图中还示出了由附图标记43所示的胶合剂的应用，其中当胶合剂被应用成将成形标准件34附着至柔性电路结构时，所述胶合剂43优选为液胶。
如该实施例中所示出的，CSP 18的触头28的高度Dc小于前面图2中示出的高度D1。在组合件37附着至柔性电路结构之前，CSP 18的所示的触头28通过压缩或其他高度减小的方式减小高度。这种压缩可以在成形标准件34与CSP 18的附着之前或之后完成，优选附着之后进行压缩。触头28可以在固体或半固体状态时被减小高度。在模块10的形成过程中，如果不是高度减小，则CSP 18上的触头28将“坐落”在焊膏41所在的位置上。这导致了柔性电路结构与成形标准件34之间的胶合线比期望的厚。胶合剂延展成填充柔性电路结构与成形标准件34之间的缝隙，其是由于通过触头28“坐落”于焊膏41所在的位置上而在所述附着的成形标准件34与所述柔性电路结构之间的距离造成的。
由于柔性电路结构与成形标准件34之间的较厚的胶合线，在回流后，触头28内的焊剂与焊膏41混和，并延展成横跨CSP 18与柔性电路结构之间的空间，而此时柔性电路结构与CSP 18之间是固定的距离。这导致了触头28的竖直尺寸比需要的更大，这是由于较高的胶合线，以及因此具有较高外形的模块10。较高的胶合线通过以下方式形成，在将柔性电路结构附着至成形标准件34(或者组合件37的成形标准件部分)之前没有减小触头的直径。但是，利用本发明的优选方法，在回流后，受压缩的触头28与焊膏41混和，并且有利地设定较小直径的触头28。组合件37与柔性电路结构组合得到的单元然后可被应用于形成模块10的低外形实施例。
图5示出了优选可替换的和附加的实施例，以减小模块10高度，同时在成形标准件34与柔性电路结构之间提供稳定结合部35。通过以下方法形成图1中之前所示的优选结合部35。如图5所示，由附图标记47所示的第一金属材料层叠、附加或电镀至成形标准件34。例如通过将薄金属层施加至柔性电路结构30，或者通过暴露柔性电路结构的导电层的相应部分，设置位于柔性电路结构30上由附图标记49所示的第二金属材料。在成形标准件34接近柔性电路结构时，并且局部加热第一和第二金属47和49相邻的区域时，形成金属间结合部35。优选金属材料47可以是薄锡层，其被应用成形成大约0.0005″厚的层。在被熔化以与例如在相应部位所暴露的柔性电路结构的导电层的金结合时，产生的金属间结合部35将具有更高的融点，导致具有这样的优点，即在随后以特定温度进行回流操作的过程中，不会再熔化。
各种不同的方法可以被用来提供适于实现在此所述的金属结合的局部加热，包括本领域技术人员公知的的局部加热方法以及超声波焊接方法，其中柔性电路结构内的图案并不受到这种方法中的内在振动的影响，并且所述金属被选择成实现这样的结合部，其具有位于由所述超声波方法接受的范围内的熔点。
图6示出了单元39，其包括柔性电路结构31，其在所示的实施例中为单柔性电路；以及成形标准件34和CSP 18。热量所示被施加至区域50，在那里，通过使得组合件37和柔性电路结构31在一起而使得第一金属材料47和第二金属材料49接近。
金属间结合部的形成还可应用成，沿成形标准件34和柔性电路结构相邻的其它部位，例如就在该部位，或者连续沿大体胶合剂另外被施加以进一步将柔性电路结构固定至成形标准件34的成形标准件的顶侧，将组合件37结合至柔性电路结构。在此所述的金属间结合部可被单独应用或与诸如在此所述的接触压缩技术的其它方法一起使用，以形成具有低外形的模块10的实例。
在优选实施例中，柔性电路30和32是具有至少两个导电层的多层柔性电路结构。然而，其它实施例可将柔性电路结构实施为连接至一对CPS的一个电路或两个柔性电路，其仅仅具有单个导电层，并且可表现出本领域技术人员所公知的各种不同的简单构造参数，具有诸如在一侧、两侧或两侧都没有包覆涂层的特征。
优选地，导电层是诸如合金110的金属，而且如本领域技术人员所公知的那样，所述导电层通常具有镀金的导电区域。多个导电层的使用提供了优点并且形成了横贯模块10的分布电容，这将减少噪声或振动作用，它们尤其在高频时降低信号完整性，如本领域技术人员将清楚的那样。图1中的模块10具有多个模块触头38。在包括多于两个IC的模块10的实施例中，可以会发现柔性电路结构之间的连接部，大体为球，但可以是由垫和/或环构成的低外形触头，这些触头与施加至适合连接部的焊膏相连。适合的填料在所期望的部位提供附加的结构稳定性和共面性，并且取决于所述填料，可改进散热性能。
本发明已经详细的进行了介绍，很明显，对于本领域技术人员来说，本发明可以被实施为各种不同的特定形式，并且在不脱离本发明的精神和范围的前提下，可进行各种不同的改变、替换和改型。所述的实施例仅是示意性的，不具有限制性，因此本发明的范围由权利要求书表示。

Claims (31)

1.一种用于构造高密度电路模块的方法，该方法包括以下步骤：
提供具有平坦表面的第一CSP，触头从所述平坦表面伸出，每个所述触头在所述平坦表面之上升高高度H；
将成形标准件附着至第一CSP，以形成基本组合件；并且
减小每个所述触头的高度H。
2.根据权利要求1所述的方法，其特征在于，还包括以下步骤：
将所述基本组合件附着至至少一个柔性电路，以形成一单元。
3.根据权利要求2所述的方法，其特征在于，所述柔性电路包括至少一个导电层。
4.根据权利要求2所述的方法，其特征在于，所述柔性电路包括两个导电层。
5.根据权利要求1所述的方法，其特征在于，还包括以下步骤：将所述基本组合件附着至两个柔性电路上，以形成一单元。
6.根据权利要求2所述的方法，其特征在于，还包括以下步骤：
提供第二CSP；
将所述第二CSP安置于所述单元之上；并且
将所述第一和第二CSP与所述至少一个柔性电路相连。
7.根据权利要求5所述的方法，其特征在于，还包括以下步骤：
提供第二CSP；
将所述第二CSP安置于所述单元之上；并且
将所述第一和第二CSP与所述两个柔性电路相连。
8.根据权利要求1所述的方法，其特征在于，还包括以下步骤：
提供第二CSP；
将附加的成形标准件附着至所述第二CSP，以形成附加的组合件；
将柔性电路结构附着至所述基本组合件的所述成形标准件，以形成一单元；
将所述附加的组合件安置于所述单元之上；并且
将所述第一CSP和所述第二CSP与所述柔性电路结构相连。
9.根据权利要求8所述的方法，其特征在于，所述柔性电路结构包括至少一个导电层。
10.根据权利要求8所述的方法，其特征在于，所述柔性电路结构包括两个柔性电路。
11.根据权利要求10所述的方法，其特征在于，所述两个柔性电路中的每一个柔性电路包括至少一个导电层。
12.根据权利要求10所述的方法，其特征在于，所述两个柔性电路中的每一个柔性电路包括两个导电层。
13.一种用于构造高密度电路模块的方法，该方法包括以下步骤：
提供具有平坦表面的第一CSP，触头在所述平坦表面之上伸出，每个所述触头在所述平坦表面之上升高高度H；
将成形标准件附着至所述第一CSP，以形成基本组合件；
减小每个所述触头的高度H；
提供柔性电路，焊膏所在的部位设置在其上；
将所述基本组合件靠近所述柔性电路安置，以使得所述焊膏所在的部位与所述触头之间的接触区域高于所述第一CSP的所述平坦表面；
将所述组合件的所述成形标准件附着至所述柔性电路，以形成一单元；并且
选择性加热所述焊膏所在的部位与所述触头之间的接触区域，以在所述第一CSP与所述柔性电路之间形成连接部。
14.根据权利要求13所述的方法，其特征在于，还包括以下步骤：
将第二CSP安置于所述单元之上，并将所述柔性电路连接至所述第二CSP。
15.根据权利要求13或14所述的方法，其特征在于，所述柔性电路包括至少一个导电层。
16.根据权利要求13或14所述的方法，其特征在于，所述柔性电路包括两个导电层。
17.一种利用根据权利要求1所述的方法构造的高密度电路模块。
18.一种利用根据权利要求8所述的方法构造的高密度电路模块。
19.根据权利要求18所述的高密度电路模块，其特征在于，所述柔性电路结构包括两个导电层。
20.根据权利要求18所述的高密度电路模块，其特征在于，所述柔性电路结构包括两个柔性电路结构，它们每一个包括两个导电层。
21.一种高密度电路模块，包括：
具有平坦表面的第一CSP，触头从所述平坦表面伸出，所述触头从所述平坦表面升高高度H；
以堆叠的方式安置在所述第一CSP之上的第二CSP；
主要部分安置在所述第一CSP之上的第一成形标准件；
连接所述第一和第二CSP的柔性电路结构；
至少一个金属结合部，其连接所述柔性电路结构和所述第一成形标准件；以及
模块触头，所述模块触头从所述柔性电路结构延伸高度Dm，其中所述Dm大于D1。
22.根据权利要求21所述的高密度电路模块，其特征在于，还包括第二成形标准件。
23.根据权利要求22所述的高密度电路模块，其特征在于，所述柔性电路结构包括第一柔性电路和第二柔性电路，它们分别通过至少一个金属结合部附着至所述第一成形标准件。
24.根据权利要求21所述的高密度电路模块，其特征在于，所述金属结合部包括锡和金。
25.根据权利要求21所述的高密度电路模块，其特征在于，所述金属结合部通过以下方式形成，结合施加至所述第一成形标准件的第一金属材料和由所述柔性电路结构所包括的第二金属材料。
26.一种高密度电路模块，包括：
第一CSP；
堆叠在所述第一CSP之上的第二CSP；
与所述第一CSP相关联的第一成形标准件；
与所述第二CSP相关联的第二成形标准件；以及
柔性电路结构，其连接所述第一和第二CSP，所述柔性电路结构附着至所述第一成形标准件，并且包括至少两个导电层。
27.根据权利要求26所述的高密度电路模块，其特征在于，利用至少一个金属结合部，所述柔性电路结构附着至所述第一成形标准件。
28.根据权利要求27所述的高密度模块，其特征在于，所述至少一个金属结合部包括第一金属材料和第二金属材料，其中所述第一金属材料由锡构成。
29.根据权利要求27所述的高密度模块，其特征在于，所述柔性电路结构包括第一柔性电路和第二柔性电路，并且所述第一柔性电路和第二柔性电路中的每一个柔性电路利用至少一个金属结合部附着至所述第一成形标准件。
30.根据权利要求26所述的高密度模块，其特征在于，所述柔性电路结构利用粘合剂附着至所述第一成形标准件。
31.一种通过包括以下步骤的方法构造的高密度电路模块，所述方法的步骤包括：
提供成形标准件；
提供第一CSP和第二CSP；
将所述成形标准件附着至所述第一CSP；
将第一金属材料应用至所述第一成形标准件的至少一个部分；
提供柔性电路结构，其具有柔性金属材料被暴露的区域；
将所述柔性电路结构邻近所述第一成形标准件安置，以在所述柔性金属材料与所述第一金属材料之间形成接触区域；
选择性将热量施加至所述接触区域。
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US7572671B2 (en) 2009-08-11
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WO2005112100A2 (en) 2005-11-24
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US20050242423A1 (en) 2005-11-03
US20090298230A1 (en) 2009-12-03

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