CN1866815A - 接收并行数据的装置及其方法 - Google Patents
接收并行数据的装置及其方法 Download PDFInfo
- Publication number
- CN1866815A CN1866815A CNA200510068099XA CN200510068099A CN1866815A CN 1866815 A CN1866815 A CN 1866815A CN A200510068099X A CNA200510068099X A CN A200510068099XA CN 200510068099 A CN200510068099 A CN 200510068099A CN 1866815 A CN1866815 A CN 1866815A
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- clock signal
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- 239000000872 buffer Substances 0.000 claims abstract description 139
- 230000014759 maintenance of location Effects 0.000 claims abstract description 20
- 238000012163 sequencing technique Methods 0.000 claims description 32
- 238000003860 storage Methods 0.000 claims description 28
- 230000005540 biological transmission Effects 0.000 claims description 17
- 238000001514 detection method Methods 0.000 claims description 15
- 230000001360 synchronised effect Effects 0.000 description 34
- 230000014509 gene expression Effects 0.000 description 9
- 230000000630 rising effect Effects 0.000 description 8
- 238000012360 testing method Methods 0.000 description 7
- 238000012549 training Methods 0.000 description 7
- 230000003111 delayed effect Effects 0.000 description 4
- 238000012545 processing Methods 0.000 description 3
- 238000012546 transfer Methods 0.000 description 3
- 230000000295 complement effect Effects 0.000 description 2
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Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
- G06F13/4027—Coupling between buses using bus bridges
- G06F13/405—Coupling between buses using bus bridges where the bridge performs a synchronising function
- G06F13/4054—Coupling between buses using bus bridges where the bridge performs a synchronising function where the function is bus cycle extension, e.g. to meet the timing requirements of the target bus
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/12—Synchronisation of different clock signals provided by a plurality of clock generators
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/0016—Arrangements for synchronising receiver with transmitter correction of synchronization errors
- H04L7/005—Correction by an elastic buffer
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/062—Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers
- H04J3/0626—Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers plesiochronous multiplexing systems, e.g. plesiochronous digital hierarchy [PDH], jitter attenuators
- H04J3/0629—Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers plesiochronous multiplexing systems, e.g. plesiochronous digital hierarchy [PDH], jitter attenuators in a network, e.g. in combination with switching or multiplexing, slip buffers
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Computer Hardware Design (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
- Dc Digital Transmission (AREA)
- Communication Control (AREA)
Abstract
Description
Claims (15)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004192626 | 2004-06-30 | ||
JP2004192626A JP4291225B2 (ja) | 2004-06-30 | 2004-06-30 | パラレルデータを受信する装置および方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN1866815A true CN1866815A (zh) | 2006-11-22 |
CN100559750C CN100559750C (zh) | 2009-11-11 |
Family
ID=35169784
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CNB200510068099XA Expired - Fee Related CN100559750C (zh) | 2004-06-30 | 2005-05-16 | 接收并行数据的装置及其方法 |
Country Status (5)
Country | Link |
---|---|
US (1) | US7620138B2 (zh) |
EP (1) | EP1612690B1 (zh) |
JP (1) | JP4291225B2 (zh) |
KR (1) | KR100669931B1 (zh) |
CN (1) | CN100559750C (zh) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101853217A (zh) * | 2009-03-30 | 2010-10-06 | 富士通株式会社 | 缓存控制装置、信息处理装置和计算机可读记录介质 |
CN104601985A (zh) * | 2015-01-14 | 2015-05-06 | 华为技术有限公司 | 信号分析方法、装置和系统 |
CN108009111A (zh) * | 2016-11-01 | 2018-05-08 | 华为技术有限公司 | 数据流连接方法及装置 |
CN116521613A (zh) * | 2023-07-04 | 2023-08-01 | 南京启见半导体科技有限公司 | 超低延迟的时钟域切换数据传输系统 |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7483173B2 (en) * | 2005-03-10 | 2009-01-27 | Kabushiki Kaisha Toshiba | Data processor having a synchronizing function of a plurality of chips |
US7401246B2 (en) | 2005-06-30 | 2008-07-15 | Intel Corporation | Nibble de-skew method, apparatus, and system |
WO2007097008A1 (ja) | 2006-02-24 | 2007-08-30 | Fujitsu Limited | データ受信装置及びデータ送信装置 |
KR100903132B1 (ko) | 2007-12-11 | 2009-06-16 | 한국전자통신연구원 | 병렬 수신 장치 및 방법 |
KR101918455B1 (ko) * | 2012-07-27 | 2018-11-15 | 삼성전자주식회사 | 위상 잠금 루프의 홀드 타임 또는 록 타임을 이용하여 데이터 세그먼트들을 스케쥴링하는 저전력 통신 장치 |
Family Cites Families (30)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4841551A (en) | 1987-01-05 | 1989-06-20 | Grumman Aerospace Corporation | High speed data-clock synchronization processor |
JP3125348B2 (ja) | 1991-09-11 | 2001-01-15 | 日本電気株式会社 | パラレルビット同期方式 |
JPH0653955A (ja) | 1992-04-21 | 1994-02-25 | Nec Corp | パラレルビット同期方式 |
JPH07154381A (ja) | 1993-11-30 | 1995-06-16 | Hitachi Ltd | データ転送装置 |
US6078623A (en) * | 1995-03-20 | 2000-06-20 | Hitachi, Ltd. | Data transmission apparatus and method |
JP2730517B2 (ja) * | 1995-06-12 | 1998-03-25 | 日本電気株式会社 | 高速データ受信回路 |
US6279077B1 (en) * | 1996-03-22 | 2001-08-21 | Texas Instruments Incorporated | Bus interface buffer control in a microprocessor |
US6247138B1 (en) * | 1997-06-12 | 2001-06-12 | Fujitsu Limited | Timing signal generating circuit, semiconductor integrated circuit device and semiconductor integrated circuit system to which the timing signal generating circuit is applied, and signal transmission system |
JP4063392B2 (ja) * | 1998-03-26 | 2008-03-19 | 富士通株式会社 | 信号伝送システム |
US6173432B1 (en) * | 1997-06-20 | 2001-01-09 | Micron Technology, Inc. | Method and apparatus for generating a sequence of clock signals |
US6262998B1 (en) * | 1997-12-24 | 2001-07-17 | Nortel Networks Limited | Parallel data bus integrated clocking and control |
JP3349943B2 (ja) * | 1998-03-03 | 2002-11-25 | 日本電気株式会社 | 半導体装置 |
JP4634605B2 (ja) | 1998-03-12 | 2011-02-16 | エルピーダメモリ株式会社 | データ伝送システム |
JP3228708B2 (ja) * | 1998-04-03 | 2001-11-12 | パイオニア株式会社 | 伝送システムにおける受信インターフェース装置 |
KR20000026042A (ko) * | 1998-10-16 | 2000-05-06 | 서평원 | 고속데이터 전송장치에 구비되는 선입력선출력메모리를 이용한데이터 다중화/역다중화 회로 |
US6252419B1 (en) * | 1999-01-08 | 2001-06-26 | Altera Corporation | LVDS interface incorporating phase-locked loop circuitry for use in programmable logic device |
US6636993B1 (en) * | 1999-02-12 | 2003-10-21 | Fujitsu Limited | System and method for automatic deskew across a high speed, parallel interconnection |
JP3630591B2 (ja) * | 1999-08-30 | 2005-03-16 | 沖電気工業株式会社 | クロック乗せ換え方法及び回路 |
JP3522628B2 (ja) * | 1999-11-09 | 2004-04-26 | シャープ株式会社 | 半導体装置および表示装置モジュール |
JP2002082830A (ja) | 2000-02-14 | 2002-03-22 | Mitsubishi Electric Corp | インターフェイス回路 |
JP3758953B2 (ja) * | 2000-07-21 | 2006-03-22 | 富士通株式会社 | スキュー補正装置 |
JP3557612B2 (ja) * | 2000-12-05 | 2004-08-25 | 日本電気株式会社 | 低レーテンシ高速伝送システム |
JP2002223208A (ja) | 2001-01-29 | 2002-08-09 | Nec Corp | 多チャネルデータ伝送方法および方式 |
US6907552B2 (en) * | 2001-08-29 | 2005-06-14 | Tricn Inc. | Relative dynamic skew compensation of parallel data lines |
US7085950B2 (en) * | 2001-09-28 | 2006-08-01 | Koninklijke Philips Electronics N.V. | Parallel data communication realignment of data sent in multiple groups |
US7187741B2 (en) * | 2001-10-31 | 2007-03-06 | Nxp B.V. | Clock domain crossing FIFO |
JP3998532B2 (ja) * | 2002-08-07 | 2007-10-31 | 株式会社ルネサステクノロジ | データ転送装置 |
TWI298223B (en) * | 2002-11-04 | 2008-06-21 | Mstar Semiconductor Inc | Data recovery circuit, phase detection circuit and method for detecting and correcting phase conditions |
JP4467233B2 (ja) * | 2002-12-24 | 2010-05-26 | 株式会社日立製作所 | 位相調整装置、位相調整方法および高速並列信号用スキュー補正装置 |
JP4456432B2 (ja) * | 2004-08-02 | 2010-04-28 | 富士通株式会社 | 基準信号を用いて同期伝送を行う装置および方法 |
-
2004
- 2004-06-30 JP JP2004192626A patent/JP4291225B2/ja not_active Expired - Fee Related
- 2004-11-29 US US10/997,950 patent/US7620138B2/en not_active Expired - Fee Related
- 2004-11-29 EP EP04257388A patent/EP1612690B1/en not_active Expired - Fee Related
- 2004-12-10 KR KR1020040104244A patent/KR100669931B1/ko not_active IP Right Cessation
-
2005
- 2005-05-16 CN CNB200510068099XA patent/CN100559750C/zh not_active Expired - Fee Related
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101853217A (zh) * | 2009-03-30 | 2010-10-06 | 富士通株式会社 | 缓存控制装置、信息处理装置和计算机可读记录介质 |
CN101853217B (zh) * | 2009-03-30 | 2013-02-13 | 富士通株式会社 | 缓存控制装置、信息处理装置和计算机可读记录介质 |
CN104601985A (zh) * | 2015-01-14 | 2015-05-06 | 华为技术有限公司 | 信号分析方法、装置和系统 |
CN104601985B (zh) * | 2015-01-14 | 2017-04-12 | 华为技术有限公司 | 信号分析方法、装置和系统 |
CN108009111A (zh) * | 2016-11-01 | 2018-05-08 | 华为技术有限公司 | 数据流连接方法及装置 |
CN108009111B (zh) * | 2016-11-01 | 2020-02-21 | 华为技术有限公司 | 数据流连接方法及装置 |
CN116521613A (zh) * | 2023-07-04 | 2023-08-01 | 南京启见半导体科技有限公司 | 超低延迟的时钟域切换数据传输系统 |
CN116521613B (zh) * | 2023-07-04 | 2023-08-25 | 南京启见半导体科技有限公司 | 超低延迟的时钟域切换数据传输系统 |
Also Published As
Publication number | Publication date |
---|---|
US20060002399A1 (en) | 2006-01-05 |
CN100559750C (zh) | 2009-11-11 |
EP1612690A3 (en) | 2006-09-20 |
JP4291225B2 (ja) | 2009-07-08 |
JP2006019790A (ja) | 2006-01-19 |
KR100669931B1 (ko) | 2007-01-16 |
EP1612690A2 (en) | 2006-01-04 |
KR20060001808A (ko) | 2006-01-06 |
US7620138B2 (en) | 2009-11-17 |
EP1612690B1 (en) | 2013-04-03 |
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Legal Events
Date | Code | Title | Description |
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C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
CI01 | Correction of invention patent gazette |
Correction item: [30] priority [32][33][31] Correct: [32]2004.06.30[33]JP[31]192626/2004 False: Leak open Number: 47 Volume: 22 |
|
CI02 | Correction of invention patent application |
Correction item: [30] priority [32][33][31] Correct: [32]2004.06.30[33]JP[31]192626/2004 False: Leak open Number: 47 Volume: 22 |
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COR | Change of bibliographic data |
Free format text: CORRECT: ¢30!PRIORITY ¬¢32!¢33!¢31!; FROM: NON-PUBLICITY TO: ¢32!2004.6.30¢33!JP¢31!192626/2004 |
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ERR | Gazette correction |
Free format text: CORRECT: ¢30!PRIORITY ¬¢32!¢33!¢31!; FROM: NON-PUBLICITY TO: ¢32!2004.6.30¢33!JP¢31!192626/2004 |
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C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20091111 Termination date: 20170516 |
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CF01 | Termination of patent right due to non-payment of annual fee |