CN1630087A - 具有通过层叠模板层的局部非晶化和再结晶而形成的选定半导体晶向的平坦衬底 - Google Patents
具有通过层叠模板层的局部非晶化和再结晶而形成的选定半导体晶向的平坦衬底 Download PDFInfo
- Publication number
- CN1630087A CN1630087A CNA2004100923713A CN200410092371A CN1630087A CN 1630087 A CN1630087 A CN 1630087A CN A2004100923713 A CNA2004100923713 A CN A2004100923713A CN 200410092371 A CN200410092371 A CN 200410092371A CN 1630087 A CN1630087 A CN 1630087A
- Authority
- CN
- China
- Prior art keywords
- orientation
- crystal
- substrat structure
- semiconductor
- smooth hybrid
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 147
- 239000000758 substrate Substances 0.000 title claims abstract description 103
- 238000001953 recrystallisation Methods 0.000 title claims abstract description 4
- 239000013078 crystal Substances 0.000 title claims description 98
- 238000000034 method Methods 0.000 claims abstract description 76
- 229910052710 silicon Inorganic materials 0.000 claims description 80
- 239000010703 silicon Substances 0.000 claims description 76
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 75
- 238000002425 crystallisation Methods 0.000 claims description 40
- 230000008025 crystallization Effects 0.000 claims description 37
- 238000003475 lamination Methods 0.000 claims description 25
- 150000002500 ions Chemical class 0.000 claims description 16
- 238000005516 engineering process Methods 0.000 claims description 14
- 238000002347 injection Methods 0.000 claims description 14
- 239000007924 injection Substances 0.000 claims description 14
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 13
- 239000000463 material Substances 0.000 claims description 10
- 230000004888 barrier function Effects 0.000 claims description 8
- 235000012239 silicon dioxide Nutrition 0.000 claims description 8
- 239000012212 insulator Substances 0.000 claims description 7
- 229910052760 oxygen Inorganic materials 0.000 claims description 6
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 5
- 229910052734 helium Inorganic materials 0.000 claims description 5
- 229910052739 hydrogen Inorganic materials 0.000 claims description 5
- 239000000377 silicon dioxide Substances 0.000 claims description 5
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 4
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims description 4
- 229910000927 Ge alloy Inorganic materials 0.000 claims description 4
- 229910000673 Indium arsenide Inorganic materials 0.000 claims description 4
- 229910003811 SiGeC Inorganic materials 0.000 claims description 4
- 229910045601 alloy Inorganic materials 0.000 claims description 4
- 239000000956 alloy Substances 0.000 claims description 4
- 229910052786 argon Inorganic materials 0.000 claims description 4
- 150000001875 compounds Chemical class 0.000 claims description 4
- 229910052732 germanium Inorganic materials 0.000 claims description 4
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 claims description 4
- 229910003465 moissanite Inorganic materials 0.000 claims description 4
- 229910052757 nitrogen Inorganic materials 0.000 claims description 4
- 238000005498 polishing Methods 0.000 claims description 4
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 4
- 229910002026 crystalline silica Inorganic materials 0.000 claims description 3
- 239000003989 dielectric material Substances 0.000 claims description 3
- 239000007789 gas Substances 0.000 claims description 3
- 229910044991 metal oxide Inorganic materials 0.000 claims description 3
- 150000004706 metal oxides Chemical class 0.000 claims description 3
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 2
- 229910052785 arsenic Inorganic materials 0.000 claims description 2
- 229910052796 boron Inorganic materials 0.000 claims description 2
- 229910052799 carbon Inorganic materials 0.000 claims description 2
- 229910052743 krypton Inorganic materials 0.000 claims description 2
- 239000002184 metal Substances 0.000 claims description 2
- 229910052751 metal Inorganic materials 0.000 claims description 2
- 239000000203 mixture Substances 0.000 claims description 2
- 150000004767 nitrides Chemical class 0.000 claims description 2
- -1 oxonium ion Chemical class 0.000 claims description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 2
- 238000000926 separation method Methods 0.000 claims 2
- 239000004020 conductor Substances 0.000 claims 1
- 238000005280 amorphization Methods 0.000 abstract description 3
- 235000012431 wafers Nutrition 0.000 description 10
- 238000000137 annealing Methods 0.000 description 9
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 7
- 238000010849 ion bombardment Methods 0.000 description 5
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 4
- 238000002955 isolation Methods 0.000 description 4
- 239000001301 oxygen Substances 0.000 description 4
- 238000013459 approach Methods 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- 238000010899 nucleation Methods 0.000 description 3
- 238000012937 correction Methods 0.000 description 2
- 230000007797 corrosion Effects 0.000 description 2
- 238000005260 corrosion Methods 0.000 description 2
- 239000002019 doping agent Substances 0.000 description 2
- 238000011049 filling Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 230000002209 hydrophobic effect Effects 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000011835 investigation Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000005224 laser annealing Methods 0.000 description 1
- 230000035772 mutation Effects 0.000 description 1
- 230000006911 nucleation Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 229910021426 porous silicon Inorganic materials 0.000 description 1
- 238000004151 rapid thermal annealing Methods 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 239000011435 rock Substances 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02609—Crystal orientation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02656—Special treatments
- H01L21/02664—Aftertreatments
- H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
- H01L21/76275—Vertical isolation by bonding techniques
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
- H01L27/1207—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI combined with devices in contact with the semiconductor body, i.e. bulk/SOI hybrid circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/04—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
- H01L29/045—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes by their particular orientation of crystalline planes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
- H01L29/1054—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a variation of the composition, e.g. channel with strained layer for increasing the mobility
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/66772—Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/78654—Monocrystalline silicon transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Element Separation (AREA)
- Recrystallisation Techniques (AREA)
- Thin Film Transistor (AREA)
Abstract
提供了一种利用模板叠层的局部非晶化和再结晶来形成具有不同晶向的半导体层的平坦衬底的方法。还提供了用本发明方法形成的混合取向半导体衬底结构以及与包含排列在不同表面取向上的至少二个半导体器件用来提高器件性能的各种CMOS电路集成的这种结构。
Description
技术领域
本发明涉及到高性能互补金属氧化物半导体(CMOS)电路,其中,利用p型场效应晶体管(FET)和n型FET不同的半导体表面取向,载流子迁移率得到了提高。更确切地说,本发明涉及到用来制造具有不同表面晶向的平坦衬底的方法,并涉及到用此方法制造的混合取向的衬底结构。
背景技术
当前半导体技术的CMOS电路包含其工作利用电子载流子的n型FET以及其工作利用空穴载流子的p型FET。CMOS电路通常被制造在具有单个晶向的半导体晶片上。确切地说,大多数当今半导体器件被制作在具有(100)表面取向的硅上。
已知电子在(100)表面取向的硅中具有高的迁移率,而空穴在(110)表面取向的硅中具有高的迁移率。实际上,110取向的硅晶片上的空穴迁移率能够高于标准100取向硅晶片上的空穴迁移率大约2-4倍。因此,希望制作一种包含100取向的硅(其中可以制作nFET)以及110取向的硅(其中可以制作pFET)的混合取向的衬底。
具有不同表面取向的平坦混合衬底结构,先前已经有所描述(见例如2003年10月29日提交的共同受让的美国申请No.10/696634以及2003年6月17日提交的共同受让的美国申请No.10/250241)。
图1A-1E剖面图示出了平坦混合取向半导体衬底结构的一些现有技术例子,它包含体半导体衬底10、介质沟槽隔离区20、具有第一表面取向(例如j’k’l’)的半导体区30、以及具有第二表面取向(例如jkl)的半导体区40。在图1A的结构中,半导体区30和40都直接位于体衬底10上,半导体区40与体衬底10具有相同的取向。图1B的结构与图1A的结构的不同之处仅仅在于半导体区30位于埋置的氧化物(BOX)层50上而不是直接位于体衬底10上。图1C-1E的结构与图1A-1B的结构的不同之处是BOX层50和50’的厚度以及沟槽隔离结构20和20’的深度。
图2A-2B剖面图示出了包含至少一个(110)硅晶面上的pFET和至少一个(100)硅晶面上的nFET的集成CMOS电路如何可以被有利地排列在图1B的混合取向衬底结构上的一些以前的例子。在图2A中,100取向的体硅衬底120具有BOX层140上的110取向硅区域130以及体衬底120上的再生长的100取向硅区域150。pFET器件170被排列在110取向的区域130上,而nFET器件180被排列在100取向的区域150上。在图2B中,110取向的体硅衬底180具有BOX层140上的100取向硅区域190以及体衬底180上的再生长的110取向硅区域200。pFET器件210被排列在110取向的区域180上,而nFET器件220被排列在100取向的区域190上。
图3A-3I剖面图示出了用来形成图1B的结构的现有技术方法的各个步骤。具体地说,图3A示出了起始硅衬底250,而图3B示出了形成BOX层260和绝缘体上硅(SiOI)器件层270之后的衬底250。硅衬底250可以是110(或100)取向,且SiOI器件层270可以是100(或110)取向。可以用键合方法或其它方法来形成SiOI层270。在淀积保护介质(最好是SiNx)层280以形成图3C的结构之后,如图3D所示,清除选定区域中的SiOI器件层270和BOX层260,以便形成延伸到硅衬底250的窗口290。如图3E所示,用介质(最好是SiNx)对窗口290进行衬垫,然后对衬垫进行腐蚀,以便形成侧壁间隔300。接着,在窗口290中选择性地生长外延硅310,以便产生图3F的结构,此结构被整平,以便形成图3G的结构。然后用诸如抛光之类的工艺清除保护介质280,以便形成具有共平面的取向不同的硅器件层310(体硅衬底250上)和320(BOX层260上)的图3H的结构。图3I示出了在图3H结构中已经形成了浅沟槽隔离区330之后所完成的衬底结构。
但对于许多应用来说,可能希望在一个BOX上具有二种不同取向的硅区。利用图3A-3I方法的变种,有可能制作这种结构,但不容易。例如,借助于用包含衬底410、BOX层420、以及硅层430的SiOI衬底代替图3A中的硅衬底250来产生不同取向的第一取向单晶区320和与半导体层430一致的第二取向单晶区440,可以形成图4的结构。但使用二个BOX层,对工艺增加了额外的复杂性,并产生了混合取向中的一个明显地比另一个更厚的结构(当二个层需要薄时,这是一个缺点)。此外,选择性外延硅生长可能是错综复杂的;缺陷容易成核在侧壁间隔300的侧壁上(图3E-3F所示),特别当窗口290小(例如直径小于500nm)时,更是如此。
考虑到上述情况,希望具有一些更简单和更好的方法(亦即不要求外延再生长的方法)来形成平坦的混合取向半导体衬底结构,特别是其中不同取向的半导体被排列在一个公共BOX层上的平坦的混合取向绝缘体上半导体(SOI)衬底结构。
此外,希望具有这种平坦的混合取向SOI衬底上的集成电路,其中的电路包含(110)晶面上的pFET以及(100)晶面上的nFET。
发明内容
因此,本发明的目的是提供一种具有一个表面的平坦的混合取向SOI衬底结构,它包含至少二个具有不同表面取向的清楚地确定的单晶半导体区,其中,各个不同取向的半导体区被排列在一个公共的BOX层上。术语“清楚地确定的”在此处被用来表示给定表面取向的各个表面区是宏观的而不仅仅是多晶硅的单个晶粒。
本发明的一个相关目的是提供一些用来制造这种平坦的混合取向半导体衬底结构的方法。
本发明的另一目的是提供一些在各种支持层上制造相似的混合取向半导体衬底结构的方法。
本发明的又一目的是在本发明的混合取向衬底上提供集成电路(IC),其中的IC包含(110)晶面上的pFET以及(100)晶面上的nFET。
根据上述和其它的目的,提供了一些新方法来形成各种平坦的混合取向半导体衬底结构。所有方法的共同点在于3个基本步骤,利用这些步骤,选定的半导体区的取向可以从原来的取向被改变成所希望的取向:
形成双层模板叠层,它包含具有第一取向的第一下单晶半导体层(即衬底)以及具有不同于第一取向的第二取向的第二上(通常为键合的)单晶半导体层;
在选定的区域内,(例如用通过掩模的离子注入方法)对双层模板叠层的一个层进行非晶化;以及
用叠层的未被非晶化的层作为模板,对局部非晶化的区域进行再结晶,从而将局部非晶化的区域的取向从原来的取向改变成所希望的取向。
为了尽量减少横向模板的可能性,选定要非晶化的且模板再结晶的各个区域的侧面通常可以例如被沟槽隔离于相邻的结晶区。可以在非晶化之前或在非晶化与再结晶之间来形成和填充这些沟槽,或在非晶化之后形成这些沟槽并在再结晶之后填充这些沟槽。
在本发明的一个实施方案中,上述的各个基本步骤被组合到用来形成平坦的混合取向SiOI衬底结构的方法中。100取向的硅衬底被用于双层模板叠层的第一下层,而110取向的硅层被用于双层模板叠层的第二上层。模板叠层的最上部分在选定的区域内被非晶化到终止于下方100取向硅衬底的深度。然后,用下方100取向的硅作为模板,各个非晶化的硅区被再结晶成100取向的硅。这些图形化非晶化和再结晶步骤在被处理的区域内留下了100取向硅的表面区,并在未被处理的区域内留下了110取向硅的表面区,在这些步骤之后,用氧注入和退火的方法(例如“氧注入分离”或SIMOX工艺),来形成埋置的氧化物(BOX)层。
在本发明的另一个实施方案中,上述的各个基本步骤被组合到用来形成平坦的混合取向SiOI衬底结构的另一方法中。在此方法中,BOX层上110取向的SiOI层被用于双层模板叠层的第一下层,而100取向的硅层被用于双层模板叠层的第二上层。然后,模板叠层的最下部分在选定的区域内被从BOX层一直非晶化到终止于上模板层的深度。然后,用100取向的上层硅作为模板,各个非晶化的硅区被再结晶成100取向的硅。然后,用诸如抛光之类的工艺清除双层模板的最上部分,从而留下110取向的硅(在未被处理的区域内)和100取向的硅(在被处理的区域内)的共平面表面区。
本发明的基本步骤能够容易地被整个或部分地用来在不同的衬底(例如体衬底、薄的或厚的BOX衬底、绝缘的或高阻的衬底)上形成平坦的混合取向半导体结构,或用来形成具有3个或更多个表面取向的平坦的混合取向半导体衬底结构。
本发明的另一情况提供了本发明平坦的混合取向半导体衬底上的集成电路,其中的集成电路包含(110)晶面上的pFET以及(100)晶面上的nFET。
附图说明
从本发明的下列详细描述中,这些和其它的特点、情况、以及优点将更加明显和被理解,其中:
图1A-1E剖面图示出了现有技术平坦的混合取向半导体衬底结构的一些例子,其中,二种半导体取向的第一种被直接排列在体半导体衬底上,而二种半导体取向的第二种被排列在衬底上(图1A和1C)、被薄的BOX层部分地隔离于衬底(图1E)、或被薄的BOX层完全地隔离于衬底(图1B和1D);
图2A-2B剖面图示出了图1B的混合取向衬底结构如何可以构成包含至少一个110取向的单晶硅区上的pFET和至少一个100取向的单晶硅区上的nFET的集成电路的基础;
图3A-3I剖面图示出了用来形成图1B情况所述图1A-1E结构的基本的现有技术方法的各步骤;
图4剖面图示出了平坦的混合取向半导体衬底结构的现有技术例子,其中,二种不同取向的单晶硅区都被排列在埋置的绝缘层上;
图5A-5B剖面图示出了本发明的混合取向衬底的二个优选的SOI实施方案;
图6剖面图示出了本发明的混合取向衬底结构如何能够被用来构成包含至少一个(110)硅晶面上的pFET和至少一个(100)硅晶面上的nFET的集成电路的基础;
图7A-7G剖面图示出了上层非晶化和下层模板的情况所述的本发明方法的各个基本步骤;
图8A-8G剖面图示出了用来产生本发明的图5A的结构的第一优选方法;
图9A-9F剖面图示出了用来产生本发明的图5B的结构的第二优选方法;而
图10A-10I剖面图示出了可以用本发明的方法产生的混合取向衬底的不同的实施方案。
具体实施方式
下面参照本发明的附图来更详细地描述本发明,本发明提供了平坦的混合取向SOI衬底结构及其制造方法。
图5A-5B剖面图示出了可以用本发明的方法制造的混合取向衬底的二个优选实施方案。图5A的混合取向衬底450和图5B的混合取向衬底460都包含具有第一取向的第一单晶半导体区470和具有不同于第一取向的第二取向的第二单晶半导体区480。半导体区470和480具有大致相同的厚度,并被排列在同一个BOX层490上。术语“BOX”表示埋置的氧化物区。虽然此处具体地使用了这一称谓,但本发明不仅仅局限于埋置的氧化物。而是能够采用各种绝缘层;以下更详细地来描述各种绝缘层。
各个半导体区470和480被示为具有相同的深度并止于BOX层490的介质沟槽隔离区500分隔开。但在本发明的某些实施方案中,沟槽隔离区500可以按需要较浅(以便不达及BOX层490),较深(以便延伸通过BOX层490),或深度不相等。图5A和5B的结构彼此的不同处仅仅在于衬底510和520的特色。图5A中的衬底510是对单晶半导体区480具有外延关系的半导体,而图5B中的衬底520除了与随后要经受的任何一种加工兼容之外,没有特殊的限制。
图5A-5B的混合取向衬底结构可以被组合成包含至少一个(110)晶面上的pFET和至少一个(100)晶面上的nFET的集成电路的衬底。图6剖面图示出了图5B的混合取向衬底结构的硅上的一种示例性集成电路。衬底520具有被BOX层490上的隔离区500分隔开的单晶110取向的硅区530和单晶100取向的硅区540。pFET器件170被排列在110取向的区域530上,而nFET器件180被排列在100取向的区域540上。为清楚起见,未示出掺杂情况。
用本技术领域熟练人员众所周知的技术,图6所示的FET可以被制作在图5A所示的结构上。在某些实施方案中,层540和530的110和100晶向被反转。在这种实施方案中,pFET器件170可以仍然被制作在110取向的区域顶部,而nFET器件180可以被制作在100取向的表面顶部。
本发明还提供了用来形成平坦的混合取向衬底结构的一些新方法。所有方法的共同点是3个基本步骤,利用这些步骤,选定的半导体区的取向可以从原来的取向被改变成所希望的取向:
形成双层模板叠层,它包含具有第一取向的第一下单晶半导体层(即衬底)以及具有不同于第一取向的第二取向的第二上(通常为键合的)单晶半导体层;
在选定的区域内,(例如用通过掩模的离子注入方法)对双层模板叠层的一个层进行非晶化;以及
用叠层的未被非晶化的层作为模板,对局部非晶化的区域进行再结晶,从而将局部非晶化的区域的取向从原来的取向改变成所希望的取向。
上层非晶化和底层模板的情况的这些步骤被示于图7A-7D中。虽然示出了此实施方案,但本发明还尝试了底层被非晶化且再结晶从顶层被模板的方法。
图7A示出了起始的SOI衬底580,它包含基底衬底520、BOX层490、以及具有第一取向的单晶SOI层590。可以用键合或用本技术熟知的任何其它方法来形成SOI层590。图7B示出了双层模板叠层600,它包含作为具有第一取向的下模板层的SOI层590以及作为具有不同于第一取向的第二取向的上模板层的单晶半导体层610。通常可以用键合方法来形成层610。图7C示出了选定区域中离子轰击620产生局部非晶化区域630之后的图7B结构。局部非晶化的区域630从上模板层610的顶部表面一直延伸到位于下模板层590中的界面640。通常可以用结合图形化掩模的满铺离子轰击来进行选定区域的离子轰击620。图7D示出了局部非晶化区域630已经被再结晶(开始于界面640,用下层590作为模板)以便形成单晶半导体区650之后的图7C结构。未被非晶化的上模板层区域610’(具有第二晶向)和再结晶的区域650(具有第一晶向)现在包含平坦的混合取向衬底650,其表面A-B包含至少二个具有不同表面取向的清楚地确定的单晶半导体区。
为了尽量减少横向模板的可能性,选定要非晶化的以及模板再结晶的各个区域的侧面通常可以例如被沟槽至少部分地隔离于相邻的结晶区。可以在非晶化之前或在非晶化与再结晶之间来形成和填充这些沟槽,或在非晶化之后形成这些沟槽并在再结晶之后填充这些沟槽。典型地可以用诸如通过掩模的反应离子刻蚀(RIE)来形成沟槽。
图7E-7G示出了隔离沟槽的3种几何形状。在图7E中,隔离沟槽660延伸通过上模板层,但不延伸超过非晶化深度。在此情况下,可能出现来自侧界面670的模板。在图7F中,隔离沟槽680延伸超过非晶化深度,但不是一直到BOX层490,而在图7G中,隔离沟槽690一直延伸到BOX层490。但若所希望的晶向的再结晶速率比从竞争的不希望晶向引晶的再结晶快得多,则可以不需要隔离沟槽。例如,已经报道,100取向硅的硅注入晶化的单晶硅样品的再结晶速率比110取向硅的快3倍(见例如论文L.Csepregi et al.,J.Appl.Phys.,493096(1978))。
当设计模板叠层和工艺流程时,还应该考虑不同半导体取向的再结晶速率可以不同的事实。具有较慢生长取向的双层模板叠层的一个最好是被晶化的层,而具有较快生长取向的层最好是再结晶从中模板的层。
在图8A-8G所示的本发明的一个实施方案中,图7A-7D的基本步骤被组合到用来形成与图5A的结构450相似的平坦的混合取向SiOI衬底结构的方法中。为简单起见,未示出隔离沟槽。图8A示出了包含模板叠层第一下层的100取向的硅衬底700;图8B示出了加入包含模板叠层第二上层的110取向的硅层710之后的衬底700。层710通常用键合方法来形成。
图8C示出了图8B的结构在选定区域中经受离子轰击720,以便产生具有从模板层710的顶部表面延伸到终止于衬底700的深度的局部非晶化区730的图8D的结构。图8E示出了局部非晶化区730已经被再结晶(利用100取向的硅衬底700作为模板)以便形成单晶100取向的硅区740之后的图8D的结构。未被非晶化的110取向的硅区710’和再结晶的100取向的硅区740现在包含平坦的混合取向体衬底750,其表面A-B包含至少二个具有不同表面取向的清楚地确定的单晶半导体区。
然后,如图8F-8G所示,SIMOX工艺被用来产生BOX层。图8F示出了图8E的结构被暴露于用来产生埋置的富氧层770的满铺氧离子注入760。富氧层770最好包含层700与710之间的原先界面,并被适当的退火步骤转变成图8G的BOX层780。
在图9A-9F所示的本发明的另一个实施方案中,图7A-7D的基本步骤被组合到用来形成与图5B的结构460相似的平坦的混合取向SiOI衬底结构的另一方法中。具体地说,图9A示出了起始的SiOI衬底800,它包含基底衬底520、BOX层490、以及110取向的单晶硅层810。可以用键合方法或用本技术熟知的任何其它方法来形成硅层810。图9B示出了双层模板叠层820,它包含作为下模板层的110取向的硅层810以及作为上模板层的单晶100取向的硅层830。通常可以用键合方法来形成层830。图9C示出了选定区域中经受离子轰击840以产生具有埋置的局部非晶化区域850的图9B结构。局部非晶化的区域850从BOX层490通过下模板层810延伸,且部分地延伸到上模板层830中。如上所述,选择来非晶化和模板再结晶的区域典型地可以被沟槽(未示出)隔离于相邻的结晶区,以便尽量减少横向模板的可能性。图9E示出了局部非晶化区850已经用上模板层810作为模板被再结晶以便形成100取向的单晶硅区860之后的图9D结构。然后用诸如抛光之类的工艺(或氧化随之以湿法回腐蚀)清除上模板层810,以便留下排列在公共BOX层490上的共平面110取向的单晶硅区810’和100取向的单晶硅区860。
应该指出的是,图8A-8G的方法同样可以被用于衬底700和上模板层710的取向被反转,亦即衬底700包含110取向的硅晶片而不是100取向的硅晶片,而上引晶层710包含100取向的硅单晶层而不是110取向的硅单晶层。同样,图9A-9F的方法可以被用于下模板层810和上模板层830的取向被反转,亦即用于是为100取向的硅而不是110取向的硅的下模板层810以及是为110取向的硅而不是100取向的硅的上模板层830。更一般地说,如下列更详细地描述的那样,本发明的结构和方法可以被用于硅之外的半导体。
图10A-10I剖面图示出了可以用本发明的方法制作的混合取向衬底的不同实施方案。图10A示出了“体”平坦混合取向半导体衬底结构900,它包含具有第一取向的第一单晶半导体区910和具有不同于第一取向但与衬底930的取向相同的第二取向的第二单晶半导体区920。图10B的平坦混合取向半导体衬底结构940相似于图10A的结构900,但具有分隔单晶半导体区910与920的沟槽隔离区950。
图10C的平坦混合取向半导体衬底结构960相似于图10A的结构900。但已经用衬底980代替了衬底930,它可以与半导体区920外延相关,或不与半导体区920外延相关。结构960还包含半导体区910和920下方的BOX层970以及保留在第一半导体区910下方的具有第二取向的第二半导体材料的残留部分990。除了半导体区920与半导体衬底930外延相关,且BOX层970位于第一单晶半导体区910与衬底930之间的界面1010上方之外,图10D的平坦混合取向半导体衬底结构1000相似于图10C的结构960。
除了半导体衬底930已经被绝缘衬底1040代替之外,图10E-10F的平坦混合取向半导体衬底结构1020和1030完全相同于图10A-10B的结构1000和940。
图10G-10H的平坦混合取向半导体衬底结构1050和1060相似于图10C的结构960,但具有沟槽隔离区950。在图10G的结构1050中,沟槽隔离区950延伸在第一单晶半导体区910与残留部分990之间的界面1070下方,但不达及BOX层970。在图10H的结构1060中,沟槽隔离区950延伸到BOX层970。
图10I的平坦混合取向半导体衬底结构1080包含被延伸到BOX层970的沟槽隔离区950分隔开的3个不同取向的单晶半导体区910、920、以及1090。利用本发明的局部晶化和再结晶方法,用多层模板叠层代替双层模板叠层,可以形成具有3个或更多个表面取向的平坦混合取向半导体衬底结构。
可以用本发明各个基本步骤的具有或不具有额外步骤的各种排列,来形成图5A-5B以及图10A-10I那样的结构。例如,利用对第二半导体材料920的残留部分990进行非晶化,并用单晶区910作为模板对非晶化区进行再结晶的额外步骤,可以从图10H的结构形成图5B的平坦混合取向结构仿制460。
本发明的半导体衬底和单晶半导体区可以选自各种半导体材料。例如,衬底510、520、700、930和980,以及不同取向的第一和第二半导体区470、610’、910、480、650、920,可以选自Si、SiC、SiGe、SiGeC、Ge合金、Ge、C、GaAs、InAs、InP、以及其它III-V或II-VI化合物半导体。此处还尝试了具有或不具有一些掺杂剂的上述各种半导体材料的层状组合或合金(例如SiGe上的硅层)。第一和第二半导体区可以是应变的和非应变的,或可以采用应变层与非应变层的组合。晶向通常可以选自(110)、(111)、(100)。
第一和第二单晶半导体区470、610’、910、480、650、920的厚度典型约为1-500nm,约为10-100nm的厚度更典型。衬底510、520、700、930、980的厚度典型为5-1000微米,约为600微米最典型。
BOX层和绝缘衬底1040可以选自各种介质材料,包括但不局限于二氧化硅、结晶二氧化硅、包含氮或其它元素的二氧化硅、氮化硅、金属氧化物(例如Al2O3)、绝缘金属氮化物(例如AIN)、诸如结晶金刚石之类的高导热的材料。BOX的厚度可以约为2-500nm,优选厚度约为50-150nm。
用来形成模板叠层的键合方法可以包括本技术领域熟练人员所知的任何方法(见例如Q.Y.Tong等人的著作“in SemiconductorWafer Bonding:Science and Technology(John Wiley,1998)”以及2003年10月29日提交的共同申请中和共同受让的美国申请No.10/696634和2003年6月17日提交的共同申请中和共同受让的美国申请No.10/250241)。上述共同受让的美国申请在此处被列为参考。
由于晶化区中的杂质通常会阻碍再结晶的进行,故对于最清洁的界面,待要键合的各个不同取向的半导体表面最好是疏水性的(而不是亲水性的)。但键合界面处非常薄的氧化物若能够借助于退火使其成为不连续的小岛形貌,则是可以容忍的(见例如论文P.McCann et al.,“An investigation into interfacial oxide in direct silicon bonding”,6thInt.Symp.on Semeconductor Wafer Bonding,San Francisco,Sept2-7,2001)。借助于将晶片研磨或腐蚀掉(最好利用腐蚀停止层),或借助于利用加工过程早期步骤中产生的机械强度弱的界面层,可以实现键合之后的晶片分离/清除。机械强度弱的界面层的例子包括多孔硅(见例如K.Sakaguchi等人在Solid State Technology,June 2000中描述的Epitaxial Layer Transfer(ELTRAN)以及离子注入的含氢气泡(见例如1994年12月20日发布的M.Bruel的美国专利No.5374564和1999年3月16日发布的K.V.Srikrishnan的美国专利No.5882987所述的智能切割工艺)。
典型地可以用离子注入方法来进行非晶化。最佳的离子注入条件依赖于模板层的材料、模板层的厚度、以及被非晶化的叠层的位置(上部或下部)。可以采用本技术领域熟练人员所知的任何离子种类,包括但不局限于Si、Ge、Ar、C、O、N、H、He、Kr、Xe、P、B、As等。用于非晶化的离子最好是Si或Ge。诸如H和He之类的较轻的离子通常对非晶化的效果较低。可以在从低温到正常室温以上几百℃的温度范围内执行离子注入。“正常室温”意味着大约20-40℃的温度。通常可以用图形化的掩模(例如,对于室温注入工艺,是图形化的光抗蚀剂)来保护不被非晶化的区域免遭离子注入。可以用或不用“屏蔽氧化物”层来执行注入,且若用单个注入无法容易地得到足够均匀非晶化的区域,就可以在不同能量下来执行多个注入。要求的注入剂量依赖于注入的离子种类、被注入的半导体、以及需要非晶化的层的厚度。发现在低温下于50、100、150、以及200keV以每平方厘米6×1015的总剂量注入的硅,足以使100取向和110取向的硅的顶部400nm非晶化(见例如Csepregi等人的论文)。但当注入的离子是Ge且待要非晶化的表面区薄于50-100nm时,低得多的剂量(例如40keV下每平方厘米5×1014)就能够使硅非晶化。
通常,利用在大约200-1300℃,优选在大约400-900℃,更优选在大约400-600℃的温度下的足以引起所希望的再结晶的时间的退火,来进行局部非晶区630、730、850的再结晶。这一时间长度依赖于模板层的取向、待要再结晶的非晶区的厚度、注入的杂质和其它杂质在非晶层中的存在,以及可能依赖于注入区和非注入区之间界面的陡峭性。可以在炉子中或用快速热退火来执行退火。在其它实施方案中,可以用激光退火或脉冲退火来执行退火。退火气氛典型地可以选自各种气体,包括N2、Ar、He、H2、以及这些气体的混合物。
当再结晶步骤之后在结构中产生埋置的绝缘层时,可以采用能够用来形成埋置的绝缘层的任何常规离子注入步骤和退火步骤。例如,任何常规SIMOX工艺都能够被用来在图8F-8G所示的结构中产生埋置的氧化物层。
此处已经与其修正一起详细地描述了本发明的一些实施方案,并在附图中进行了说明,显然,可以进行各种进一步的修正而不偏离本发明的范围。特别应该强调的是,虽然对于具有二种不同取向的少数单晶区的情况已经描述了本发明的大多数衬底结构、电路、以及方法,但本发明同样适用于用来提供包含大量这种单晶区的结构的方法。而且,若这种衬底特征对后续制造的器件是所希望的,则本发明的混合取向衬底可以组合额外的上方层(例如外延生长的半导体或额外的键合层)、清除或回腐蚀某些表面特征(例如使一个或多个单晶半导体区凹陷或沟槽隔离)、和/或特殊的掺杂分布。在上述说明书中,没有打算将本发明限制到比所附权利要求更窄的范围内。给出的例子仅仅是说明性的而不是排他性的。
Claims (55)
1.一种平坦的混合取向绝缘体上半导体即SOI衬底结构,它包含:
具有不同表面取向的至少二个清楚地确定的单晶半导体区,所述至少二个清楚地确定的单晶半导体区设置在公共的埋置绝缘层上,所述公共的埋置绝缘层设置在衬底上。
2.权利要求1的平坦的混合取向SOI衬底结构,还包含至少一个隔离区,此隔离区将所述至少二个清楚地确定的单晶半导体区彼此分隔开。
3.权利要求2的平坦的混合取向SOI衬底结构,其中,所述至少一个隔离区是沟槽隔离区。
4.权利要求2的平坦的混合取向SOI衬底结构,其中,所述至少一个隔离区至少向下延伸到公共埋置绝缘层的上表面。
5.权利要求2的平坦的混合取向SOI衬底结构,其中,所述至少一个隔离区不向下延伸到所述公共埋置绝缘层。
6.权利要求1的平坦的混合取向SOI衬底结构,其中,所述至少二个清楚地确定的单晶半导体区包含相同的或不同的半导体材料。
7.权利要求6的平坦的混合取向SOI衬底结构,其中,所述半导体材料选自Si、SiC、SiGe、SiGeC、Ge合金、Ge、C、GaAs、InAs、InP、它们的层状组合或合金、以及其它III-V或II-VI化合物半导体。
8.权利要求1的平坦的混合取向SOI衬底结构,其中,所述具有不同表面取向的至少二个清楚地确定的单晶半导体区都包括含硅的半导体材料。
9.权利要求1的平坦的混合取向SOI衬底结构,其中,所述至少二个清楚地确定的单晶半导体区,各由应变半导体材料、非应变半导体材料、或应变半导体材料与非应变半导体材料的组合组成。
10.权利要求1的平坦的混合取向SOI衬底结构,其中,所述不同的表面取向选自(110)、(111)和(100)。
11.权利要求8的平坦的混合取向SOI衬底结构,其中,所述不同的表面取向选自(110)、(111)和(100)。
12.权利要求11的平坦的混合取向SOI衬底结构,其中,所述第一含硅半导体区具有(100)晶向,而所述第二含硅半导体区具有(110)晶向。
13.权利要求12的平坦的混合取向SOI衬底结构,还包含至少一个nFET器件和至少一个pFET器件,其中,所述至少一个nFET器件位于所述(100)晶向上,而所述至少一个pFET器件位于所述(110)晶向上。
14.权利要求1的平坦的混合取向SOI衬底结构,还包含至少一个nFET器件和至少一个pFET器件,其中,所述至少一个nFET器件位于对所述器件最佳的晶向上,而所述至少一个pFET器件位于对所述器件最佳的晶向上。
15.权利要求1的平坦的混合取向SOI衬底结构,其中,所述埋置绝缘层是选自二氧化硅、结晶二氧化硅、包含氮的二氧化硅、氮化硅、金属氧化物、金属氮化物、高导热材料的介质材料。
16.权利要求15的平坦的混合取向SOI衬底结构,其中,所述介质材料是二氧化硅或结晶二氧化硅。
17.权利要求1的平坦的混合取向SOI衬底结构,其中,所述衬底是选自Si、SiC、SiGe、SiGeC、Ge合金、Ge、C、GaAs、InAs、InP、它们的层状组合或合金、以及其它III-V或II-VI化合物半导体的半导体材料。
18.权利要求1的平坦的混合取向SOI衬底结构,其中,所述衬底对至少一个所述单晶半导体区具有外延关系。
19.权利要求1的平坦的混合取向SOI衬底结构,其中,所述至少二个清楚地确定的单晶半导体区包含被隔离区分隔开的不同晶向的3个单晶半导体区。
20.权利要求19的平坦的混合取向SOI衬底结构,还包含至少一个nFET器件和至少一个pFET器件,其中,所述至少一个nFET器件位于对所述器件最佳的晶向上,而所述至少一个pFET器件位于对所述器件最佳的晶向上。
21.权利要求1的平坦的混合取向SOI衬底结构,其中,所述至少二个清楚地确定的单晶半导体区的至少一个包含设置在下残留半导体上的上半导体,所述上半导体和下半导体具有不同的表面取向,所述残留半导体与所述公共的埋置绝缘层直接接触。
22.权利要求21的平坦的混合取向SOI衬底结构,还包含至少一个nFET器件和至少一个pFET器件,其中,所述至少一个nFET器件位于对所述器件最佳的晶向上,所述至少一个pFET器件位于对所述器件最佳的晶向上。
23.权利要求21的平坦的混合取向SOI衬底结构,还包含将所述至少二个清楚地确定的单晶半导体区彼此分隔开的至少一个隔离区,其中,所述至少一个隔离区至少向下延伸到所述公共的埋置绝缘层。
24.权利要求21的平坦的混合取向SOI衬底结构,还包含将所述至少二个清楚地确定的单晶半导体区彼此分隔开的至少一个隔离区,其中,所述至少一个隔离区不向下延伸到所述公共的埋置绝缘层。
25.权利要求1的平坦的混合取向SOI衬底结构,其中,所述衬底是绝缘体。
26.权利要求8的平坦的混合取向SOI衬底结构,其中,所述至少二个清楚地确定的单晶含硅半导体区的至少一个包含设置在下残留含硅半导体上的上含硅半导体,所述上半导体和下半导体具有不同的表面取向,所述残留半导体与所述公共的埋置氧化物层直接接触。
27.权利要求26的平坦的混合取向SOI衬底结构,其中,所述不同的表面取向选自(110)、(111)和(100)。
28.权利要求27的平坦的混合取向SOI衬底结构,其中,第一含硅半导体区具有(100)晶向,而所述第二含硅半导体区具有(110)晶向。
29.权利要求28的平坦的混合取向SOI衬底结构,还包含至少一个nFET器件和至少一个pFET器件,其中,所述至少一个nFET器件位于所述(100)晶向上,而所述至少一个pFET器件位于所述(110)晶向上。
30.权利要求26的平坦的混合取向SOI衬底结构,还包含至少一个nFET器件和至少一个pFET器件,其中,所述至少一个nFET器件位于对所述器件最佳的晶向上,所述至少一个pFET器件位于对所述器件最佳的晶向上。
31.权利要求26的平坦的混合取向SOI衬底结构,还包含将所述至少二个清楚地确定的单晶含硅半导体区彼此分隔开的至少一个隔离区。
32.权利要求31的平坦的混合取向SOI衬底结构,其中,所述至少一个隔离区是沟槽隔离区。
33.权利要求31的平坦的混合取向SOI衬底结构,其中,所述至少一个隔离区至少向下延伸到至少公共埋置绝缘层的上表面。
34.权利要求31的平坦的混合取向SOI衬底结构,其中,所述至少一个隔离区不延伸到所述公共埋置氧化物层。
35.一种形成平坦的混合取向衬底的方法,它包含下列步骤:
形成双层模板叠层,它包含具有第一取向的第一下单晶半导体层以及具有与第一取向不同的第二取向的第二上单晶半导体层;
在选定的区域中对双层模板叠层的一个半导体层进行非晶化,以便形成局部非晶化区域;以及
用叠层的未被非晶化的半导体层作为模板,使局部非晶化的区域再结晶,从而将局部非晶化区域的取向从原来的取向改变成所希望的取向。
36.权利要求35的方法,其中,所述第一下单晶半导体层位于SOI衬底的绝缘层上。
37.权利要求35的方法,其中,所述第一下单晶半导体层包含单晶半导体衬底。
38.权利要求35的方法,其中,通过键合方法,所述第二上单晶半导体层被形成在第一下单晶半导体的顶部。
39.权利要求35的方法,其中,所述局部非晶化的区域主要被形成在第二上单晶半导体层中。
40.权利要求35的方法,其中,所述局部非晶化的区域主要被形成在第一下单晶半导体层中。
41.权利要求36的方法,其中,所述局部非晶化的区域主要被形成在第一下单晶半导体层中,且还包括采用诸如化学机械抛光之类的工艺,在再结晶之后清除所述顶部层的步骤。
42.权利要求35的方法,还包含形成至少一个沟槽隔离区以便将选定要非晶化的所述区域从未被选定要非晶化的区域分隔开的步骤,所述至少一个沟槽隔离区在非晶化之前、非晶化与再结晶之间、或部分在非晶化之后和部分在再结晶之后被形成。
43.权利要求35的方法,其中,所述第一下单晶半导体层和所述第二上单晶半导体层由选自Si、SiC、SiGe、SiGeC、Ge合金、Ge、C、GaAs、InAs、InP、它们的层状组合或合金、以及其它III-V或II-VI化合物半导体的相同的或不同的半导体材料组成。
44.权利要求35的方法,其中,所述第一下单晶半导体层和所述第二上单晶半导体层都由含硅的半导体材料组成。
45.权利要求35的方法,其中,所述第一下单晶半导体层和所述第二上单晶半导体层由应变半导体材料、非应变半导体材料、或应变半导体材料与非应变半导体材料的组合组成。
46.权利要求35的方法,其中,所述第一下单晶半导体层和所述第二上单晶半导体层具有选自(110)、(111)和(100)的不同的表面取向。
47.权利要求35的方法,还包含制作至少一个nFET器件和至少一个pFET器件,其中,所述至少一个nFET器件位于对所述器件最佳的晶向上,所述至少一个pFET器件位于对所述器件最佳的晶向上。
48.权利要求37的方法,还包含在所述再结晶步骤之后形成埋置的绝缘层。
49.权利要求48的方法,其中,所述埋置的绝缘层用氧离子注入分离方法来形成。
50.权利要求35的方法,其中,所述非晶化用离子注入方法来完成。
51.权利要求50的方法,其中,所述离子注入包含选自Si、Ge、Ar、C、O、N、H、He、Kr、Xe、P、B、As的离子。
52.权利要求50的方法,其中,所述离子注入包含选自Si和Ge的离子。
53.权利要求50的方法,其中,所述离子注入用图形化的掩模来执行。
54.权利要求35的方法,其中,所述再结晶在大约200-1300℃的温度下执行。
55.权利要求35的方法,其中,所述再结晶在选自N2、Ar、He、H2、以及它们的混合物的气体中执行。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/725,850 | 2003-12-02 | ||
US10/725,850 US20050116290A1 (en) | 2003-12-02 | 2003-12-02 | Planar substrate with selected semiconductor crystal orientations formed by localized amorphization and recrystallization of stacked template layers |
Publications (2)
Publication Number | Publication Date |
---|---|
CN1630087A true CN1630087A (zh) | 2005-06-22 |
CN100505273C CN100505273C (zh) | 2009-06-24 |
Family
ID=34620372
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CNB2004100923713A Expired - Fee Related CN100505273C (zh) | 2003-12-02 | 2004-11-09 | 平坦的混合取向衬底结构及其形成方法 |
Country Status (7)
Country | Link |
---|---|
US (2) | US20050116290A1 (zh) |
EP (1) | EP1702350A2 (zh) |
JP (1) | JP5063114B2 (zh) |
KR (1) | KR100961800B1 (zh) |
CN (1) | CN100505273C (zh) |
TW (1) | TWI328286B (zh) |
WO (1) | WO2005057631A2 (zh) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101331583B (zh) * | 2005-12-14 | 2010-09-29 | 飞思卡尔半导体公司 | 具有不同表面取向的soi活性层 |
CN102768983A (zh) * | 2012-07-12 | 2012-11-07 | 上海新傲科技股份有限公司 | 带有绝缘埋层的混合晶向衬底的制备方法 |
CN102768982A (zh) * | 2012-07-06 | 2012-11-07 | 上海新傲科技股份有限公司 | 带有绝缘埋层的混合晶向衬底的制备方法 |
CN102790084A (zh) * | 2011-05-16 | 2012-11-21 | 中国科学院上海微系统与信息技术研究所 | 锗和iii-v混合共平面的soi半导体结构及其制备方法 |
CN103946970A (zh) * | 2011-11-30 | 2014-07-23 | Soitec公司 | 限制缺陷形成的制备异质结构的工艺 |
Families Citing this family (119)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2004119943A (ja) * | 2002-09-30 | 2004-04-15 | Renesas Technology Corp | 半導体ウェハおよびその製造方法 |
US20050116290A1 (en) | 2003-12-02 | 2005-06-02 | De Souza Joel P. | Planar substrate with selected semiconductor crystal orientations formed by localized amorphization and recrystallization of stacked template layers |
US7291886B2 (en) * | 2004-06-21 | 2007-11-06 | International Business Machines Corporation | Hybrid substrate technology for high-mobility planar and multiple-gate MOSFETs |
US7253034B2 (en) * | 2004-07-29 | 2007-08-07 | International Business Machines Corporation | Dual SIMOX hybrid orientation technology (HOT) substrates |
US7354806B2 (en) * | 2004-09-17 | 2008-04-08 | International Business Machines Corporation | Semiconductor device structure with active regions having different surface directions and methods |
US7235433B2 (en) | 2004-11-01 | 2007-06-26 | Advanced Micro Devices, Inc. | Silicon-on-insulator semiconductor device with silicon layers having different crystal orientations and method of forming the silicon-on-insulator semiconductor device |
DE102004057764B4 (de) * | 2004-11-30 | 2013-05-16 | Advanced Micro Devices, Inc. | Verfahren zur Herstellung eines Substrats mit kristallinen Halbleitergebieten mit unterschiedlichen Eigenschaften, die über einem kristallinen Vollsubstrat angeordnet sind und damit hergestelltes Halbleiterbauelement |
US7393733B2 (en) * | 2004-12-01 | 2008-07-01 | Amberwave Systems Corporation | Methods of forming hybrid fin field-effect transistor structures |
US7422956B2 (en) * | 2004-12-08 | 2008-09-09 | Advanced Micro Devices, Inc. | Semiconductor device and method of making semiconductor device comprising multiple stacked hybrid orientation layers |
US7285473B2 (en) * | 2005-01-07 | 2007-10-23 | International Business Machines Corporation | Method for fabricating low-defect-density changed orientation Si |
US8138061B2 (en) * | 2005-01-07 | 2012-03-20 | International Business Machines Corporation | Quasi-hydrophobic Si-Si wafer bonding using hydrophilic Si surfaces and dissolution of interfacial bonding oxide |
US20060175659A1 (en) * | 2005-02-07 | 2006-08-10 | International Business Machines Corporation | A cmos structure for body ties in ultra-thin soi (utsoi) substrates |
US7547917B2 (en) * | 2005-04-06 | 2009-06-16 | International Business Machines Corporation | Inverted multilayer semiconductor device assembly |
US7250351B2 (en) * | 2005-04-14 | 2007-07-31 | International Business Machines Corporation | Enhanced silicon-on-insulator (SOI) transistors and methods of making enhanced SOI transistors |
US7291539B2 (en) * | 2005-06-01 | 2007-11-06 | International Business Machines Corporation | Amorphization/templated recrystallization method for hybrid orientation substrates |
US7358164B2 (en) * | 2005-06-16 | 2008-04-15 | International Business Machines Corporation | Crystal imprinting methods for fabricating substrates with thin active silicon layers |
US7473985B2 (en) * | 2005-06-16 | 2009-01-06 | International Business Machines Corporation | Hybrid oriented substrates and crystal imprinting methods for forming such hybrid oriented substrates |
US7439108B2 (en) * | 2005-06-16 | 2008-10-21 | International Business Machines Corporation | Coplanar silicon-on-insulator (SOI) regions of different crystal orientations and methods of making the same |
US7344962B2 (en) * | 2005-06-21 | 2008-03-18 | International Business Machines Corporation | Method of manufacturing dual orientation wafers |
US7217629B2 (en) * | 2005-07-15 | 2007-05-15 | International Business Machines Corporation | Epitaxial imprinting |
US20070040235A1 (en) * | 2005-08-19 | 2007-02-22 | International Business Machines Corporation | Dual trench isolation for CMOS with hybrid orientations |
DE102005052055B3 (de) * | 2005-10-31 | 2007-04-26 | Advanced Micro Devices, Inc., Sunnyvale | Eingebettete Verformungsschicht in dünnen SOI-Transistoren und Verfahren zur Herstellung desselben |
WO2007053382A1 (en) * | 2005-10-31 | 2007-05-10 | Advanced Micro Devices, Inc. | An embedded strain layer in thin soi transistors and a method of forming the same |
US7535089B2 (en) * | 2005-11-01 | 2009-05-19 | Massachusetts Institute Of Technology | Monolithically integrated light emitting devices |
US7986029B2 (en) * | 2005-11-08 | 2011-07-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Dual SOI structure |
US7569466B2 (en) * | 2005-12-16 | 2009-08-04 | International Business Machines Corporation | Dual metal gate self-aligned integration |
US7436034B2 (en) * | 2005-12-19 | 2008-10-14 | International Business Machines Corporation | Metal oxynitride as a pFET material |
US8319285B2 (en) * | 2005-12-22 | 2012-11-27 | Infineon Technologies Ag | Silicon-on-insulator chip having multiple crystal orientations |
US8530355B2 (en) * | 2005-12-23 | 2013-09-10 | Infineon Technologies Ag | Mixed orientation semiconductor device and method |
US7432567B2 (en) * | 2005-12-28 | 2008-10-07 | International Business Machines Corporation | Metal gate CMOS with at least a single gate metal and dual gate dielectrics |
US7833849B2 (en) | 2005-12-30 | 2010-11-16 | International Business Machines Corporation | Method of fabricating a semiconductor structure including one device region having a metal gate electrode located atop a thinned polygate electrode |
US7425497B2 (en) | 2006-01-20 | 2008-09-16 | International Business Machines Corporation | Introduction of metal impurity to change workfunction of conductive electrodes |
US7285452B2 (en) * | 2006-02-10 | 2007-10-23 | Sadaka Mariam G | Method to selectively form regions having differing properties and structure |
US7531392B2 (en) * | 2006-02-27 | 2009-05-12 | International Business Machines Corporation | Multi-orientation semiconductor-on-insulator (SOI) substrate, and method of fabricating same |
US20070215984A1 (en) * | 2006-03-15 | 2007-09-20 | Shaheen Mohamad A | Formation of a multiple crystal orientation substrate |
US7396407B2 (en) * | 2006-04-18 | 2008-07-08 | International Business Machines Corporation | Trench-edge-defect-free recrystallization by edge-angle-optimized solid phase epitaxy: method and applications to hybrid orientation substrates |
US7521307B2 (en) * | 2006-04-28 | 2009-04-21 | International Business Machines Corporation | CMOS structures and methods using self-aligned dual stressed layers |
US7452784B2 (en) | 2006-05-25 | 2008-11-18 | International Business Machines Corporation | Formation of improved SOI substrates using bulk semiconductor wafers |
US7435639B2 (en) * | 2006-05-31 | 2008-10-14 | Freescale Semiconductor, Inc. | Dual surface SOI by lateral epitaxial overgrowth |
US20080048269A1 (en) * | 2006-08-25 | 2008-02-28 | International Business Machines Corporation | Method of fabricating structure for integrated circuit incorporating hybrid orientation technology and trench isolation regions |
US7595232B2 (en) | 2006-09-07 | 2009-09-29 | International Business Machines Corporation | CMOS devices incorporating hybrid orientation technology (HOT) with embedded connectors |
US7820501B2 (en) * | 2006-10-11 | 2010-10-26 | International Business Machines Corporation | Decoder for a stationary switch machine |
US20080128821A1 (en) * | 2006-12-04 | 2008-06-05 | Texas Instruments Incorporated | Semiconductor Device Manufactured Using Passivation of Crystal Domain Interfaces in Hybrid Orientation Technology |
US20080164572A1 (en) * | 2006-12-21 | 2008-07-10 | Covalent Materials Corporation | Semiconductor substrate and manufacturing method thereof |
JP2008177529A (ja) * | 2006-12-21 | 2008-07-31 | Covalent Materials Corp | 半導体基板およびその製造方法 |
US20080169535A1 (en) * | 2007-01-12 | 2008-07-17 | International Business Machines Corporation | Sub-lithographic faceting for mosfet performance enhancement |
US8016941B2 (en) * | 2007-02-05 | 2011-09-13 | Infineon Technologies Ag | Method and apparatus for manufacturing a semiconductor |
US7611979B2 (en) * | 2007-02-12 | 2009-11-03 | International Business Machines Corporation | Metal gates with low charge trapping and enhanced dielectric reliability characteristics for high-k gate dielectric stacks |
US7608522B2 (en) * | 2007-03-11 | 2009-10-27 | United Microelectronics Corp. | Method for fabricating a hybrid orientation substrate |
US9034102B2 (en) * | 2007-03-29 | 2015-05-19 | United Microelectronics Corp. | Method of fabricating hybrid orientation substrate and structure of the same |
US20080248626A1 (en) * | 2007-04-05 | 2008-10-09 | International Business Machines Corporation | Shallow trench isolation self-aligned to templated recrystallization boundary |
US7651902B2 (en) * | 2007-04-20 | 2010-01-26 | International Business Machines Corporation | Hybrid substrates and methods for forming such hybrid substrates |
FR2915318B1 (fr) * | 2007-04-20 | 2009-07-17 | St Microelectronics Crolles 2 | Procede de realisation d'un circuit electronique integre a deux portions de couches actives ayant des orientations cristallines differentes |
US7750406B2 (en) * | 2007-04-20 | 2010-07-06 | International Business Machines Corporation | Design structure incorporating a hybrid substrate |
US7575968B2 (en) * | 2007-04-30 | 2009-08-18 | Freescale Semiconductor, Inc. | Inverse slope isolation and dual surface orientation integration |
US7547641B2 (en) * | 2007-06-05 | 2009-06-16 | International Business Machines Corporation | Super hybrid SOI CMOS devices |
FR2917235B1 (fr) * | 2007-06-06 | 2010-09-03 | Soitec Silicon On Insulator | Procede de realisation de composants hybrides. |
FR2913815A1 (fr) * | 2007-06-06 | 2008-09-19 | Soitec Silicon On Insulator | PROCEDE DE CO-INTEGRATION DE SEMI-CONDUCTEURS, EN PARTICULIER SOI ET GeOI OU GaAsOI |
US7989306B2 (en) * | 2007-06-29 | 2011-08-02 | International Business Machines Corporation | Method of forming alternating regions of Si and SiGe or SiGeC on a buried oxide layer on a substrate |
US20090008725A1 (en) * | 2007-07-03 | 2009-01-08 | International Business Machines Corporation | Method for deposition of an ultra-thin electropositive metal-containing cap layer |
FR2918793B1 (fr) * | 2007-07-11 | 2009-10-09 | Commissariat Energie Atomique | Procede de fabrication d'un substrat semiconducteur-sur- isolant pour la microelectronique et l'optoelectronique. |
US8803195B2 (en) * | 2007-08-02 | 2014-08-12 | Wisconsin Alumni Research Foundation | Nanomembrane structures having mixed crystalline orientations and compositions |
US7808020B2 (en) * | 2007-10-09 | 2010-10-05 | International Business Machines Corporation | Self-assembled sidewall spacer |
US8105960B2 (en) * | 2007-10-09 | 2012-01-31 | International Business Machines Corporation | Self-assembled sidewall spacer |
US7863712B2 (en) * | 2007-10-30 | 2011-01-04 | International Business Machines Corporation | Hybrid orientation semiconductor structure with reduced boundary defects and method of forming same |
US7696573B2 (en) * | 2007-10-31 | 2010-04-13 | International Business Machines Corporation | Multiple crystallographic orientation semiconductor structures |
US8043947B2 (en) * | 2007-11-16 | 2011-10-25 | Texas Instruments Incorporated | Method to eliminate re-crystallization border defects generated during solid phase epitaxy of a DSB substrate |
US8288756B2 (en) * | 2007-11-30 | 2012-10-16 | Advanced Micro Devices, Inc. | Hetero-structured, inverted-T field effect transistor |
WO2009095813A1 (en) * | 2008-01-28 | 2009-08-06 | Nxp B.V. | A method for fabricating a dual-orientation group-iv semiconductor substrate |
WO2009128776A1 (en) * | 2008-04-15 | 2009-10-22 | Vallin Oerjan | Hybrid wafers with hybrid-oriented layer |
US8241970B2 (en) | 2008-08-25 | 2012-08-14 | International Business Machines Corporation | CMOS with channel P-FinFET and channel N-FinFET having different crystalline orientations and parallel fins |
JP2010072209A (ja) * | 2008-09-17 | 2010-04-02 | Fuji Xerox Co Ltd | 静電荷像現像用トナー、静電荷像現像用トナーの製造方法、静電荷像現像用現像剤および画像形成装置 |
FR2938117B1 (fr) * | 2008-10-31 | 2011-04-15 | Commissariat Energie Atomique | Procede d'elaboration d'un substrat hybride ayant une couche continue electriquement isolante enterree |
FR2942674B1 (fr) * | 2009-02-27 | 2011-12-16 | Commissariat Energie Atomique | Procede d'elaboration d'un substrat hybride par recristallisation partielle d'une couche mixte |
US8227307B2 (en) * | 2009-06-24 | 2012-07-24 | International Business Machines Corporation | Method for removing threshold voltage adjusting layer with external acid diffusion process |
US8105892B2 (en) * | 2009-08-18 | 2012-01-31 | International Business Machines Corporation | Thermal dual gate oxide device integration |
US8022488B2 (en) | 2009-09-24 | 2011-09-20 | International Business Machines Corporation | High-performance FETs with embedded stressors |
US7943458B2 (en) * | 2009-10-06 | 2011-05-17 | International Business Machines Corporation | Methods for obtaining gate stacks with tunable threshold voltage and scaling |
US8288222B2 (en) | 2009-10-20 | 2012-10-16 | International Business Machines Corporation | Application of cluster beam implantation for fabricating threshold voltage adjusted FETs |
US8035141B2 (en) | 2009-10-28 | 2011-10-11 | International Business Machines Corporation | Bi-layer nFET embedded stressor element and integration to enhance drive current |
FR2954584B1 (fr) * | 2009-12-22 | 2013-07-19 | Commissariat Energie Atomique | Substrat hybride a isolation amelioree et procede de realisation simplifie d'un substrat hybride |
US8445974B2 (en) | 2010-01-07 | 2013-05-21 | International Business Machines Corporation | Asymmetric FET including sloped threshold voltage adjusting material layer and method of fabricating same |
US8299530B2 (en) | 2010-03-04 | 2012-10-30 | International Business Machines Corporation | Structure and method to fabricate pFETS with superior GIDL by localizing workfunction |
US8450807B2 (en) | 2010-03-09 | 2013-05-28 | International Business Machines Corporation | MOSFETs with reduced contact resistance |
KR101642834B1 (ko) | 2010-04-09 | 2016-08-11 | 삼성전자주식회사 | Leg 공정을 이용하여 벌크 실리콘 웨이퍼의 필요한 영역내에 soⅰ층을 형성하는 반도체 소자의 제조방법 |
US8236660B2 (en) | 2010-04-21 | 2012-08-07 | International Business Machines Corporation | Monolayer dopant embedded stressor for advanced CMOS |
US8299535B2 (en) | 2010-06-25 | 2012-10-30 | International Business Machines Corporation | Delta monolayer dopants epitaxy for embedded source/drain silicide |
US8361889B2 (en) | 2010-07-06 | 2013-01-29 | International Business Machines Corporation | Strained semiconductor-on-insulator by addition and removal of atoms in a semiconductor-on-insulator |
US8962417B2 (en) | 2010-10-15 | 2015-02-24 | International Business Machines Corporation | Method and structure for pFET junction profile with SiGe channel |
US8659054B2 (en) | 2010-10-15 | 2014-02-25 | International Business Machines Corporation | Method and structure for pFET junction profile with SiGe channel |
US8466473B2 (en) | 2010-12-06 | 2013-06-18 | International Business Machines Corporation | Structure and method for Vt tuning and short channel control with high k/metal gate MOSFETs |
US8564063B2 (en) | 2010-12-07 | 2013-10-22 | United Microelectronics Corp. | Semiconductor device having metal gate and manufacturing method thereof |
US8536656B2 (en) | 2011-01-10 | 2013-09-17 | International Business Machines Corporation | Self-aligned contacts for high k/metal gate process flow |
US8643115B2 (en) | 2011-01-14 | 2014-02-04 | International Business Machines Corporation | Structure and method of Tinv scaling for high κ metal gate technology |
US8432002B2 (en) * | 2011-06-28 | 2013-04-30 | International Business Machines Corporation | Method and structure for low resistive source and drain regions in a replacement metal gate process flow |
US9064808B2 (en) * | 2011-07-25 | 2015-06-23 | Synopsys, Inc. | Integrated circuit devices having features with reduced edge curvature and methods for manufacturing the same |
US8609550B2 (en) | 2011-09-08 | 2013-12-17 | Synopsys, Inc. | Methods for manufacturing integrated circuit devices having features with reduced edge curvature |
JP2014093319A (ja) * | 2012-10-31 | 2014-05-19 | Toshiba Corp | 半導体装置およびその製造方法 |
CN103871813A (zh) * | 2012-12-14 | 2014-06-18 | 中国科学院微电子研究所 | 一种半导体离子注入均匀性的改善方法 |
FR3003685B1 (fr) | 2013-03-21 | 2015-04-17 | St Microelectronics Crolles 2 | Procede de modification localisee des contraintes dans un substrat du type soi, en particulier fd soi, et dispositif correspondant |
US9059095B2 (en) | 2013-04-22 | 2015-06-16 | International Business Machines Corporation | Self-aligned borderless contacts using a photo-patternable dielectric material as a replacement contact |
US8999791B2 (en) | 2013-05-03 | 2015-04-07 | International Business Machines Corporation | Formation of semiconductor structures with variable gate lengths |
US9214567B2 (en) | 2013-09-06 | 2015-12-15 | Globalfoundries Inc. | Nanowire compatible E-fuse |
US8951868B1 (en) | 2013-11-05 | 2015-02-10 | International Business Machines Corporation | Formation of functional gate structures with different critical dimensions using a replacement gate process |
CN103745952B (zh) * | 2013-12-25 | 2016-04-06 | 上海新傲科技股份有限公司 | 带有绝缘埋层的混晶衬底的制备方法 |
US9595525B2 (en) | 2014-02-10 | 2017-03-14 | International Business Machines Corporation | Semiconductor device including nanowire transistors with hybrid channels |
US9093425B1 (en) | 2014-02-11 | 2015-07-28 | International Business Machines Corporation | Self-aligned liner formed on metal semiconductor alloy contacts |
US9184290B2 (en) | 2014-04-02 | 2015-11-10 | International Business Machines Corporation | Method of forming well-controlled extension profile in MOSFET by silicon germanium based sacrificial layer |
US9293375B2 (en) | 2014-04-24 | 2016-03-22 | International Business Machines Corporation | Selectively grown self-aligned fins for deep isolation integration |
US9490161B2 (en) | 2014-04-29 | 2016-11-08 | International Business Machines Corporation | Channel SiGe devices with multiple threshold voltages on hybrid oriented substrates, and methods of manufacturing same |
US9331076B2 (en) | 2014-05-02 | 2016-05-03 | International Business Machines Corporation | Group III nitride integration with CMOS technology |
US10056293B2 (en) * | 2014-07-18 | 2018-08-21 | International Business Machines Corporation | Techniques for creating a local interconnect using a SOI wafer |
US9412840B1 (en) | 2015-05-06 | 2016-08-09 | International Business Machines Corporation | Sacrificial layer for replacement metal semiconductor alloy contact formation |
US9666493B2 (en) | 2015-06-24 | 2017-05-30 | International Business Machines Corporation | Semiconductor device structure with 110-PFET and 111-NFET curent flow direction |
FR3076292B1 (fr) * | 2017-12-28 | 2020-01-03 | Commissariat A L'energie Atomique Et Aux Energies Alternatives | Procede de transfert d'une couche utile sur un substrat support |
US11139402B2 (en) | 2018-05-14 | 2021-10-05 | Synopsys, Inc. | Crystal orientation engineering to achieve consistent nanowire shapes |
US11011411B2 (en) * | 2019-03-22 | 2021-05-18 | International Business Machines Corporation | Semiconductor wafer having integrated circuits with bottom local interconnects |
US11264458B2 (en) | 2019-05-20 | 2022-03-01 | Synopsys, Inc. | Crystal orientation engineering to achieve consistent nanowire shapes |
US11854816B2 (en) * | 2021-08-27 | 2023-12-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor devices and methods of manufacturing thereof |
Family Cites Families (29)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4385937A (en) * | 1980-05-20 | 1983-05-31 | Tokyo Shibaura Denki Kabushiki Kaisha | Regrowing selectively formed ion amorphosized regions by thermal gradient |
JPS60154548A (ja) * | 1984-01-24 | 1985-08-14 | Fujitsu Ltd | 半導体装置の製造方法 |
US4768076A (en) * | 1984-09-14 | 1988-08-30 | Hitachi, Ltd. | Recrystallized CMOS with different crystal planes |
US4659392A (en) * | 1985-03-21 | 1987-04-21 | Hughes Aircraft Company | Selective area double epitaxial process for fabricating silicon-on-insulator structures for use with MOS devices and integrated circuits |
DE3688318T2 (de) * | 1985-12-19 | 1993-07-29 | Sumitomo Electric Industries | Feldeffekttransistor. |
US4775641A (en) * | 1986-09-25 | 1988-10-04 | General Electric Company | Method of making silicon-on-sapphire semiconductor devices |
US4816893A (en) * | 1987-02-24 | 1989-03-28 | Hughes Aircraft Company | Low leakage CMOS/insulator substrate devices and method of forming the same |
US4863877A (en) * | 1987-11-13 | 1989-09-05 | Kopin Corporation | Ion implantation and annealing of compound semiconductor layers |
JPH01162362A (ja) * | 1987-12-18 | 1989-06-26 | Fujitsu Ltd | 半導体装置の製造方法 |
JPH01162376A (ja) * | 1987-12-18 | 1989-06-26 | Fujitsu Ltd | 半導体装置の製造方法 |
JPH03285351A (ja) * | 1990-04-02 | 1991-12-16 | Oki Electric Ind Co Ltd | Cmis型半導体装置およびその製造方法 |
JPH04372166A (ja) * | 1991-06-21 | 1992-12-25 | Matsushita Electric Ind Co Ltd | 半導体装置の製造方法 |
FR2681472B1 (fr) | 1991-09-18 | 1993-10-29 | Commissariat Energie Atomique | Procede de fabrication de films minces de materiau semiconducteur. |
JP3017860B2 (ja) * | 1991-10-01 | 2000-03-13 | 株式会社東芝 | 半導体基体およびその製造方法とその半導体基体を用いた半導体装置 |
JP3156878B2 (ja) * | 1992-04-30 | 2001-04-16 | 株式会社東芝 | 半導体装置およびその製造方法 |
US5554562A (en) * | 1995-04-06 | 1996-09-10 | Advanced Micro Devices, Inc. | Advanced isolation scheme for deep submicron technology |
US5888872A (en) * | 1997-06-20 | 1999-03-30 | Advanced Micro Devices, Inc. | Method for forming source drain junction areas self-aligned between a sidewall spacer and an etched lateral sidewall |
US5882987A (en) | 1997-08-26 | 1999-03-16 | International Business Machines Corporation | Smart-cut process for the production of thin semiconductor material films |
JP4521542B2 (ja) * | 1999-03-30 | 2010-08-11 | ルネサスエレクトロニクス株式会社 | 半導体装置および半導体基板 |
EP1073112A1 (en) * | 1999-07-26 | 2001-01-31 | STMicroelectronics S.r.l. | Process for the manufacturing of a SOI wafer by oxidation of buried cavities |
US6229187B1 (en) * | 1999-10-20 | 2001-05-08 | Advanced Micro Devices, Inc. | Field effect transistor with non-floating body and method for forming same on a bulk silicon wafer |
US6407425B1 (en) * | 2000-09-21 | 2002-06-18 | Texas Instruments Incorporated | Programmable neuron MOSFET on SOI |
US6782759B2 (en) * | 2001-07-09 | 2004-08-31 | Nartron Corporation | Anti-entrapment system |
JP3782021B2 (ja) * | 2002-02-22 | 2006-06-07 | 株式会社東芝 | 半導体装置、半導体装置の製造方法、半導体基板の製造方法 |
US6902962B2 (en) * | 2003-04-04 | 2005-06-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Silicon-on-insulator chip with multiple crystal orientations |
US7329923B2 (en) | 2003-06-17 | 2008-02-12 | International Business Machines Corporation | High-performance CMOS devices on hybrid crystal oriented substrates |
US6815278B1 (en) * | 2003-08-25 | 2004-11-09 | International Business Machines Corporation | Ultra-thin silicon-on-insulator and strained-silicon-direct-on-insulator with hybrid crystal orientations |
US7023055B2 (en) | 2003-10-29 | 2006-04-04 | International Business Machines Corporation | CMOS on hybrid substrate with different crystal orientations using silicon-to-silicon direct wafer bonding |
US20050116290A1 (en) | 2003-12-02 | 2005-06-02 | De Souza Joel P. | Planar substrate with selected semiconductor crystal orientations formed by localized amorphization and recrystallization of stacked template layers |
-
2003
- 2003-12-02 US US10/725,850 patent/US20050116290A1/en not_active Abandoned
-
2004
- 2004-11-09 CN CNB2004100923713A patent/CN100505273C/zh not_active Expired - Fee Related
- 2004-11-12 TW TW093134666A patent/TWI328286B/zh not_active IP Right Cessation
- 2004-11-30 KR KR1020067010604A patent/KR100961800B1/ko not_active IP Right Cessation
- 2004-11-30 EP EP04812491A patent/EP1702350A2/en not_active Withdrawn
- 2004-11-30 WO PCT/US2004/039970 patent/WO2005057631A2/en active Application Filing
- 2004-11-30 JP JP2006542666A patent/JP5063114B2/ja not_active Expired - Fee Related
-
2006
- 2006-12-04 US US11/566,579 patent/US7785939B2/en not_active Expired - Fee Related
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101331583B (zh) * | 2005-12-14 | 2010-09-29 | 飞思卡尔半导体公司 | 具有不同表面取向的soi活性层 |
CN102790084A (zh) * | 2011-05-16 | 2012-11-21 | 中国科学院上海微系统与信息技术研究所 | 锗和iii-v混合共平面的soi半导体结构及其制备方法 |
CN102790084B (zh) * | 2011-05-16 | 2016-03-16 | 中国科学院上海微系统与信息技术研究所 | 锗和iii-v混合共平面的soi半导体结构及其制备方法 |
CN103946970A (zh) * | 2011-11-30 | 2014-07-23 | Soitec公司 | 限制缺陷形成的制备异质结构的工艺 |
CN103946970B (zh) * | 2011-11-30 | 2017-07-25 | Soitec公司 | 限制缺陷形成的制备异质结构的工艺 |
CN102768982A (zh) * | 2012-07-06 | 2012-11-07 | 上海新傲科技股份有限公司 | 带有绝缘埋层的混合晶向衬底的制备方法 |
CN102768983A (zh) * | 2012-07-12 | 2012-11-07 | 上海新傲科技股份有限公司 | 带有绝缘埋层的混合晶向衬底的制备方法 |
Also Published As
Publication number | Publication date |
---|---|
US7785939B2 (en) | 2010-08-31 |
US20080108184A1 (en) | 2008-05-08 |
KR100961800B1 (ko) | 2010-06-08 |
WO2005057631A2 (en) | 2005-06-23 |
TWI328286B (en) | 2010-08-01 |
KR20060130572A (ko) | 2006-12-19 |
WO2005057631A3 (en) | 2007-05-10 |
CN100505273C (zh) | 2009-06-24 |
JP5063114B2 (ja) | 2012-10-31 |
US20050116290A1 (en) | 2005-06-02 |
EP1702350A2 (en) | 2006-09-20 |
TW200529423A (en) | 2005-09-01 |
JP2007535802A (ja) | 2007-12-06 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN100505273C (zh) | 平坦的混合取向衬底结构及其形成方法 | |
US9275910B2 (en) | Semiconductor-on-insulator structure and method of fabricating the same | |
TWI364095B (en) | Finfet having improved carrier mobility and method of its formation | |
US7915148B2 (en) | Method of producing a tensioned layer on a substrate | |
US7812340B2 (en) | Strained-silicon-on-insulator single-and double-gate MOSFET and method for forming the same | |
US7060585B1 (en) | Hybrid orientation substrates by in-place bonding and amorphization/templated recrystallization | |
CN101233606B (zh) | 用于制造受应力的mos器件的方法 | |
CN1691350A (zh) | 在体硅和soi mos器件中制造无位错应力沟道的结构和方法 | |
CN101828260A (zh) | 在体半导体晶片中制造局域化绝缘体上半导体(soi)结构的方法 | |
JP4948785B2 (ja) | シリコン単結晶基板中に、mosfetデバイスのための接合を形成するための方法 | |
CN1728362A (zh) | 一种形成集成半导体结构的方法 | |
CN1828908A (zh) | 半导体结构及制造半导体结构的方法 | |
CN1836323A (zh) | 混合晶向衬底上的高性能cmos soi器件 | |
TW200303073A (en) | Method for porducing CMOS device | |
CN1897286A (zh) | 半导体结构及其制造方法 | |
US20050217566A1 (en) | Method for producing one or more monocrystalline layers, each with a different lattice structure, on one plane of a series of layers | |
US20070228384A1 (en) | Single-crystal layer on a dielectric layer | |
US6642536B1 (en) | Hybrid silicon on insulator/bulk strained silicon technology | |
CN100361302C (zh) | 混合衬底、集成半导体结构以及它们的制备方法 | |
CN101313394A (zh) | 制造半导体器件的方法以及用该方法获得的半导体器件 | |
US7312125B1 (en) | Fully depleted strained semiconductor on insulator transistor and method of making the same | |
KR100529633B1 (ko) | 에피택셜 실리콘을 이용한 반도체 소자 및 그 제조 방법 | |
JP2002270509A5 (zh) | ||
JP4325134B2 (ja) | 半導体基板の製造方法及び電界効果型トランジスタの製造方法 | |
EP4287239A1 (en) | A low loss semiconductor substrate |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
C17 | Cessation of patent right | ||
CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20090624 Termination date: 20101109 |