JP5063114B2 - プレーナ型ハイブリッド配向基板を形成する方法 - Google Patents
プレーナ型ハイブリッド配向基板を形成する方法 Download PDFInfo
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- 239000000758 substrate Substances 0.000 title claims description 125
- 238000000034 method Methods 0.000 title claims description 87
- 239000004065 semiconductor Substances 0.000 claims description 145
- 239000013078 crystal Substances 0.000 claims description 93
- 238000002955 isolation Methods 0.000 claims description 22
- 238000001953 recrystallisation Methods 0.000 claims description 19
- 238000005280 amorphization Methods 0.000 claims description 17
- 239000000463 material Substances 0.000 claims description 11
- 238000005468 ion implantation Methods 0.000 claims description 9
- 229910052760 oxygen Inorganic materials 0.000 claims description 8
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 6
- 239000001301 oxygen Substances 0.000 claims description 6
- 150000002500 ions Chemical class 0.000 claims description 5
- 229910052710 silicon Inorganic materials 0.000 claims description 5
- 229910052734 helium Inorganic materials 0.000 claims description 4
- 229910052739 hydrogen Inorganic materials 0.000 claims description 4
- 229910052757 nitrogen Inorganic materials 0.000 claims description 4
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 3
- 229910045601 alloy Inorganic materials 0.000 claims description 3
- 239000000956 alloy Substances 0.000 claims description 3
- 229910052786 argon Inorganic materials 0.000 claims description 3
- 239000007789 gas Substances 0.000 claims description 3
- 229910052732 germanium Inorganic materials 0.000 claims description 3
- 238000000926 separation method Methods 0.000 claims description 3
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims description 2
- 229910000673 Indium arsenide Inorganic materials 0.000 claims description 2
- 229910003811 SiGeC Inorganic materials 0.000 claims description 2
- 229910052785 arsenic Inorganic materials 0.000 claims description 2
- 229910052796 boron Inorganic materials 0.000 claims description 2
- 229910052799 carbon Inorganic materials 0.000 claims description 2
- 150000001875 compounds Chemical class 0.000 claims description 2
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 claims description 2
- 229910052743 krypton Inorganic materials 0.000 claims description 2
- 239000000203 mixture Substances 0.000 claims description 2
- 229910003465 moissanite Inorganic materials 0.000 claims description 2
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 2
- 229910000927 Ge alloy Inorganic materials 0.000 claims 1
- 238000004519 manufacturing process Methods 0.000 description 16
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 14
- 238000000137 annealing Methods 0.000 description 8
- 238000002513 implantation Methods 0.000 description 7
- 238000010849 ion bombardment Methods 0.000 description 6
- 239000012535 impurity Substances 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 238000005498 polishing Methods 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 1
- 108091006149 Electron carriers Proteins 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 229910021488 crystalline silicon dioxide Inorganic materials 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 230000002209 hydrophobic effect Effects 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000005224 laser annealing Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229910021426 porous silicon Inorganic materials 0.000 description 1
- 238000004151 rapid thermal annealing Methods 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 238000009279 wet oxidation reaction Methods 0.000 description 1
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Description
第1の配向を有する第1の下部単結晶半導体層(又は基板)と、第1の配向とは異なる第2の配向を有する第2の上部(一般的には、接合された)単結晶半導体層とからなる二層テンプレート層スタックを形成するステップ、
選択された領域において二層テンプレート・スタックの層の一方をアモルファス化し(例えば、マスクを通してイオン注入によって)、局部的なアモルファス化領域を形成するステップ、及び
テンプレートとしてアモルファス化されていないスタックの層を用いて、局部的なアモルファス化領域を再結晶化し、これにより該局部的なアモルファス化領域の配向を元の配向から所望の配向に変えるステップである。
第1の配向を有する第1の下部単結晶半導体層(又は基板)と、第1の配向とは異なる第2の配向を有する第2の上部(一般的には、接合された)単結晶半導体層からなる二層テンプレート層スタックを形成するステップ、
選択された領域において二層テンプレート・スタックの層の一方をアモルファス化し、局部的なアモルファス化領域を形成するステップ、及び
テンプレートとしてアモルファス化されていないスタックの層を用いて、局部的なアモルファス化領域を再結晶化し、これにより該局部的なアモルファス化領域の配向を元の配向から所望の配向に変えるステップである。
Claims (17)
- プレーナ型ハイブリッド配向基板を形成する方法であって、
埋め込み絶縁層上に形成され第1の結晶配向を有する第1の下部単結晶半導体層、及び該第1の下部単結晶半導体層の上に形成され前記第1の結晶配向と異なる第2の結晶配向を有する第2の上部単結晶半導体層を有する二層テンプレート・スタックを準備するステップと、
前記埋込み絶縁層から前記第1の下部単結晶半導体層を通り前記第2の上部単結晶半導体層内に部分的に延びる局部的なアモルファス化領域を形成するように、前記第1の下部単結晶半導体層の一部と前記第2の上部単結晶半導体層の一部とをアモルファス化するステップと、
前記第2の上部単結晶半導体層をテンプレートとして使用して前記局部的なアモルファス化領域を再結晶化することにより、前記第2の上部単結晶半導体層の前記第2の結晶配向を有する単結晶半導体領域を形成するステップと、
前記第2の上部単結晶半導体層を除去して、同一平面の前記第1の下部単結晶半導体層及び前記単結晶半導体領域を残すステップとを含む方法。 - 前記第2の上部単結晶半導体層が、接合によって前記第1の下部単結晶半導体の上に形成される、請求項1に記載の方法。
- 前記アモルファス化するステップの前に、
前記局部的なアモルファス化領域を形成するための少なくとも前記第2の上部単結晶半導体層の一部と該一部に隣接する残りの部分との間に、トレンチ分離領域を形成するステップを行う、請求項1に記載の方法。 - 前記アモルファス化するステップと前記単結晶半導体領域を形成するステップの間に、
前記局部的なアモルファス化領域と該局部的なアモルファス化領域に隣接する部分との間に、トレンチ分離領域を形成するステップを行う、請求項1に記載の方法。 - 前記アモルファス化するステップの後に、前記局部的なアモルファス化領域と該局部的なアモルファス化領域に隣接する部分との間に、トレンチ分離領域のトレンチを形成するステップを行い、
前記単結晶半導体領域を形成するステップの後に前記トレンチを充填して前記トレンチ分離領域を形成するステップを行う、請求項1に記載の方法。 - 前記二層テンプレート・スタックは、基板上に形成される、請求項1に記載の方法。
- 前記第1の下部単結晶半導体層及び前記第2の上部単結晶半導体層は、Si、SiC、SiGe、SiGeC、Ge合金、Ge、C、GaAs、InAs、InP、これらの層状の組み合わせ又はこれらの合金、及び、他のIII−V族又はII−VI族化合物半導体からなる群から選択された同じ半導体材料又は異なる半導体材料から構成される、請求項1に記載の方法。
- 前記第1の下部単結晶半導体層及び前記第2の上部単結晶半導体層の両方が、Si半導体材料から構成される、請求項1に記載の方法。
- 前記第1の下部単結晶半導体層及び前記第2の上部単結晶半導体層が、歪み半導体材料、非歪み半導体材料、又は歪み半導体材料と非歪み半導体材料の組み合わせから構成される、請求項1に記載の方法。
- 前記第1の下部単結晶半導体層及び前記第2の上部単結晶半導体層が、(110)、(111)、及び(100)から選択される異なる結晶配向を有する、請求項1に記載の方法。
- 前記第1の下部単結晶半導体層の前記第1の結晶配向が(100)であり、前記単結晶半導体領域の前記第2の結晶配向が(110)であり、前記第1の下部単結晶半導体層にnFETを形成し、前記単結晶半導体領域にpFETを形成するステップを含む、請求項1に記載の方法。
- 前記第1の下部単結晶半導体層の前記第1の結晶配向が(110)であり、前記単結晶半導体領域の前記第2の結晶配向が(100)であり、前記第1の下部単結晶半導体層にpFETを形成し、前記単結晶半導体領域にnFETを形成するステップを含む、請求項1に記載の方法。
- 前記埋め込み絶縁層は、酸素のイオン注入による分離(SIMOX)プロセスによって形成される、請求項1に記載の方法。
- 前記アモルファス化するステップは、イオン注入によって達成される、請求項1に記載の方法。
- 前記イオン注入は、Si、Ge、Ar、C、O、N、H、He、Kr、Xe、P、B、及びAsからなる群から選択されるイオンを含む、請求項14に記載の方法。
- 前記再結晶化するステップが、200℃から1300℃までの温度で行われる、請求項1に記載の方法。
- 前記再結晶化するステップは、N2、Ar、He、H2、及びこれらの混合物からなる群から選択されるガス内で行われる、請求項1に記載の方法。
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-
2003
- 2003-12-02 US US10/725,850 patent/US20050116290A1/en not_active Abandoned
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2004
- 2004-11-09 CN CNB2004100923713A patent/CN100505273C/zh not_active Expired - Fee Related
- 2004-11-12 TW TW093134666A patent/TWI328286B/zh not_active IP Right Cessation
- 2004-11-30 KR KR1020067010604A patent/KR100961800B1/ko not_active IP Right Cessation
- 2004-11-30 WO PCT/US2004/039970 patent/WO2005057631A2/en active Application Filing
- 2004-11-30 EP EP04812491A patent/EP1702350A2/en not_active Withdrawn
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Also Published As
Publication number | Publication date |
---|---|
EP1702350A2 (en) | 2006-09-20 |
TW200529423A (en) | 2005-09-01 |
CN100505273C (zh) | 2009-06-24 |
US20080108184A1 (en) | 2008-05-08 |
TWI328286B (en) | 2010-08-01 |
CN1630087A (zh) | 2005-06-22 |
KR100961800B1 (ko) | 2010-06-08 |
US20050116290A1 (en) | 2005-06-02 |
US7785939B2 (en) | 2010-08-31 |
KR20060130572A (ko) | 2006-12-19 |
WO2005057631A3 (en) | 2007-05-10 |
WO2005057631A2 (en) | 2005-06-23 |
JP2007535802A (ja) | 2007-12-06 |
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