FR2917235B1 - Procede de realisation de composants hybrides. - Google Patents

Procede de realisation de composants hybrides.

Info

Publication number
FR2917235B1
FR2917235B1 FR0755531A FR0755531A FR2917235B1 FR 2917235 B1 FR2917235 B1 FR 2917235B1 FR 0755531 A FR0755531 A FR 0755531A FR 0755531 A FR0755531 A FR 0755531A FR 2917235 B1 FR2917235 B1 FR 2917235B1
Authority
FR
France
Prior art keywords
producing hybrid
hybrid components
components
producing
hybrid
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR0755531A
Other languages
English (en)
Other versions
FR2917235A1 (fr
Inventor
Thomas Signamarcheix
Frank Fournel
Hubert Moriceau
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Soitec SA
Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
Original Assignee
Commissariat a lEnergie Atomique CEA
Soitec SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to FR0755531A priority Critical patent/FR2917235B1/fr
Application filed by Commissariat a lEnergie Atomique CEA, Soitec SA filed Critical Commissariat a lEnergie Atomique CEA
Priority to CN200880101633.4A priority patent/CN101779283B/zh
Priority to EP08760680.2A priority patent/EP2153462B1/fr
Priority to SG2011057833A priority patent/SG174068A1/en
Priority to PCT/EP2008/057110 priority patent/WO2008148882A2/fr
Priority to KR1020107000163A priority patent/KR101525611B1/ko
Priority to JP2010510822A priority patent/JP5801053B2/ja
Priority to US12/663,096 priority patent/US8871607B2/en
Publication of FR2917235A1 publication Critical patent/FR2917235A1/fr
Application granted granted Critical
Publication of FR2917235B1 publication Critical patent/FR2917235B1/fr
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/8258—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using a combination of technologies covered by H01L21/8206, H01L21/8213, H01L21/822, H01L21/8252, H01L21/8254 or H01L21/8256
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823878—Complementary field-effect transistors, e.g. CMOS isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Recrystallisation Techniques (AREA)
  • Compounds Of Alkaline-Earth Elements, Aluminum Or Rare-Earth Metals (AREA)
  • Inorganic Insulating Materials (AREA)
FR0755531A 2007-06-06 2007-06-06 Procede de realisation de composants hybrides. Expired - Fee Related FR2917235B1 (fr)

Priority Applications (8)

Application Number Priority Date Filing Date Title
FR0755531A FR2917235B1 (fr) 2007-06-06 2007-06-06 Procede de realisation de composants hybrides.
EP08760680.2A EP2153462B1 (fr) 2007-06-06 2008-06-06 Procédé de fabrication de composants hybrides
SG2011057833A SG174068A1 (en) 2007-06-06 2008-06-06 Method for producing hybrid components
PCT/EP2008/057110 WO2008148882A2 (fr) 2007-06-06 2008-06-06 Procédé de fabrication de composants hybrides
CN200880101633.4A CN101779283B (zh) 2007-06-06 2008-06-06 制备混合组件的方法
KR1020107000163A KR101525611B1 (ko) 2007-06-06 2008-06-06 하이브리드 부품들의 제조 방법
JP2010510822A JP5801053B2 (ja) 2007-06-06 2008-06-06 ハイブリッド構成要素の製造方法
US12/663,096 US8871607B2 (en) 2007-06-06 2008-06-06 Method for producing hybrid components

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR0755531A FR2917235B1 (fr) 2007-06-06 2007-06-06 Procede de realisation de composants hybrides.

Publications (2)

Publication Number Publication Date
FR2917235A1 FR2917235A1 (fr) 2008-12-12
FR2917235B1 true FR2917235B1 (fr) 2010-09-03

Family

ID=39033751

Family Applications (1)

Application Number Title Priority Date Filing Date
FR0755531A Expired - Fee Related FR2917235B1 (fr) 2007-06-06 2007-06-06 Procede de realisation de composants hybrides.

Country Status (8)

Country Link
US (1) US8871607B2 (fr)
EP (1) EP2153462B1 (fr)
JP (1) JP5801053B2 (fr)
KR (1) KR101525611B1 (fr)
CN (1) CN101779283B (fr)
FR (1) FR2917235B1 (fr)
SG (1) SG174068A1 (fr)
WO (1) WO2008148882A2 (fr)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7767546B1 (en) 2009-01-12 2010-08-03 International Business Machines Corporation Low cost fabrication of double box back gate silicon-on-insulator wafers with built-in shallow trench isolation in back gate layer
US20100176482A1 (en) 2009-01-12 2010-07-15 International Business Machine Corporation Low cost fabrication of double box back gate silicon-on-insulator wafers with subsequent self aligned shallow trench isolation
FR2942674B1 (fr) 2009-02-27 2011-12-16 Commissariat Energie Atomique Procede d'elaboration d'un substrat hybride par recristallisation partielle d'une couche mixte
EP2254148B1 (fr) * 2009-05-18 2011-11-30 S.O.I.Tec Silicon on Insulator Technologies Procédé de fabrication d'un substrat semi-conducteur hybride
US8587063B2 (en) * 2009-11-06 2013-11-19 International Business Machines Corporation Hybrid double box back gate silicon-on-insulator wafers with enhanced mobility channels
US8367519B2 (en) * 2009-12-30 2013-02-05 Memc Electronic Materials, Inc. Method for the preparation of a multi-layered crystalline structure
WO2011123199A1 (fr) * 2010-03-31 2011-10-06 S.O.I.Tec Silicon On Insulator Technologies Structures semi-conductrices soudées et leur procédé de formation
US8912055B2 (en) 2011-05-03 2014-12-16 Imec Method for manufacturing a hybrid MOSFET device and hybrid MOSFET obtainable thereby
FR3007892B1 (fr) 2013-06-27 2015-07-31 Commissariat Energie Atomique Procede de transfert d'une couche mince avec apport d'energie thermique a une zone fragilisee via une couche inductive
KR102203033B1 (ko) * 2013-12-18 2021-01-14 인텔 코포레이션 평면형 이종 디바이스
US9601571B2 (en) * 2014-10-02 2017-03-21 Taiwan Semiconductor Manufacturing Company Limited Nanowire fabrication method and structure thereof
FR3040108B1 (fr) 2015-08-12 2017-08-11 Commissariat Energie Atomique Procede de fabrication d'une structure semi-conductrice avec collage direct temporaire exploitant une couche poreuse
CN106653676B (zh) * 2015-11-03 2019-12-24 中芯国际集成电路制造(上海)有限公司 衬底结构、半导体器件以及制造方法
JP7051288B2 (ja) * 2015-12-21 2022-04-11 キヤノン株式会社 造形装置、および造形用データを生成するためのデータ処理装置、および立体物の製造方法
FR3091032B1 (fr) * 2018-12-20 2020-12-11 Soitec Silicon On Insulator Procédé de transfert d’une couche superficielle sur des cavités
US20230090017A1 (en) * 2021-09-20 2023-03-23 International Business Machines Corporation Semiconductor structure with different crystalline orientations

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4956313A (en) 1987-08-17 1990-09-11 International Business Machines Corporation Via-filling and planarization technique
JPH06163677A (ja) 1992-11-20 1994-06-10 Nippondenso Co Ltd 半導体装置の製造方法
JP4202563B2 (ja) 1999-11-18 2008-12-24 株式会社東芝 半導体装置
US6815278B1 (en) * 2003-08-25 2004-11-09 International Business Machines Corporation Ultra-thin silicon-on-insulator and strained-silicon-direct-on-insulator with hybrid crystal orientations
JP2005150403A (ja) * 2003-11-14 2005-06-09 Fujitsu Ltd 半導体装置の製造方法
US20050116290A1 (en) * 2003-12-02 2005-06-02 De Souza Joel P. Planar substrate with selected semiconductor crystal orientations formed by localized amorphization and recrystallization of stacked template layers
US7094634B2 (en) * 2004-06-30 2006-08-22 International Business Machines Corporation Structure and method for manufacturing planar SOI substrate with multiple orientations
US7253034B2 (en) * 2004-07-29 2007-08-07 International Business Machines Corporation Dual SIMOX hybrid orientation technology (HOT) substrates
US7271043B2 (en) * 2005-01-18 2007-09-18 International Business Machines Corporation Method for manufacturing strained silicon directly-on-insulator substrate with hybrid crystalline orientation and different stress levels
US7282425B2 (en) * 2005-01-31 2007-10-16 International Business Machines Corporation Structure and method of integrating compound and elemental semiconductors for high-performance CMOS
US7439108B2 (en) * 2005-06-16 2008-10-21 International Business Machines Corporation Coplanar silicon-on-insulator (SOI) regions of different crystal orientations and methods of making the same
US7638842B2 (en) * 2005-09-07 2009-12-29 Amberwave Systems Corporation Lattice-mismatched semiconductor structures on insulators
US7348633B2 (en) 2005-11-18 2008-03-25 International Business Machines Corporation Hybrid crystallographic surface orientation substrate having one or more SOI regions and/or bulk semiconductor regions
FR2906078B1 (fr) 2006-09-19 2009-02-13 Commissariat Energie Atomique Procede de fabrication d'une structure micro-technologique mixte et une structure ainsi obtenue

Also Published As

Publication number Publication date
WO2008148882A2 (fr) 2008-12-11
EP2153462A2 (fr) 2010-02-17
JP2010529666A (ja) 2010-08-26
JP5801053B2 (ja) 2015-10-28
KR20100040285A (ko) 2010-04-19
WO2008148882A3 (fr) 2009-07-23
CN101779283B (zh) 2014-06-11
CN101779283A (zh) 2010-07-14
SG174068A1 (en) 2011-09-29
EP2153462B1 (fr) 2018-08-01
KR101525611B1 (ko) 2015-06-03
US8871607B2 (en) 2014-10-28
US20110163410A1 (en) 2011-07-07
FR2917235A1 (fr) 2008-12-12

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