CN1604306A - 具有制作在不同晶向晶片上的器件层的三维cmos集成电路 - Google Patents

具有制作在不同晶向晶片上的器件层的三维cmos集成电路 Download PDF

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CN1604306A
CN1604306A CNA2004100798836A CN200410079883A CN1604306A CN 1604306 A CN1604306 A CN 1604306A CN A2004100798836 A CNA2004100798836 A CN A2004100798836A CN 200410079883 A CN200410079883 A CN 200410079883A CN 1604306 A CN1604306 A CN 1604306A
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陈永聪
凯瑟琳·W·瓜里尼
杨美基
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GlobalFoundries Inc
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Abstract

提供了一种制造3D集成电路的三维(3D)集成方案，其中，pFET位于对其最佳的晶面上，且nFET位于对其最佳的晶面上。根据本发明的第一3D集成方案，第一半导体器件被预先制作在第一绝缘体上硅(SOI)衬底的半导体表面上，且第二半导体器件被预先制作在第二SOI衬底的半导体表面上。在预先制作这二种结构之后，此二种结构被键合到一起，并经由穿过通孔的晶片－通道被互连。在第二3D集成方案中，具有第一结晶学取向的第一SOI层的覆盖绝缘体上硅(SOI)衬底，被键合到结晶学取向不同于第一SOI层的第二SOI层上具有第二半导体器件的预先制造的晶片的表面；以及在第一SOI层上制作第一半导体器件。

Description

具有制作在不同晶向晶片上的 器件层的三维CMOS集成电路
技术领域
本发明涉及到互补金属氧化物半导体(CMOS)集成电路，更确切地说是涉及到具有制作在不同晶向晶片上的半导体器件层的三维CMOS集成电路。
背景技术
在当前的半导体技术中，诸如nFET或pFET之类的CMOS器件典型地被制造在诸如硅的具有单个晶向的半导体晶片上。特别是大多数当今半导体器件被制作在具有(100)晶向的硅上。
已知电子在(100)硅表面取向中具有高的迁移率，但空穴在(110)表面取向中具有高的迁移率。亦即，(100)硅上的空穴迁移率大约比这一晶向的相应电子迁移率低2-4倍。为了补偿这一差异，pFET通常被设计成具有较大的宽度，以便使上拉电流与nFET的下拉电流平衡并得到均匀的电路转换，具有较大宽度的pFET由于占据很大的芯片面积而不可取。
另一方面，(110)硅上的空穴迁移率比(100)硅上的大2倍；因此，制作在(110)表面上的pFET表现出明显高于制作在(100)表面上的pFET的驱动电流。不幸的是，(110)硅表面上的电子迁移率明显地低于(100)硅表面上的。
如从上述讨论能够推测到那样，(110)硅表面由于优异的空穴迁移率而对pFET器件是最佳的，但这一晶向对nFET器件是完全不合适的。代之以(100)硅表面由于晶向有利于电子迁移率而对nFET器件是最佳的。
用传统的CMOS器件和互连按比例缩小来达到主要集成电路(IC)性能的提高，变得更为困难。引入到IC制造前端和后端的新材料正使性能得以继续提高，但这些改进仅仅可以提供一时或短时间的提高，可能很快就达到基本的物理限度。
存在着几种现有技术的方法当前被用来制造三维集成电路。在一种现有技术的方法中，最下面的器件层被制造在体衬底或绝缘体上硅(SOI)衬底上，然后形成第二器件层。第二器件层可以用外延硅生长来形成。例如在论文S.Pae，et al.，”Multiple layers ofsilicon-on-insulator island fabrication by selective eoitaxial growth”，IEEE Elec.Dev.Lett 20：196-196(1999)中，描述了这种方法。形成第二器件层的另一现有技术方法是利用非晶硅层的再结晶。例如在论文V.Subramanian，et al.，”High performance Germanium seededlaterally crystallized TFTs for vertical device integration”，IEEETrans.Electron Devices 45，1934-1939(1998)；T.Kunio，et al.，“Threedimensional IC’s hanving four stacked active device layers”，IEDMTech Dig 837-840(1989)；以及V.W.C.Chen，et al.，“Three-dimensional CMOS SOI integrated circuit usinghigh-temperature metal-induced lateral crystallization”，IEEE TransElec Dev 48：1394-1399(2001)中，描述了这种方法。
随后的工艺则可以在这种现有技术方法中执行，以便制造额外的有源器件和互连布线。以这种方式制造的电路存在着二个主要缺点：(1)再结晶的顶层常常具有很差的电学特性，可能导致较低级的器件和电路性能；还难以控制再结晶层的表面取向；(2)从顶层形成到随后的器件制造的热循环降低了下方器件的性能。
在某些现有技术方法中，用晶片键合方法来得到三维集成电路。例如在论文R.J.Gutmann，et al.，“Three dimensional(3D)ICs：Atechnology platform for integrated systems and opportunities for newpolmeric adhesives”，Proc IEEE Int’l Conf on Polymers andAdhesives in Microelectronics and Photonics，Germany，173-180(2001)；R.Reif，et al.，“Fabrication technologies for threedimensional integrated circuits”，Proc IEEE Int’l Symposium onQuality Electronic Design 33-37(2002)；以及A.W.Topol，et al.，“Ademonstration of wafer level layer transfer of high performancedevices and circuits for three-dimensional integrated circuitfabrication”，Proc.AVS ICMI，5-7(2003)中，描述了用晶片键合方法的三维集成方案。
尽管有这些采用三维集成的目前进展，但不存在制造具有制作在不同表面取向上的nFET和pFET的三维集成电路的现有技术。因此，对于提供一种新的和改进了的三维集成方案，使存在于半导体芯片或晶片上的各类器件能够被制作在为各个特定器件提供最佳性能的结晶学表面取向上，存在着需求。例如，对于提供一种其中所有nFET被制作在(100)结晶学表面上，而所有pFET被制作在(110)结晶学表面上的三维集成方案，存在着需求。
发明内容
本发明提供了制造三维集成电路的三维(3D)集成方案，其中，pFET位于(110)晶面上，而nFET位于(100)晶面上。术语“三维集成电路”可以被定义为包含各层之间具有垂直互连的多个有源器件层的IC。与常规二维(2D)电路相比，在三维IC中，各个晶体管能够接近更大数目的最近邻，致使各个晶体管或功能块具有更大的带宽。
三维集成的一个优点是封装密度提高了；借助于将第三维增加到常规二维布局中，能够改进晶体管的封装密度，从而减小芯片占据的面积。对于无线或便携式电子装置，这是特别有吸引力的。三维集成的另一优点是总的互连长度缩短了。这提供了较短的互连延迟、较低的噪声、以及改进了的电迁移可靠性。三维集成的另一好处是与常规二维IC相比能够明显地改善给定功耗下的整个芯片性能。
根据本发明的第一三维集成方案，第一半导体器件被预先制作在对第一半导体器件最佳的第一绝缘体上硅(SOI)衬底的半导体表面上，且不同于第一半导体器件的第二半导体器件被预先制作在对第二半导体器件最佳的第二SOI衬底的半导体表面上。在预先制作这二种结构之后，此二种结构被键合到一起，并经由穿过通孔的晶片-通道被互连。
广义地说，本发明的第一三维集成方案包含下列步骤：
提供第一互连结构，它包含至少一个位于第一绝缘体上硅衬底的第一含硅层的表面上的第一半导体器件，所述第一含硅层具有对所述第一半导体器件最佳的第一表面取向；
将操作晶片固定到第一互连结构的表面；
提供第二互连结构，它包含至少一个第二绝缘体上硅衬底的第二含硅层的表面上的不同于第一半导体器件的第二半导体器件，所述第二含硅层具有对所述第二半导体器件最佳的第二表面取向；
彼此键合第一和第二互连结构；以及
去除操作晶片。
在本三维集成方案的某些实施方案中，垂直互连被提供在第一和第二半导体器件之间。
除了上述第一三维集成方案之外，本发明还提供了第二三维集成方案。本发明的第二三维集成方案包含：
将具有第一晶向的第一SOI层的覆盖(blanket)绝缘体上硅(SOI)衬底，键合到晶向不同于第一SOI层的第二SOI层上具有至少一个第二半导体器件的预先制造的晶片的表面；以及
在所述第一SOI层中制作至少一个第一半导体器件。
根据本发明，第一半导体器件可以是pFET，且第一晶向可以是(110)，而第二半导体器件可以是nFET，且第二晶向可以是(100)。在本发明中，也有可能第一半导体器件可以是nFET，且第一晶向可以是(100)，而第二半导体器件可以是pFET，且第二晶向可以是(110)。
本发明还提供了一种三维(3D)集成电路，它包括：
第一互连结构，它包含至少一个位于第一绝缘体上硅衬底的第一含硅层的表面上的第一半导体器件，所述第一含硅层具有对所述第一半导体器件最佳的第一表面取向；
第二互连结构，它包含至少一个位于第二绝缘体上硅衬底的第二含硅层的表面上的不同于第一半导体器件的第二半导体器件，所述第二含硅层具有对所述第二半导体器件最佳的第二表面取向；以及
将第一互连结构连接到第二互连结构的垂直互连。
附图说明
图1A-1C是剖面图，示出了本发明的三维集成方案。
图2A-2C是剖面图，示出了本发明的三维集成变通方案。
具体实施方式
下面参照本发明的附图来更详细地描述本发明，本发明提供了三维集成方案，用来制作具有形成在不同晶向的SOI晶片上的器件层的三维CMOS集成电路。在这些附图中，用相似的参考号来表示相似和/或相应的元件。
在本发明中，术语“绝缘体上硅”即“SOI”晶片(术语“衬底”可以与术语“晶片”交换使用)被用来定义一种半导体结构，其中，诸如埋置的氧化层之类的埋置的绝缘层将顶部含硅层(也称为SOI层或器件层)分隔于底部含硅衬底层。术语“含硅的”在本发明中被用来表示包括硅的半导体材料。这种含硅材料的示例性例子包括但不局限于：Si、SiGe、SiC、SiGeC、Si/Si、Si/SiGe、Si/SiC、以及Si/SiGeC。埋置的绝缘层可以是连续的，也可以是不连续的，亦即图形化的埋置绝缘区。不连续的埋置绝缘区是一些分立的隔离区域或所有侧面上被含硅材料环绕的一些小岛。
用本技术领域熟练人员众所周知的技术，来形成用于本发明的SOI衬底。例如，可以用晶片键合和切割的方法来形成SOI衬底。或者，可以用所谓SIMOX(氧离子注入分离)方法来形成SOI衬底。在典型的SIMOX工艺中，氧离子被注入到含硅衬底的表面中，然后，含有注入的氧离子的衬底被退火，致使形成埋置的氧化层。在另一方法中，可以借助于用淀积或热的方法形成含硅衬底上的绝缘膜，可选地对此绝缘层进行图形化，然后形成与绝缘膜重叠的顶部含硅层，来形成SOI衬底。
虽然采用了此技术，但用于本发明的各个SOI衬底的埋置绝缘层的厚度典型约为10-1000nm，最典型的厚度约为100-200nm。用于本发明的各个SOI衬底的顶部含硅层的厚度典型约为20-200nm，更典型的厚度约为50-100nm。用于本发明的各个SOI衬底的底部含硅衬底层的厚度对本发明无关紧要。
各个SOI衬底的SOI层可以具有各种结晶学表面取向。例如，SOI衬底可以具有包含(100晶向或(110)晶向的SOI层。根据本发明，所采用的各个SOI衬底包含一个具有不同晶向的SOI层。于是，本发明试图利用具有第一结晶学取向的第一SOI层的第一SOI衬底以及具有第二结晶学取向的第二SOI层的第二SOI衬底，其中，第一结晶学取向不同于第二结晶学取向。
根据本发明，各个SOI层包含至少一个诸如nFET或pFET之类的半导体器件，但至少一个半导体器件必须位于提供最佳器件性能的结晶学表面上。于是，例如若此至少一个半导体器件是pFET，则此pFET可以位于(110)晶向的SOI层顶部。当此至少一个半导体器件是nFET时，则此nFET位于(100)晶向的SOI层顶部。
用本技术领域熟练人员众所周知的常规CMOS工艺步骤来制造此至少一个半导体器件。例如，借助于在SOI层表面上提供栅介质层，在栅介质层顶部上形成图形化的栅导体，所述图形化的栅导体包括位于其上的可选的图形化硬掩模，将掺杂剂注入到SOI层中和可选地注入到栅导体中，以及在图形化的栅导体的垂直侧壁上形成侧壁隔板，来制作FET。沟槽隔离区可以被形成在各个SOI衬底中，部分地或整个地通过SOI层延伸，停止于埋置的绝缘层的表面上。
在完成FET之后，利用常规的生产线后期(BEOL)工艺方案，在SOI结构上形成包括具有导电线条和通道的互连介质的至少一个互连层面。此BEOL工艺包括淀积介质、用光刻和腐蚀方法对淀积的介质进行图形化、以及用金属导体填充图形化的区域。可以采用本技术领域熟练人员众所周知的单重镶嵌或双重镶嵌技术或二者。
上面的讨论提供了本发明的一些基础，包括术语、材料、以及用来形成能够用于本发明的初始互连结构的工艺。参照特定附图的下面的描述，提供了可以用于本发明的三维集成方案的细节。
首先参照图1A-1C，示出了本发明的第一三维集成方案。根据本发明的第一三维集成方案，第一半导体器件被预先制作在对第一半导体器件最佳的第一绝缘体上硅(SOI)衬底的半导体表面上，且不同于第一半导体器件的第二半导体器件被预先制作在对第二半导体器件最佳的第二SOI衬底的半导体表面上。在预先制作这二种结构之后，此二种结构被键合到一起，并经由穿过通孔的晶片-通道被互连。
图1A示出了本发明第一三维集成方案的起始步骤，其中，操作晶片80被固定到第一互连结构10。第一互连结构10包括位于第一绝缘体上硅(SOI)衬底12的第一含硅层18的表面上的至少一个半导体器件20。根据本发明，第一含硅层18具有对第一半导体器件20最佳的第一表面取向。
在一个实施方案中，第一半导体器件20是nFET，且第一含硅层18具有(100)晶向。在另一实施方案中，第一半导体器件20是pFET，且第一含硅层18具有(110)晶向。第一半导体器件20如上所述被制造。
第一互连结构10还包括具有导电布线亦即线条和通道位于其中的至少一个介质22。此导电布线由图1A中的参考号24指定。
操作晶片80包含通过聚合物粘合剂被固定到第一互连结构10的表面的体半导体衬底，另一个SOI衬底或玻璃。在图1A中，起始结构包括第一互连结构10与操作晶片80之间的聚合物粘合层28。
能够用于本发明的聚合物粘合剂的示例性类型可以是导电或不导电的材料。用于本发明的优选聚合物粘合剂是一种不导电的材料。此聚合物粘合剂通常被涂敷到第一互连结构10的最上部表面，并借助于使操作晶片80与第一互连结构10紧密接触而得到固定。借助于将外力施加到二个衬底，或借助于将此结构加热到稍许高于聚合物粘合剂熔点的温度，可以方便此固定。在图1A中，箭头30表示按此发生接触的方向。
在固定之后，用诸如化学机械抛光(CMP)、研磨、和/或腐蚀之类的整平工艺，去除参考号14所示的第一SOI衬底12的底部含硅衬底。此整平工艺一旦到达参考号16所示的埋置绝缘层就停止。箭头32示出了本发明的这一减薄步骤。
提供了包含位于第二绝缘体上硅衬底52的第二含硅层58表面上的至少一个第二半导体器件60的第二互连结构50，并使之与图1A所示的结构相接触。图1B示出了本发明的这一步骤。根据本发明，第二含硅层58具有对第二半导体器件最佳的第二表面取向。第二预先制作的SOI衬底52还包括底部含硅层54和埋置的绝缘层56。第二互连结构还包括互连介质62和布线区64。
在一个实施方案中，当第一半导体器件20是nFET时，第二半导体器件60是位于晶向为(110)的第二含硅层58上的pFET。在另一实施方案中，当第一半导体器件20是pFET时，第二半导体器件60是位于晶向为(100)的第二含硅层58上的nFET。应该指出的是，第一半导体器件20不同于第二半导体器件60，且第一含硅层18的结晶学取向不同于第二含硅层58的结晶学取向。
然后，第一和第二互连结构(分别是10和50)被彼此键合。具体地说，借助于首先使二个结构彼此紧密接触；可选地将外力施加到接触的二个晶片；以及然后在能够将二个结构键合到一起的条件下加热二个接触的结构，来达到二个互连结构的键合。可以在存在或不存在外力的情况下执行加热步骤。参考号70所示的箭头表示接触的方向。
加热步骤通常在大约200-1050℃的温度下，于惰性气氛中执行大约2-20小时的时间。更优选的是，在大约200-400℃的温度下执行大约2-20小时的键合。术语“惰性气氛”被用于本发明来表示其中使用诸如He、Ar、N2、Xe、Kr、或它们的混合物的气氛。键合工艺中使用的优选气氛是N2。
图1C示出了操作晶片80和粘合层28从键合的结构被去除之后的结构。可以利用上述的整平工艺之一来去除操作晶片80和粘合层28。亦即，可以用研磨、化学机械抛光、和/或腐蚀来从键合的结构去除操作和粘合层。或者，用激光烧蚀来去除操作晶片80，而用化学机械抛光来去除粘合层28。图1C还示出了用光刻、腐蚀、以及导电金属的淀积形成的可选垂直互连75的存在。尽管是可选的，但在其中要求二个半导体器件之间直接连接的本发明的某些实施方案中，垂直互连75是优选的。
图1C所示的三维集成电路包括制作在对各个器件最佳的特定结晶学取向的SOI层(18或58)上的诸如nFET和pFET之类的半导体器件20和60。在一个优选实施方案中，三维集成电路包括(100)SOI层上的nFET和(110)SOI层上的pFET。
除了上述第一三维集成方案之外，本发明还尝试了第二三维集成方案。下面参照图2A-2C来更详细地描述第二三维集成方案。在第二集成方案中，覆盖SOI晶片90被层叠在预先制作的器件晶片120上，各个晶片具有结晶学取向不同的SOI层。然后键合二个晶片，并对覆盖SOI晶片执行其它的制造工艺，以便形成有源器件和互连。
图2A示出了一种初始结构，它包括第二SOI层128上具有第二半导体器件130的预先制作的晶片120。层124代表底部含硅层，而层126代表埋置的绝缘层。预先制作的晶片120还可以包括互连区，此互连区包括介质132和位于其中的导电布线134。
接着，具有结晶学取向不同于第二SOI层128的第一SOI层96的覆盖SOI晶片90，被层叠在图2A所示的结构顶部，致使覆盖SOI层90的底部含硅层92成为层叠结构的最上层。这些层叠结构然后如上所述被键合，就提供了图2B所示的结构。参考号94表示覆盖SOI晶片90的埋置绝缘层。
然后用研磨、化学机械抛光、和/或腐蚀的方法，去除覆盖SOI晶片90的底部含硅层92和埋置的绝缘层94，以便暴露覆盖SOI晶片90的第一SOI层96。
然后，用上述技术，将诸如nFET或pFET之类的第一半导体器件118制作在第一SOI层96上。生产线后端加工可以被用来将互连结构150形成在现已制作的覆盖SOI晶片的顶部，且上述加工可以被用于形成垂直互连75。得到的结构被示于图2C中。
虽然对其优选实施方案已经具体地描述了本发明，但本技术领域的熟练人员可以理解的是，可以进行形式和细节方面的上述和其它的改变而不偏离本发明的构思与范围。因此认为本发明不局限于所述的准确形式和细节，而是在所附权利要求的范围内。

Claims (23)

1.一种三维集成方案，它包括下列步骤：
提供第一互连结构，它包括位于第一绝缘体上硅衬底的第一含硅层的表面上的至少一个第一半导体器件，所述第一含硅层具有对所述第一半导体器件最佳的第一表面取向；
将操作晶片固定到第一互连结构的表面；
提供第二互连结构，它包括第二绝缘体上硅衬底的第二含硅层的表面上的不同于第一半导体器件的至少一个第二半导体器件，所述第二含硅层具有对所述第二半导体器件最佳的第二表面取向；
彼此键合第一和第二互连结构；以及
去除操作晶片。
2.权利要求1的三维集成方案，还包括形成第一与第二半导体器件之间的垂直互连。
3.权利要求2的三维集成方案，其中，所述形成垂直互连的步骤包括光刻、腐蚀、以及导电金属的淀积。
4.权利要求1的三维集成方案，其中，所述固定的步骤包括将聚合物粘合剂涂敷到第一互连结构的表面以及使操作晶片与包括所述聚合物粘合剂的第一互连结构彼此紧密接触。
5.权利要求4的三维集成方案，还包括将外力施加到接触的操作晶片和包括所述聚合物粘合剂的第一互连结构。
6.权利要求4的三维集成方案，还包括将接触的操作晶片和包括所述聚合物粘合剂的第一互连结构加热到聚合物粘合剂熔点以上的温度。
7.权利要求1的三维集成方案，其中，第一半导体器件是pFET，第一半导体层具有(110)结晶学取向，第二半导体器件是nFET，且第二半导体层具有(100)结晶学取向。
8.权利要求1的三维集成方案，其中，第一半导体器件是nFET，第一半导体层具有(100)结晶学取向，第二半导体器件是pFET，且第二半导体层具有(110)结晶学取向。
9.权利要求1的三维集成方案，其中，加热步骤在大约200-1050℃的温度下执行大约2-20小时。
10.权利要求1的三维集成方案，其中，加热步骤在惰性气氛中执行。
11.一种三维集成方案，它包括下列步骤：
将具有第一结晶学取向的第一绝缘体上硅层的覆盖绝缘体上硅衬底，键合到在结晶学取向不同于第一绝缘体上硅层的第二绝缘体上硅层上具有至少一个第二半导体器件的预先制造的晶片的表面；以及
在所述第一绝缘体上硅层中制作至少一个第一半导体器件。
12.权利要求11的三维集成方案，还包括形成第一与第二半导体器件之间的垂直互连。
13.权利要求12的三维集成方案，其中，所述形成垂直互连的步骤包括光刻、腐蚀、以及导电金属的淀积。
14.权利要求11的三维集成方案，其中，第一半导体器件是pFET，第一绝缘体上硅层具有(110)结晶学取向，第二半导体器件是nFET，且第二绝缘体上硅层具有(100)结晶学取向。
15.权利要求11的三维集成方案，其中，第一半导体器件是nFET，第一绝缘体上硅层具有(100)结晶学取向，第二半导体器件是pFET，且第二绝缘体上硅层具有(110)结晶学取向。
16.权利要求11的三维集成方案，其中，键合步骤在大约200-1050℃的温度下执行大约2-20小时。
17.权利要求16的三维集成方案，其中，键合步骤在惰性气氛中执行。
18.权利要求11的三维集成方案，其中，第一半导体器件用CMOS工艺来制作。
19.权利要求11的三维集成方案，还包括在键合之后但在所述制作步骤之前，去除所述覆盖绝缘体上硅衬底的底部含硅层和埋置的绝缘层的步骤。
20.一种三维集成电路，它包括：
第一互连结构，它包括位于第一绝缘体上硅衬底的第一含硅层表面上的至少一个第一半导体器件，所述第一含硅层具有对所述第一半导体器件最佳的第一表面取向；
第二互连结构，它包括位于第二绝缘体上硅衬底的第二含硅层表面上的不同于第一半导体器件的至少一个第二半导体器件，所述第二含硅层具有对所述第二半导体器件最佳的第二表面取向；以及
将第一互连结构连接到第二互连结构的垂直互连。
21.权利要求20的三维集成电路，其中，第一半导体器件是pFET，第一半导体层具有(110)结晶学取向，第二半导体器件是nFET，且第二半导体层具有(100)结晶学取向。
22.权利要求20的三维集成电路，其中，第一半导体器件是nFET，第一半导体层具有(100)结晶学取向，第二半导体器件是pFET，且第二半导体层具有(110)结晶学取向。
23.权利要求20的三维集成电路，其中，所述第一和第二互连结构包括其中具有导电布线的至少一个图形化的互连介质。
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