JPS6418248A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS6418248A JPS6418248A JP17443287A JP17443287A JPS6418248A JP S6418248 A JPS6418248 A JP S6418248A JP 17443287 A JP17443287 A JP 17443287A JP 17443287 A JP17443287 A JP 17443287A JP S6418248 A JPS6418248 A JP S6418248A
- Authority
- JP
- Japan
- Prior art keywords
- oxide film
- substrate
- layer
- mechanical
- buried
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Thin Film Transistor (AREA)
Abstract
PURPOSE:To form a uniform thin layer without being affected by an irregularity in the thickness of a semiconductor substrate by a method wherein a mechanical and chemical polishing operation of the rear of the semiconductor substrate is stopped at the rear surface of a buried insulating layer by using the semiconductor substrate where the buried insulating layer has been formed over the whole surface of the substrate. CONSTITUTION:Oxygen ions are implanted into the whole surface of a p-type silicon substrate 11; after that, a buried oxide film layer 12 composed of a silicon oxide film by an annealing operation is formed; an n-channel MOS transistor 13, a wiring part 14 and an insulating film 15 composed of the silicon oxide film are formed. Then, a supporting silicon substrate 16 is bonded onto the insulating film 15 by using an epoxy resin or the like; the silicon substrate 11 is polished from its rear by a mechanical and chemical polishing method. Because the buried oxide film layer 12 exists, the mechanical and chemical polishing operation is stopped at the rear surface of the buried oxide film layer 12. By this setup, even when the thickness of the substrate is irregular, a uniform thin layer can be formed.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP17443287A JPS6418248A (en) | 1987-07-13 | 1987-07-13 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP17443287A JPS6418248A (en) | 1987-07-13 | 1987-07-13 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6418248A true JPS6418248A (en) | 1989-01-23 |
Family
ID=15978429
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP17443287A Pending JPS6418248A (en) | 1987-07-13 | 1987-07-13 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6418248A (en) |
Cited By (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0684643A1 (en) * | 1994-05-24 | 1995-11-29 | Koninklijke Philips Electronics N.V. | Method of manufacturing semiconductor devices in an active layer on an support substrate |
JPH09260669A (en) * | 1996-03-19 | 1997-10-03 | Nec Corp | Semiconductor device and manufacture thereof |
EP0810659A3 (en) * | 1996-05-28 | 1999-08-04 | Harris Corporation | Semiconductor packaging apparatus and method |
JP2005109498A (en) * | 2003-09-30 | 2005-04-21 | Internatl Business Mach Corp <Ibm> | Three dimensional cmos integrated circuit having device layer constituted on wafer with different crystal orientation |
JP2009212530A (en) * | 1999-12-07 | 2009-09-17 | Alcatel-Lucent Usa Inc | Method for fabricating integrated circuit device |
JP2013191639A (en) * | 2012-03-12 | 2013-09-26 | Nippon Hoso Kyokai <Nhk> | Laminated semiconductor device and manufacturing method of the same |
JP2015095517A (en) * | 2013-11-11 | 2015-05-18 | 日本放送協会 | Laminate type integrated circuit, and method for manufacturing the same |
JP2016062903A (en) * | 2014-09-12 | 2016-04-25 | 日本放送協会 | Laminated semiconductor element and manufacturing method thereof |
JP2017098573A (en) * | 2011-06-22 | 2017-06-01 | ペレグリン セミコンダクター コーポレイション | Integrated circuit having component on both sides of selected substrate and manufacturing method thereof |
-
1987
- 1987-07-13 JP JP17443287A patent/JPS6418248A/en active Pending
Cited By (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0684643A1 (en) * | 1994-05-24 | 1995-11-29 | Koninklijke Philips Electronics N.V. | Method of manufacturing semiconductor devices in an active layer on an support substrate |
BE1008384A3 (en) * | 1994-05-24 | 1996-04-02 | Koninkl Philips Electronics Nv | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICES WITH SEMICONDUCTOR ELEMENTS MADE IN A LAYER SEMICONDUCTOR MATERIAL APPLIED ON A BEARING PLATE. |
JPH09260669A (en) * | 1996-03-19 | 1997-10-03 | Nec Corp | Semiconductor device and manufacture thereof |
EP0810659A3 (en) * | 1996-05-28 | 1999-08-04 | Harris Corporation | Semiconductor packaging apparatus and method |
JP2009212530A (en) * | 1999-12-07 | 2009-09-17 | Alcatel-Lucent Usa Inc | Method for fabricating integrated circuit device |
JP2005109498A (en) * | 2003-09-30 | 2005-04-21 | Internatl Business Mach Corp <Ibm> | Three dimensional cmos integrated circuit having device layer constituted on wafer with different crystal orientation |
JP2017098573A (en) * | 2011-06-22 | 2017-06-01 | ペレグリン セミコンダクター コーポレイション | Integrated circuit having component on both sides of selected substrate and manufacturing method thereof |
JP2013191639A (en) * | 2012-03-12 | 2013-09-26 | Nippon Hoso Kyokai <Nhk> | Laminated semiconductor device and manufacturing method of the same |
JP2015095517A (en) * | 2013-11-11 | 2015-05-18 | 日本放送協会 | Laminate type integrated circuit, and method for manufacturing the same |
JP2016062903A (en) * | 2014-09-12 | 2016-04-25 | 日本放送協会 | Laminated semiconductor element and manufacturing method thereof |
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