CN1359154A - 半导体器件 - Google Patents
半导体器件 Download PDFInfo
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- CN1359154A CN1359154A CN01145444A CN01145444A CN1359154A CN 1359154 A CN1359154 A CN 1359154A CN 01145444 A CN01145444 A CN 01145444A CN 01145444 A CN01145444 A CN 01145444A CN 1359154 A CN1359154 A CN 1359154A
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Abstract
可抑制内部压降的低成本半导体器件。将元件形成面2对着布线板7来配置半导体芯片1,通过导电性凸点4装载在布线板上。在布线板的芯片装载面一侧上在与凸点对应的位置上形成布线层7B。该布线层与和安装基板连接的导电性凸点13电连接。芯片的外周部上设置埋置导电性部件15的通孔3,在芯片背面的导电性部件15上形成连接端子5。通过键合引线6连接该连接端子5和布线板的布线层。由于将连接端子设置在芯片的两面上,不增大连接密度也可增加连接端子数。
Description
技术领域
本发明涉及在半导体芯片中形成埋置导电性部件的通孔、从半导体元件的形成面一侧和其背面一侧导出布线的封装结构的半导体器件,尤其是强化了电源的高性能半导体器件。
背景技术
伴随半导体集成电路的精细化的电源电压的低压化、电路规模的增大促进半导体芯片尺寸增大,半导体芯片内部的压降问题明显起来。作为其对策,跨过半导体芯片的整个表面来设置连接端子、在多层布线板上面朝下连接的倒装片结构的封装(package)正成为主流。
图29是表示上述已有半导体器件的简略结构的剖面图。图29中,21是半导体芯片,22是半导体元件的形成面,23是半导体元件的形成面22上设置的连接端子(导电凸点),24是精细布线板。将半导体元件的形成面22朝下配置半导体芯片21,通过电连接于该半导体芯片21中的半导体元件的导电性凸点23将其装载在精细布线板24上。该精细布线板24在树脂等构成的绝缘性基板24A的两面和内部分别形成布线层(多层布线)24B,在上述半导体芯片21的装载面一侧上在与上述凸点23对应的位置上形成布线层。该布线层经设置在上述基板24A上的布线层部向背面侧导出,电连接于和安装基板连接用的连接端子(导电性凸点)25。
但是,为实现上述结构的半导体器件,必须在精细布线板24中回引半导体芯片21上连接的多个信号线,因此必须是精细的图案,造价非常高。
另外,为在多个半导体芯片之间高速传送信号,还提出一种如下结构的封装:通过在将半导体芯片的电路形成面彼此相对来配置的状态下安装,以最短距离连接多个连接端子。
但是,这样的封装结构的情况下,要进行电源补充时,则由于各半导体芯片的电路形成面相对,仅能从芯片外周部提供电源,使得不能解决半导体芯片内部的压降的问题。
发明内容
如上所述,原有的半导体器件中存在的问题是:电源电压的低压化和半导体芯片内部的压降问题明显,为解决这些问题,使成本提高。
另外,提出了可高速传送信号的封装结构的半导体器件,但未能解决半导体芯片内部的压降问题。
鉴于上述情况,本发明的目的是提供以最低成本实现必要功能的半导体器件。
本发明的另一目的是提供一种半导体器件,即使因半导体集成电路的精细化造成的电源电压的低压化和电路规模增大而扩大了半导体芯片的尺寸,也可抑制半导体芯片内部的压降。
另外,本发明的又一目的是提供具有高性能且廉价的封装结构的半导体器件。
本发明的方案1记载的半导体器件的特征在于包括:形成半导体元件的第一半导体芯片;设置在上述第一半导体芯片的半导体元件的形成面一侧上、与该半导体元件电连接的第一连接端子;埋置在贯通上述第一半导体芯片的通孔内的导电性部件;设置在上述第一半导体芯片的半导体元件的形成面的背面一侧上、经上述导电性部件与上述半导体元件电连接的第二连接端子;装载上述第一半导体芯片的布线板;至少一部分形成在上述布线板的与上述第一连接端子和第二连接端子之一对应的位置上、与第一连接端子或第二连接端子电连接的第三连接端子。
本发明的方案2记载的半导体器件的特征在于包括:形成半导体元件的第一半导体芯片;设置在上述第一半导体芯片的半导体元件的形成面一侧上、与该半导体元件电连接的第一连接端子;埋置在贯通上述第一半导体芯片的通孔内的导电性部件;设置在上述第一半导体芯片的半导体元件的形成面的背面一侧上、经上述导电性部件与上述半导体元件电连接的第二连接端子;装载上述第一半导体芯片、在与上述第一连接端子和第二连接端子之一对应的位置上电连接至少一部分的引线框;密封上述引线框的内引线部与上述第一半导体芯片的封装。
本发明的方案3记载的半导体器件,包括:形成半导体元件的第一半导体芯片;设置在上述第一半导体芯片的半导体元件的形成面一侧上、与该半导体元件电连接的第一连接端子;埋置在贯通上述第一半导体芯片的通孔内的导电性部件;设置在上述第一半导体芯片的半导体元件的形成面的背面一侧上、经上述导电性部件与上述半导体元件电连接的第二连接端子,其特征在于将上述第一连接端子或第二连接端子连接于安装基板来安装。
本发明的方案4记载的半导体器件,包括:形成半导体元件的半导体芯片;设置在上述半导体芯片的半导体元件的形成面一侧上、与该半导体元件电连接的多个第一连接端子;分别埋置在贯通上述半导体芯片的多个通孔内的导电性部件;设置在上述半导体芯片的半导体元件的形成面的背面一侧上、经上述导电性部件与上述半导体元件电连接的多个第二连接端子,其特征在于使配置上述多个第一连接端子的平均密度比配置上述多个第二连接端子的平均密度低。
本发明的方案5记载的半导体器件,包括:形成半导体元件的半导体芯片;设置在上述半导体芯片的半导体元件的形成面一侧上、与该半导体元件电连接的第一连接端子;埋置在贯通上述半导体芯片的多通孔内的导电性部件;设置在上述半导体芯片的半导体元件的形成面的背面一侧上、经上述导电性部件与上述半导体元件电连接的第二连接端子,其特征在于使上述第一连接端子或第二连接端子至少之一方的一部分分散配置在上述半导体芯片的整个区域上,同时施加电源电位或接地电位。
如方案6所示,在方案1记载的半导体器件中,其特征在于还具有键合引线,将上述第一半导体芯片的上述第一连接端子或第二连接端子中未用于和上述布线板对向连接的那一方的连接端子的至少一部分与上述布线板上形成的上述第三连接端子连接起来。
如方案7所示,在方案2记载的半导体器件中,其特征在于还具有键合引线,将上述第一半导体芯片的第一连接端子或第二连接端子中未用于和引线框对向连接的那一方的连接端子的至少一部分与上述引线框的内引线部连接起来,并具有将上述引线框的内引线部与上述第一半导体芯片封装起来的封装。
如方案8所示,在方案1记载的半导体器件中,其特征在于还具有在上述第一半导体芯片上层叠的第二半导体芯片,将上述第一半导体芯片的第一连接端子或第二连接端子中未用于和上述布线板对向连接的那一方的连接端子的至少一部分与上述第二半导体芯片连接起来。
如方案9所示,在方案1记载的半导体器件中,其特征在于还具有在上述第一半导体芯片上层叠的第二至第n(n为3以上的正整数)半导体芯片,将上述第一半导体芯片的第一连接端子或第二连接端子中未用于和上述布线板对向连接的那一方的连接端子的至少一部分与上述第二至第n半导体芯片连接起来。
如方案10所示,在方案2记载的半导体器件中,其特征在于还具有在上述第一半导体芯片上层叠的第二半导体芯片,将上述第一半导体芯片的第一连接端子或第二连接端子中未用于和上述引线框对向连接的那一方的连接端子的至少一部分与上述第二半导体芯片连接起来。
如方案11所示,在方案2记载的半导体器件中,其特征在于还具有在上述第一半导体芯片上层叠的第二至第n(n为3以上的正整数)半导体芯片,将上述第一半导体芯片的第一连接端子或第二连接端子中未用于和上述引线框对向连接的那一方的连接端子的至少一部分与上述第二至第n半导体芯片连接起来。
如方案12所示,在方案3记载的半导体器件中,其特征在于还具有在上述第一半导体芯片上层叠的第二半导体芯片,将上述第一半导体芯片的第一连接端子或第二连接端子安装在安装基板上,将这些连接端子中未用于和上述安装基板外部连接的一方的连接端子的至少一部分与上述第二半导体芯片连接起来。
如方案13所示,在方案3记载的半导体器件中,其特征在于还具有在上述第一半导体芯片上层叠的第二至第n(n为3以上的正整数)半导体芯片,将上述第一半导体芯片的第一连接端子和第二连接端子安装在安装基板上,将这些连接端子中未用于和上述安装基板外部连接的一方的连接端子的至少一部分与上述第二至第n半导体芯片连接起来。
如方案14所示,在方案8-13之一记载的半导体器件中,其特征在于还具有连接上述层叠的多个半导体芯片之间的至少一部分的键合引线。
如方案15所示,在方案8-13之一记载的半导体器件中,其特征在于还具有连接上述层叠的多个半导体芯片之间的至少一部分的导电性凸点。
如方案16所示,在方案15记载的半导体器件中,其特征在于将半导体元件的形成面相对地来把上述半导体芯片中至少2个相邻的半导体芯片之间连接起来。
本发明的方案17记载的半导体器件包括:形成半导体元件的第一半导体芯片;设置在上述第一半导体芯片的半导体元件的形成面一侧上、与该半导体元件电连接的第一连接端子;埋置在贯通上述第一半导体芯片的通孔内的导电性部件;设置在上述第一半导体芯片的半导体元件的形成面的背面一侧上、经上述导电性部件与上述半导体元件电连接的第二连接端子;层叠在上述第一半导体芯片上的第二半导体芯片;仅设置在上述第二半导体芯片的半导体元件的形成面一侧上的第三连接端子,其特征在于将上述第一半导体芯片的第一连接端子和第二连接端子之一设置在与上述第二半导体芯片的第三连接端子相对的位置上,经该相对的连接端子之间把上述第一半导体芯片与第二半导体芯片电连接起来。
如方案18所示,在方案17记载的半导体器件中,其特征在于上述第二半导体芯片比上述第一半导体芯片度厚。
如方案19所示,在方案17或18记载的半导体器件中,其特征在于上述第二半导体芯片比上述第一半导体芯片大。
如方案20所示,在方案17到19之一记载的半导体器件中,其特征在于还具有在包含上述第一半导体芯片与第二半导体芯片之间的连接点的间隙中设置的填充树脂。
而且,本发明的方案21记载的半导体器件包括:形成半导体元件的半导体芯片;设置在上述半导体芯片的半导体元件的形成面一侧上、与该半导体元件电连接的第一连接端子;埋置在贯通上述半导体芯片的通孔内的导电性部件;设置在上述半导体芯片的半导体元件的形成面的背面一侧上、经上述导电性部件与上述半导体元件电连接的第二连接端子;装载上述半导体芯片的布线板;在上述布线板上形成、一部分配置在与上述半导体芯片的第一连接端子相对的位置上、电连接于上述半导体芯片的第三连接端子;将上述半导体芯片的第二连接端子中的至少一部分与上述布线板上形成的上述第三连接端子连接起来的键合引线;在包含上述键合引线和上述半导体芯片的布线板的上面设置的封装树脂;为和安装基板连接而设置在装载上述布线板的上述半导体芯片的面的背面一侧上、与上述第三连接端子电连接的第四连接端子,其特征在于上述第一连接端子主要用于施加电源电位和接地电位,上述第二连接端子主要用于信号系统。
另外,本发明的方案22记载的半导体器件包括:形成半导体元件的半导体芯片;沿着上述半导体芯片的半导体元件的形成面一侧的外周部设置、与该半导体元件电连接的第一连接端子;分别埋置在分散在整个上述半导体芯片上形成的贯通内的导电性部件;设置在上述半导体芯片的半导体元件的形成面的背面一侧上、分别经上述导电性部件与上述半导体元件电连接的第二连接端子;装载上述半导体芯片的布线板;在与上述半导体芯片的第二连接端子相对的位置上形成、电连接于上述半导体芯片的第三连接端子;将上述半导体芯片的第一连接端子中的至少一部分与上述布线板上形成的第三连接端子连接起来的键合引线;在包含上述键合引线和上述半导体芯片的布线板的上面设置的封装树脂;为和安装基板连接而设置在装载上述布线板的上述半导体芯片的面的背面一侧上、与上述第三连接端子电连接的第四连接端子,其特征在于上述第二连接端子主要用于施加电源电位和接地电位,上述第一连接端子主要用于信号系统。
根据本发明,可得到下述效果。
即,根据方案1记载的结构,可增加连接端子的配置位置,因此不增大连接密度,可增加连接端子数目。
根据方案2记载的结构,由于在引线框上装载半导体芯片,与使用方案1所示的布线板的情况相比,可提供更廉价的半导体器件。
根据方案3记载的结构,可实现不增大连接密度而增加连接端子数目的CSP,大幅度提高安装效率。
根据方案4记载的结构,通过在半导体芯片上形成的通孔可抑制芯片尺寸的增大。
根据方案5记载的结构,由于将连接端子分散配置在半导体芯片的整个表面上,可不增大连接密度而降低半导体芯片内的压降。
根据方案6记载的结构,由于可不使用高价精细布线板来增加连接端子数目,能够以最低成本实现必要功能。
根据方案7记载的结构,由于将半导体芯片装载在比布线板成本低的引线框上,与方案6所示的半导体器件相比,可实现更廉价的半导体器件。
根据方案8到15记载的结构,可不使用高价精细布线板来增加连接端子数目,并且能够以最短距离在多个半导体芯片之间传送信号,实现半导体器件的高性能化。
根据方案16记载的结构,除上述方案8到16记载的半导体器件的效果外,可在多个半导体芯片之间形成多个连接点。
根据方案17到20记载的结构,由于可用第二半导体芯片加固设置通孔的薄的第一半导体芯片,可大幅度降低第一半导体芯片破坏的危险。
根据方案21和22记载的结构,可不使用高价精细布线板来增加连接端子数目,并且能够降低半导体芯片内的压降。
附图说明
图1说明本发明的第1实施例的半导体器件,(a)是表示简略结构的剖面图,(b)是(a)图的局部放大剖面图。
图2说明本发明的第2实施例的半导体器件,(a)是表示简略结构的剖面图,(b)是(a)图的局部放大剖面图。
图3是说明本发明的第3实施例的半导体器件的剖面简图。
图4是说明本发明的第4实施例的半导体器件的剖面简图。
图5是说明本发明的第5实施例的半导体器件的剖面简图。
图6是说明本发明的第6实施例的半导体器件的剖面简图。
图7是说明本发明的第7实施例的半导体器件的剖面简图。
图8是说明本发明的第8实施例的半导体器件的剖面简图。
图9是说明本发明的第9实施例的半导体器件的剖面简图。
图10是说明本发明的第10实施例的半导体器件的剖面简图。
图11是说明本发明的第11实施例的半导体器件的剖面简图。
图12是说明本发明的第12实施例的半导体器件的剖面简图。
图13是说明本发明的第13实施例的半导体器件的剖面简图。
图14是说明本发明的第14实施例的半导体器件的剖面简图。
图15是说明本发明的第15实施例的半导体器件的剖面简图。
图16是说明本发明的第16实施例的半导体器件的剖面简图。
图17是说明本发明的第17实施例的半导体器件的剖面简图。
图18是说明本发明的第18实施例的半导体器件的剖面简图。
图19是说明本发明的第19实施例的半导体器件的剖面简图。
图20是说明本发明的第20实施例的半导体器件的剖面简图。
图21是说明本发明的第21实施例的半导体器件的剖面简图。
图22是说明本发明的第22实施例的半导体器件的剖面简图。
图23是说明本发明的第23实施例的半导体器件的剖面简图。
图24是说明本发明的第24实施例的半导体器件的剖面简图。
图25是说明本发明的第25实施例的半导体器件的剖面简图。
图26是说明本发明的第26实施例的半导体器件的剖面简图。
图27是说明本发明的第27实施例的半导体器件的剖面简图。
图28是说明本发明的第28实施例的半导体器件的剖面简图。
图29是说明原有的半导体器件的剖面简图。
具体实施方式
本发明的主旨是在各种状态下安装设置有埋置导电性部件的通孔的半导体芯片,通过经埋置在通孔内的导电性部件在半导体芯片的背面一侧上导出少数几个需要在半导体芯片表面的整个区域上分散的电源系统和接地系统的布线连接、或者未必需要在半导体芯片表面的整个区域上分散的多个必须的信号系统的布线连接,在半导体芯片的两个表面上再配置。
并且,半导体芯片面朝上安装时,把通孔分配给电源系统和接地系统,从半导体元件的形成面的背面直接进行电源补充。另一方面,在需要精细连接的信号线上从在半导体元件的形成面的外周部上设置的焊盘进行引线键合来导出。通过该组合,不使用高价精细布线板可实现强化电源的高性能半导体器件。
另一方面,半导体芯片面朝下安装时,半导体元件的形成面上二维配置电源焊盘和接地焊盘进行倒装片连接。需要进行精细连接的信号线经形成在半导体元件的外周部上的通孔导出到半导体元件的形成面的背面,从背面一侧用引线键合引出。这种组合的情况下,与上述同样,不使用高价精细布线板可实现强化电源的高性能半导体器件。
作为改进例,在上述2个例子的半导体芯片上可层叠另外的半导体芯片。尤其,2个半导体芯片之间的连接密度高时,把下面的半导体芯片面朝上,可不经高价布线板实现多端子连接。
下面参考附图详细说明本发明的各种实施例。
[第1实施例]
图1(a),(b)分别说明本发明的第1实施例的半导体器件,(a)是剖面简图,(b)是(a)图的局部放大图。如图(a)所示,半导体芯片1把半导体元件(内部电路)的形成面2对着布线板7(面朝下)安装。半导体元件的形成面2上把连接端子(导电性凸点)4分散在整个区域上(例如阵列状)来形成,经该连接端子4与布线板7的布线层7B电连接。上述布线板7在树脂等构成的绝缘性基板7A的两面和内部分别形成布线层(多层布线)7B,在上述半导体芯片1的装载侧上在与上述凸点4对应的艉上配置布线层。该布线层7B经设置在上述基板7A上的布线层部向背面一侧导出,电连接于用于和安装基板连接的连接端子(导电性凸点)13。
上述半导体芯片1的外周部上形成埋置导电性部件的通孔3,在该通孔3内埋置的导电性部件的芯片背面上分别形成连接端子(焊盘5)。上述连接端子5和布线板7通过键合引线6连接。并且,上述布线板7上的半导体芯片1和键合引线6被封装在树脂和陶瓷等构成的封装9中。
上述结构中,通孔3附近如图(b)所示。半导体芯片1上形成的通孔3侧壁上形成绝缘膜14,该通孔3内设置以与上述芯片1绝缘的状态埋置的金属(导电性部件)15。上述芯片1的半导体元件的形成面侧2上设置例如铜和铝等构成、一端电连接于上述导电性部件15的芯片内布线17。该芯片内布线17的另一端电连接于半导体元件(内部电路)。之后,包含上述芯片内布线17的芯片1的半导体元件形成面2的整个面用层间绝缘膜和表面保护膜16覆盖。另一方面,上述芯片1的元件形成面的背面一侧的导电性部件15上设置键合焊盘(连接端子)5,该连接端子5上球焊键合引线6的一端。并且,除上述通孔3附近的芯片1的背面上形成背面绝缘膜18。
本结构的最大的优点是在原有的塑性BGA封装中可连接的整个区域,即与半导体芯片1的布线板7相对的面的整个区域机器背面的外周部上可分散配置连接端子4,5,实质不增大连接密度,却可增加连接点的数目。
另外,把半导体元件的形成面2上分散的连接端子4分配给电源系统和接地系统,从而最大限度利用本结构的便利性。一般地,电源系统和接地系统的连接端子分散配置在半导体芯片1的整个面上是重要的,也未必需要多个连接点。与此相反,信号系统的连接当然也需要多个连接点数目,但反过来,不需要在半导体芯片1的整个面上分散。因此,面上配置的连接端子4端子数目少、可使用廉价布线板7回引。而且,多个信号端子通过键合引线6在从芯片外周部向外周扩开的状态下配置,因此用这些廉价布线板7也可进行充分地回引。
因此,根据上述第1实施例的半导体器件,能够以最低成本实现必要的功能。即使因半导体集成电路的精细化导致的电源电压降低和电路规模增大扩大了半导体芯片尺寸,也可抑制半导体芯片内部的压降。而且,可得到具有高性能且廉价封装结构的半导体器件。
[第2实施例]
图2(a),(b)分别说明本发明的第2实施例的半导体器件,(a)是剖面简图,(b)是(a)图的局部放大图。本实施例2中,把半导体元件的形成面2的背面面对布线板7(面朝上)装载半导体芯片1。埋置导电性部件15的通孔3分散配置在整个半导体芯片1上,使用经该通孔3形成在芯片1的背面上的连接端子(导电性凸点)5与布线板7进行连接。半导体芯片1的半导体元件的形成面2的外周部上形成与一般半导体器件相同的连接端子(凸点)4,从该连接端子4经引线键合与布线板7的布线层7B电连接。
上述结构中,通孔3附近如图(b)所示。半导体芯片1上形成的通孔3的侧壁上形成绝缘膜14,该通孔3内在与上述芯片1绝缘的状态下埋置导电性部件15。上述芯片1的半导体元件的形成面2一侧上设置一端与上述导电性部件15电连接的芯片内布线17,该芯片内布线17的另一端与半导体元件(内部电路)电连接。包含上述芯片内布线17的芯片1的半导体元件的形成面2的整个面用层间绝缘膜和表面保护膜16覆盖,背面侧的导电性部件15上设置导电性凸点(连接端子)5。该凸点5上连接布线板7的布线层7B。而且,除上述通孔3的附近外的芯片1的背面用背面绝缘膜18覆盖。
本结构也与上述第1实施例一样,具有在适合于连接的位置上分散连接端子4,5的特征,因此可不增加实际的连接密度而增加连接点的数目。本发明的情况下,电源系统和接地系统的配置因与上述第1实施例相同的理由,可分配给凸点5。
[第3、4实施例]
图3和4分别表示本发明的第3和4实施例的半导体器件的剖面简图,是上述第1和第2实施例的半导体器件的变形例。这第3和4实施例中,替代布线板7使用低成本引线框8。其他基本结构与第1和第2实施例相同,所以在图3和图4中,与图1和图2相同的结构部分附加相同的标号,其说明从略。
一般地,引线框8上装载半导体芯片1时,不同形成使用布线板7时那样的电源·接地面,因此在电源补充这一点上是不利的。但是,本实施例的半导体期间中,电源·接地全部直接从半导体芯片1的正下方供给,因此实际可确保充分的性能。
[第5、6实施例]
图5和6分别表示本发明的第5和6实施例的半导体器件的剖面简图,是上述第1和第2实施例的半导体器件的另外的变形例。这第5和6实施例中,在热熔渣(heat slag)10上装载半导体芯片1和布线板7。上述热熔渣10是形成金属层或金属布线的陶瓷板,或者金属板,上述金属部连接于电源或接地。
并且,第5实施例中,在上述热熔渣10上将半导体元件的形成面2朝下装载半导体芯片1。上述半导体芯片1的半导体元件的形成面2上设置的连接端子(导电性凸点)4连接于上述热熔渣10上的金属部。配置布线板7以包围半导体芯片1。该布线板7的上面设置安装用的连接端子13。上述半导体芯片1的连接端子(凸点)5与布线板7的布线7B由键合引线6电连接。之后,上述半导体芯片1、键合引线6和上述布线板7的芯片1附近的树脂被封装在树脂等构成的封装9中。
在上述结构中,半导体元件的形成面2上分散配置的连接端子4被分配给电源系统或接地系统,从半导体芯片1的元件形成面2侧经连接端子4连接于上述热熔渣10上的金属布线层。沿着半导体元件的形成面2的背面一侧的芯片外周部配置的连接端子5被分配给信号系统,从半导体芯片1的元件形成面2侧分别经通孔3内的导电性部件15、连接端子5、键合引线6和布线板7中的布线7B连接于上述连接端子13。
另一方面,第6实施例中,在上述热熔渣10上将半导体元件的形成面2朝上装载半导体芯片1。上述半导体芯片1的背面一侧上经通孔3设置的连接端子(导电性凸点)5连接于上述热熔渣10上的金属布线层,把布线板7配置成包围半导体芯片1,在该布线板7的上面设置安装用的连接端子13。之后,通过键合引线6电连接上述半导体芯片1的半导体元件的形成面2侧上设置的连接端子(凸点)4和布线板7的布线7B。将上述半导体芯片1、键合引线6和上述布线板7的芯片1附近的区域封装在树脂等构成的封装9中。
在上述结构中,半导体元件的形成面2的背面一侧上分散配置的连接端子5被分配给电源系统或接地系统,从半导体芯片1的元件形成面2侧经连接端子5连接于上述热熔渣10上的金属布线层。沿着半导体元件的形成面2一侧的芯片外周部配置的连接端子4被分配给信号系统,分别经该连接端子4、键合引线6和布线板7中的布线7B连接于上述连接端子13。
[第7、8实施例]
图7和8分别表示本发明的第7和8实施例的半导体器件的剖面简图,是上述第5和第6实施例的半导体器件的变形例。这第7和8实施例中,在图5和图6的热熔渣10与半导体芯片1之间插入高放热树脂层11。
此时,第7实施例中,将上述半导体芯片1的半导体元件的形成面2上设置的连接端子4连接于上述热熔渣10上的金属部,该半导体芯片1和热熔渣10之间的间隙用高放热树脂层11埋置。
另一方面,第8实施例中,将在上述半导体芯片1的背面一侧上经通孔3设置的连接端子5连接于上述热熔渣10上的金属部,该半导体芯片1和热熔渣10之间的间隙用高放热树脂层11埋置。
根据这种结构,与第5和第6实施例的半导体器件相比,可再提高放热性。
图7和图8中,以在半导体芯片1与热熔渣10之间使用连接端子4或5分别连接的情况为例说明,但把连接端子4或5用于电源系统或接地系统的情况下,通过在高放热树脂层11中使用高导电性的树脂,可一起连接。
[第9、10实施例]
图9和10分别表示本发明的第9和10实施例的半导体器件的剖面简图,是上述第7和第8实施例的半导体器件的变形例。这第9和10实施例中,替代引线键合技术,使用TAB技术。
即,第9实施例在上述热熔渣10上半导体元件的形成面2朝下装载半导体芯片1。设置在上述半导体芯片1的半导体元件的形成面2上的连接端子4与上述热熔渣10上的金属布线层连接。上述半导体芯片1的元件形成面2与热熔渣10的间隙中填充高放热树脂层11。上述半导体芯片1配置在TAB带7’的器件孔内,在设置成包围该半导体芯片1的热熔渣10A上固定。该TAB带7’的上面形成的引线上设置安装用的连接端子13。上述TAB带7’上设置的梁式引线12连接于上述半导体芯片1的连接端子5上。将上述半导体芯片1、梁式引线12和上述TAB带7’的芯片1附近区域封装在例如滴下粘结树脂形成的封装9’中。
上述结构中,半导体元件的形成面2上分散配置的连接端子4被分配给电源系统或接地系统,从半导体芯片1的元件形成面2侧经连接端子4连接于上述热熔渣10上的金属部。半导体元件的形成面2的背面一侧的连接端子5被分配给信号系统,从半导体元件的形成面2侧分别经通孔3内的导电性部件15、连接端子5、梁式引线12和布线板7中的布线7B连接于上述连接端子13。
另一方面。第10实施例中,上述热熔渣10上把半导体元件的形成面2朝上装载半导体芯片1。上述半导体芯片1的背面一侧上经通孔3设置的连接端子5连接于上述热熔渣10上的金属布线层。上述半导体芯片1的背面和热熔渣10之间的间隙中填充高放热树脂层11。上述半导体芯片1配置在TAB带7’的器件孔内,在设置成包围该半导体芯片1的热熔渣10A上固定。该TAB带7’的上面形成的引线上设置安装用的连接端子13。TAB带7’的梁式引线连接于上述半导体芯片1的半导体元件的形成面2侧上设置的连接端子4。将上述半导体芯片1、梁式引线12和上述TAB带7’的芯片1附近区域封装在例如滴下粘结树脂形成的封装9’中。
上述结构中,半导体元件的形成面2的背面上分散配置的连接端子5被分配给电源系统或接地系统,从半导体芯片1的元件形成面2侧经连接端子5连接于上述热熔渣10上的金属布线层。半导体元件的形成面2的背面一侧的连接端子4被分配给信号系统,分别经该连接端子4、梁式引线12和布线板7中的布线7B连接于上述连接端子13。
根据上述第9、第10实施例,与第5、第6实施例的半导体器件相比,提高放热性,并且可将本发明适用于应用TAB技术的半导体器件中。
假设树脂层11是绝缘性隔热材料,通过连接端子4或5与热熔渣连接,与仅粘贴隔热树脂的情况相比,可得到高的放热性。
图9和图10中,以在半导体芯片1和热熔渣10之间用连接端子4或5分别连接的情况为例说明,但与第7和第8实施例一样,若在高放热树脂层11中使用导电性高的树脂,则可一起连接。
[第11、12实施例]
图11和12分别表示本发明的第11和12实施例的半导体器件的剖面简图,是上述第1和第2实施例的半导体器件的变形例。这第11和12实施例中,在封装9的半导体芯片1上设置放热板。这里,放热板使用热熔渣10,该热熔渣10的表面不用树脂涂覆而露出来。
本实施例中,热熔渣102仅用于放热,因此不必要施加电位。因此,也未必是导体,是不具有布线的简单的陶瓷也可以。当然,金属也无妨。
根据上述的结构,进一步提高放热效果,适合于使用发热量多的半导体芯片1。
[第13、14实施例]
图13和14分别表示本发明的第13和14实施例的半导体器件的剖面简图,是上述第3和第4实施例的半导体器件的变形例。这第13和14实施例与上述第11和12实施例一样,在封装9的半导体芯片1上设置放热板。这里,将热熔渣10设置为放热板,该热熔渣10的表面不用树脂涂覆而露出来。
本实施例中,热熔渣10仅用于放热,因此不必要施加电位。因此,也未必是导体,是不具有布线的简单的陶瓷也可以。当然,金属也无妨。
根据上述的结构,进一步提高放热效果,适合于将使用发热量多的半导体芯片1装载在引线框8上。
[第15至18实施例]
图15至18分别表示本发明的第15至18的实施例的半导体器件的剖面简图,是上述第1和第2实施例的半导体器件的改进例。第15和第17的实施例在第1实施例的半导体芯片1-1上层叠另一半导体芯片1-2,第16和18实施例在第二实施例的半导体芯片1-1上层叠另一半导体芯片1-2。第15和16实施例是将键合引线6用于与上面装载的半导体芯片1-2连接的例子。第17和18实施例是将导电凸点4-2用于与上面装载的半导体芯片1-2连接的例子。
上述的第15到18的实施例中,任一实施例中在下面装载的半导体芯片1-1都具有在整个芯片上分散配置的连接端子4-1或5,因此将对芯片内部压降敏感的元件配置在下面来装载,使得提高半导体器件的性能。
另外,第17和18实施例的情况下,可以贯通芯片1-1(经通孔3)向上面的芯片1-2提供电源电位和接地电位,实现更高性能的半导体器件。
这些第15到18的实施例中,表示出各半导体芯片1-1,1-2与布线板7之间、半导体芯片1-1,1-2彼此之间都连接的例子,但可不连接全部的组合。层叠的半导体芯片的数目不限于实施例所示的2个,3个以上也可以。而且,本实施例中,在上述层叠的半导体芯片1-2以不具有通孔3的通常的半导体芯片为例说明,但层叠具有埋置导电性部件的通孔3的半导体芯片也可以。
[第19和20实施例]
图19和20分别表示本发明的第19和20实施例的半导体器件的剖面简图。这些第19和20实施例是为提高上述第15和16实施例的半导体器件的放热性而在封装9的半导体芯片1-2上设置放热板的例子。这里,作为放热板,可设置热熔渣10,该热熔渣10的表面不用树脂涂覆而露出来。该结构中,热熔渣10的金属或金属布线上不必要施加电位。
根据这种结构,可进一步提高放热效果,有效降低通过层叠半导体芯片1-1,1-2增加的发热量。
上述第19和20实施例中,以为提高上述第15和16实施例的半导体器件的放热性而设置热熔渣10为例说明,但同样的结构可用于图17和图18所示的第17和18的实施例。
[第21和22实施例]
图21和22分别表示本发明的第21和22实施例的半导体器件的剖面简图。这些第21和22实施例是为提高上述第17和18实施例的半导体器件的放热性而在封装9上面露出半导体芯片1-2的例子。
即使是这种结构,可提高放热效果,有效降低通过层叠半导体芯片1-1,1-2增加的发热量。
[第23和24实施例]
图23和24分别表示本发明的第23和24实施例的半导体器件的剖面简图。本实施例中,经导电性凸点4-2和5或导电性凸点4-1将2个半导体芯片1-1,1-2相对连接。半导体芯片1-1,1-2的间隙中用树脂填充来加固。
形成通孔3的半导体芯片1-1由于通孔3的深度制约而必然很薄。因此,为对具有该通孔3的半导体芯片1-1的强度不足进行加固,最好是把不具有相对的通孔的半导体芯片1-2设计得厚且大。
本实施例中,将在半导体芯片1-1的与半导体芯片1-2的层叠面的背面一侧上形成的连接端子(图23的情况下为4-1,图24的情况下为5)用作与安装基板的外部连接端子,从而作为CSP(芯片尺寸封装)。但是,这些连接端子可连接于封装用布线板和引线框,形成封装或模块。
[第25和26实施例]
图25和26分别表示本发明的第25和26实施例的半导体器件的剖面简图。这些实施例是在将上述图23和24所示的第23和24的实施例的半导体器件分别装载在布线板7上的同时,在半导体芯片1-1和1-2之间以及半导体芯片1和布线板7之间注入封装树脂而封装化或模块化。在图25和26中,与图23和24相同的结构部附加相同的标号,其说明从略。
根据这种结构,半导体芯片1-1、1-2二者在薄厚情况下都不会有强度不足的问题,并且使用方便性提高。
图23和24的实施例中,半导体芯片1-1的与半导体芯片1-2的层叠面的背面一侧上形成的连接端子(图23的情况下为4-1、在图24的情况下为5)的数目增大而高密度化时,安装基板上难以回引,而本发明的情况下,使用布线板7可缓和外部连接端子13的间距,因此在具有多个外部连接端子的情况下也有效。
[第27和28实施例]
图27和28分别表示本发明的第27和28实施例的半导体器件的剖面简图。这些实施例是在上述图25和26所示的第25和26的实施例的半导体器件的半导体芯片1-2上使用高放射性树脂11贴付热熔渣10。
根据这种结构,提高放热性同时,避免半导体芯片1-2露出,保护芯片1-2。
以上使用图1至图28的实施例说明了本发明,但本发明并不限于上述各实施例,在各实施阶段中,在不背离其主旨的范围内可作种种变形。上述各实施例中包含多种阶段的发明,通过适当组合公开的多个构成部件可提取出多种发明。例如,在即使从各实施例中所示的全部构成部件中去掉几个构成部件,也可解决发明要解决的问题栏中所述的至少一个,从而得到发明的效果栏中说明的效果中的至少一个的情况下,去掉该构成部件的结构可作为发明提取出来。
发明效果
如上说明,根据本发明,得到以最低成本实现必要功能的半导体器件。
得到一种半导体器件,即使因伴随半导体集成电路的精细化的电源电压的低压化和电路规模增大而扩大半导体芯片尺寸,也可抑制半导体芯片内部的压降。
而且,得到具有高性能和廉价的封装结构的半导体器件。
Claims (16)
1.一种半导体器件,其特征在于包括:
形成半导体元件的第一半导体芯片;
设置在上述第一半导体芯片的半导体元件的形成面一侧上、与该半导体元件电连接的第一连接端子;
埋置在贯通上述第一半导体芯片的通孔内的导电性部件;
设置在上述第一半导体芯片的半导体元件的形成面的背面一侧上、经上述导电性部件与上述半导体元件电连接的第二连接端子;
装载上述第一半导体芯片的布线板;
至少一部分形成在上述布线板的与上述第一连接端子和第二连接端子之一对应的位置上、与第一连接端子或第二连接端子电连接的第三连接端子。
2.一种半导体器件,其特征在于包括:
形成半导体元件的第一半导体芯片;
设置在上述第一半导体芯片的半导体元件的形成面一侧上、与该半导体元件电连接的第一连接端子;
埋置在贯通上述第一半导体芯片的通孔内的导电性部件;
设置在上述第一半导体芯片的半导体元件的形成面的背面一侧上、经上述导电性部件与上述半导体元件电连接的第二连接端子;
装载上述第一半导体芯片、在与上述第一连接端子和第二连接端子之一相对的位置上电连接至少一部分的引线框;
密封上述引线框的内引线部与上述第一半导体芯片的封装。
3.一种半导体器件,包括:
形成半导体元件的第一半导体芯片;
设置在上述第一半导体芯片的半导体元件的形成面一侧上、与该半导体元件电连接的多个第一连接端子;
埋置在贯通上述第一半导体芯片的通孔内的多个导电性部件;
设置在上述第一半导体芯片的半导体元件的形成面的背面一侧上、经上述导电性部件与上述半导体元件电连接的多个第二连接端子,
上述第一连接端子和第二连接端子被连接安装在安装基板上。
4.根据权利要求3所述的半导体器件,其特征在于使上述多个第一连接端子和第二连接端子至少之一方的连接端子面对布线板的芯片侧的表面,并且所述一方的连接端子的平均密度比另一方的连接端子的平均密度低。
5.根据权利要求4所述的半导体器件,其特征在于使上述第一连接端子和第二连接端子至少之一方的一部分分散配置在上述半导体芯片的整个区域上,同时施加电源电位或接地电位。
6.根据权利要求1所述的半导体器件,其特征在于还具有键合引线,将上述第一半导体芯片的上述第一连接端子或第二连接端子中未用于和上述布线板对向连接的那一方的连接端子的至少一部分与上述布线板上形成的上述第三连接端子连接起来。
7.根据权利要求2所述的半导体器件,其特征在于还具有键合引线,将上述第一半导体芯片的第一连接端子或第二连接端子中未用于和引线框对向连接的那一方的连接端子的至少一部分与上述引线框的内引线部连接起来。
8.根据权利要求1所述的半导体器件,其特征在于还具有在上述第一半导体芯片上层叠的第二半导体芯片,将上述第一半导体芯片的第一连接端子或第二连接端子中未用于和上述布线板对向连接的那一方的连接端子的至少一部分与上述第二半导体芯片连接起来。
9.根据权利要求1所述的半导体器件,其特征在于还具有在上述第一半导体芯片上层叠的第二至第n(n为3以上的正整数)半导体芯片,将上述第一半导体芯片的第一连接端子或第二连接端子中未用于和上述布线板对向连接的那一方的连接端子的至少一部分与上述第二至第n半导体芯片连接起来。
10.根据权利要求2所述的半导体器件,其特征在于还具有在上述第一半导体芯片上层叠的第二半导体芯片,将上述第一半导体芯片的第一连接端子或第二连接端子中未用于和上述引线框对向连接的那一方的连接端子的至少一部分与上述第二半导体芯片连接起来。
11.根据权利要求2所述的半导体器件,其特征在于还具有在上述第一半导体芯片上层叠的第二至第n(n为3以上的正整数)半导体芯片,将上述第一半导体芯片的第一连接端子或第二连接端子中未用于和上述引线框对向连接的那一方的连接端子的至少一部分与上述第二至第n半导体芯片连接起来。
12.根据权利要求3所述的半导体器件,其特征在于还具有在上述第一半导体芯片上层叠的第二半导体芯片,将上述第一半导体芯片的第一连接端子或第二连接端子中第一半导体芯片和第二半导体芯片的层叠面一侧的连接端子的至少一部分与上述第二半导体芯片连接起来。
13.根据权利要求3所述的半导体器件,其特征在于还具有在上述第一半导体芯片上层叠的第二至第n(n为3以上的正整数)半导体芯片,将上述第一半导体芯片的第一连接端子和第二连接端子中第一半导体芯片和第二半导体芯片的层叠面一侧的连接端子的至少一部分与上述第二至第n半导体芯片连接起来。
14.根据权利要求8-13之一所述的半导体器件,其特征在于还具有连接上述层叠的多个半导体芯片之间的至少一部分的键合引线。
15.根据权利要求8-13之一所述的半导体器件,其特征在于还具有连接上述层叠的多个半导体芯片之间的至少一部分的导电性凸点。
16.一种半导体器件,包括:
形成半导体元件的第一半导体芯片;
设置在上述第一半导体芯片的半导体元件的形成面一侧上、与该半导体元件电连接的第一连接端子;
埋置在贯通上述第一半导体芯片的通孔内的导电性部件;
设置在上述第一半导体芯片的半导体元件的形成面的背面一侧上、经上述导电性部件与上述半导体元件电连接的第二连接端子;
层叠在上述第一半导体芯片上的第二半导体芯片;
设置在上述第二半导体芯片的半导体元件的形成面一侧上的第三连接端子,
将上述第一半导体芯片的第一连接端子和第二连接端子之一设置在与上述第二半导体芯片的第三连接端子相对的位置上,经该相对的连接端子之间把上述第一半导体芯片与第二半导体芯片电连接起来,并且上述第二半导体芯片比上述第一半导体芯片厚且大。
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Application Number | Priority Date | Filing Date | Title |
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JP2000309764A JP3854054B2 (ja) | 2000-10-10 | 2000-10-10 | 半導体装置 |
JP309764/2000 | 2000-10-10 | ||
JP309764/00 | 2000-10-10 |
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CN1359154A true CN1359154A (zh) | 2002-07-17 |
CN1197153C CN1197153C (zh) | 2005-04-13 |
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US (1) | US20020041027A1 (zh) |
JP (1) | JP3854054B2 (zh) |
KR (1) | KR100574727B1 (zh) |
CN (1) | CN1197153C (zh) |
TW (1) | TW518742B (zh) |
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-
2001
- 2001-10-09 TW TW090124954A patent/TW518742B/zh not_active IP Right Cessation
- 2001-10-09 KR KR1020010062109A patent/KR100574727B1/ko not_active IP Right Cessation
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Cited By (4)
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CN100405591C (zh) * | 2004-03-10 | 2008-07-23 | 株式会社东芝 | 半导体器件及其制造方法 |
CN100380637C (zh) * | 2004-05-12 | 2008-04-09 | 日本电气株式会社 | 布线板及使用该板的半导体封装 |
CN100447966C (zh) * | 2004-05-12 | 2008-12-31 | 库利克和索夫工业公司 | 集成球与过孔的封装和形成工艺 |
CN1985371B (zh) * | 2004-07-13 | 2011-12-28 | Nxp股份有限公司 | 包含集成电路的电子器件 |
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KR100574727B1 (ko) | 2006-04-28 |
JP2002118198A (ja) | 2002-04-19 |
CN1197153C (zh) | 2005-04-13 |
US20020041027A1 (en) | 2002-04-11 |
JP3854054B2 (ja) | 2006-12-06 |
KR20020028812A (ko) | 2002-04-17 |
TW518742B (en) | 2003-01-21 |
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