JP2008010512A - 積層型半導体装置 - Google Patents
積層型半導体装置 Download PDFInfo
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- JP2008010512A JP2008010512A JP2006177123A JP2006177123A JP2008010512A JP 2008010512 A JP2008010512 A JP 2008010512A JP 2006177123 A JP2006177123 A JP 2006177123A JP 2006177123 A JP2006177123 A JP 2006177123A JP 2008010512 A JP2008010512 A JP 2008010512A
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- semiconductor chip
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48095—Kinked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Wire Bonding (AREA)
Abstract
【解決手段】 共通配線基板4と、一主面に設けられた突起電極5を介して共通配線基板4にフリップチップ接続される第1の半導体チップ2と、第1の半導体チップ2上に搭載された第2の半導体チップ3と、を備え、第1の半導体チップ2が第1の半導体チップ2の一主面と対向する他の主面側に第1の半導体チップ2と一体化されて設けられた裏面配線層1を有し、第2の半導体チップ3が第2の半導体チップ3の一主面に設けられた突起電極5を介して裏面配線層1にフリップチップ接続され、裏面配線層1に設けられた外部接続用パッドがワイヤ7を介して共通配線基板4のパッドに接続されている。
【選択図】 図1
Description
2 第1の半導体チップ
3、3a、3b 第2の半導体チップ
4 共通配線基板
5 突起電極
6 アンダーフィル材
7 ワイヤ
8 外部電極
9 封止樹脂
10 外部接続用パッド
11 内部接続用パッド
12 絶縁層
13 配線層
14 裏面電極
15 第3の半導体チップ
16 スペーサ
17 配線フィルム
18 接着剤
Claims (5)
- 共通配線基板と、一主面に設けられた突起電極を介して前記共通配線基板にフリップチップ接続される第1の半導体チップと、前記第1の半導体チップ上に搭載された第2の半導体チップと、を備え、前記第1の半導体チップが前記第1の半導体チップの前記一主面に対向する他の主面側に前記第1の半導体チップと一体化して設けられた裏面配線層を有し、前記第2の半導体チップが前記第2の半導体チップの一主面に設けられた突起電極を介して前記裏面配線層にフリップチップ接続され、前記裏面配線層に設けられた外部接続用パッドがワイヤを介して前記共通配線基板のパッドに接続されていることを特徴とする半導体装置。
- 請求項1に記載の半導体装置において、さらに前記第1の半導体チップ上に搭載された1つ以上の半導体チップを備え、前記1つ以上の半導体チップが前記1つ以上の半導体チップの一主面に設けられた突起電極を介して前記第1の半導体チップの前記裏面配線層にフリップチップ接続されていることを特徴とする半導体装置。
- 請求項1に記載の半導体装置において、さらに前記第2の半導体チップ上に搭載された第3の半導体チップを備え、前記第2の半導体チップが前記第2の半導体チップの前記一主面に対向する面側に前記第2の半導体チップと一体化されて設けられた裏面配線層を有し、前記第3の半導体チップが前記第3の半導体チップの一主面に設けられた突起電極を介して前記第2の半導体チップの前記裏面配線層にフリップチップ接続されていることを特徴とする半導体装置。
- 請求項1乃至3に記載の半導体装置において、前記裏面配線層の直下に裏面電極が形成され、前記裏面電極がワイヤを介して前記共通配線基板のパッドに接続されていることを特徴とする半導体装置。
- 請求項1乃至4に記載の半導体装置において、前記裏面配線層が多層配線層であることを特徴とする半導体装置。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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JP2006177123A JP2008010512A (ja) | 2006-06-27 | 2006-06-27 | 積層型半導体装置 |
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JP2006177123A JP2008010512A (ja) | 2006-06-27 | 2006-06-27 | 積層型半導体装置 |
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JP2008010512A true JP2008010512A (ja) | 2008-01-17 |
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JP2006177123A Pending JP2008010512A (ja) | 2006-06-27 | 2006-06-27 | 積層型半導体装置 |
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102064163A (zh) * | 2010-04-02 | 2011-05-18 | 日月光半导体制造股份有限公司 | 堆栈封装组件 |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH06177213A (ja) * | 1992-12-09 | 1994-06-24 | Mitsubishi Electric Corp | 半導体装置 |
JP2002110902A (ja) * | 2000-10-04 | 2002-04-12 | Toshiba Corp | 半導体素子及び半導体装置 |
JP2002118198A (ja) * | 2000-10-10 | 2002-04-19 | Toshiba Corp | 半導体装置 |
JP2006005260A (ja) * | 2004-06-21 | 2006-01-05 | Matsushita Electric Ind Co Ltd | 半導体装置およびその製造方法 |
JP2006108520A (ja) * | 2004-10-08 | 2006-04-20 | Sharp Corp | 半導体装置及び半導体装置の製造方法 |
-
2006
- 2006-06-27 JP JP2006177123A patent/JP2008010512A/ja active Pending
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH06177213A (ja) * | 1992-12-09 | 1994-06-24 | Mitsubishi Electric Corp | 半導体装置 |
JP2002110902A (ja) * | 2000-10-04 | 2002-04-12 | Toshiba Corp | 半導体素子及び半導体装置 |
JP2002118198A (ja) * | 2000-10-10 | 2002-04-19 | Toshiba Corp | 半導体装置 |
JP2006005260A (ja) * | 2004-06-21 | 2006-01-05 | Matsushita Electric Ind Co Ltd | 半導体装置およびその製造方法 |
JP2006108520A (ja) * | 2004-10-08 | 2006-04-20 | Sharp Corp | 半導体装置及び半導体装置の製造方法 |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102064163A (zh) * | 2010-04-02 | 2011-05-18 | 日月光半导体制造股份有限公司 | 堆栈封装组件 |
CN102064163B (zh) * | 2010-04-02 | 2014-08-27 | 日月光半导体制造股份有限公司 | 堆栈封装组件 |
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