CN1210798C - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

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Publication number
CN1210798C
CN1210798C CNB011450673A CN01145067A CN1210798C CN 1210798 C CN1210798 C CN 1210798C CN B011450673 A CNB011450673 A CN B011450673A CN 01145067 A CN01145067 A CN 01145067A CN 1210798 C CN1210798 C CN 1210798C
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superiors
film
wiring
semiconductor device
copper wiring
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CNB011450673A
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CN1359155A (zh
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石丸一成
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Toshiba Corp
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Toshiba Corp
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    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
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Abstract

一种具有可通过能量束切断的熔丝的半导体器件，所述半导体器件具有：在形成多个半导体元件的半导体衬底上配置的由铜布线构成的多个铜布线层；配置在多个所述铜布线层上方、至少包含连接于最上层的所述铜布线的高熔点金属膜的最上层布线；作为所述最上层布线的一部分形成的熔丝；配置在所述最上层布线上的表面保护膜。

Description

半导体器件及其制造方法
技术领域
本发明涉及半导体器件及其制造方法，尤其涉及具有在使用铜布线时构成冗余电路的一部分的熔丝的半导体器件及其制造方法。另外，涉及适合于具有突出电极(凸点)的倒装片安装的半导体器件及其制造方法。
技术背景
近年来，在半导体集成电路装置中，电路功能在提高和存储容量在增大。另一方面，通过元件、布线的细微化、金属布线的多层化等，半导体芯片制造中的缺陷产生率增高，恐怕随之而来的是半导体芯片的制造合格率降低。作为抑制这种缺陷产生引起的合格率降低的代表技术之一，可举出冗余结构技术(冗余电路：redundancy circuit)。冗余结构技术是在半导体芯片内预先设置可与缺陷部分置换的预置元件、通过在产生缺陷时将该缺陷部分与预置元件置换修补(repair)半导体芯片的技术。例如，半导体存储器产品中，用预置存储器单元置换包括缺陷存储器单元的列或行。缺陷部分与预置元件的互换通过构成冗余电路的一部分的熔丝(fuse)的切断进行。熔丝的切断方法有例如激光方法和电熔断方法。通常使用多晶硅、金属布线形成熔丝。
在半导体芯片的安装技术领域，替代原有的引线键合(wire bonding)，盛行研究/开发倒装片安装等的引线键合技术。倒装片安装是在半导体芯片表面的电极上形成叫作凸点的突出电极，把芯片正反两面翻转，配合陶瓷等的布线衬底的电极与凸点的位置，通过面朝下的键合进行进接的安装方法。从半导体封装的小型化、高密度安装的角度看，是理想的安装方法。
另外，从低电阻和可靠性提高等观点看，替代原有的铝(Al)布线，金属布线铜(Cu)布线实用化了。随着半导体集成电路装置的大型化、高集成化，布线层数增加，在现有的高速SRAM(静态RAM)中使用4层、在混合存储器的逻辑电路LS1中使用5层以上的多个布线层。还有，从电源电压的稳定等角度看，金属布线的膜厚形成为上层比下层厚。
发明内容
本发明就是为了解决现有技术中存在的问题所提出的。
本发明的一个目的是提供一种熔丝熔断容易，并且熔丝上的绝缘膜的膜厚控制容易的半导体器件及其制造方法。
本发明的另一个目的是提供一种在衬底·布线工序(晶片工序)中形成熔断容易的熔丝的半导体器件及其制造方法。
本发明的一个方面是一种半导体器件，具有：在形成多个半导体元件的半导体衬底上配置的由铜布线构成的多个铜布线层；配置在多个所述铜布线层上方、至少包含连接于最上层的所述铜布线层的高熔点金属膜的最上层布线；作为所述最上层布线的一部分形成的可通过能量束切断的熔丝；配置在所述最上层布线上的表面保护膜。
本发明的另一个方面是一种半导体器件的制造方法，具有：经层间绝缘膜在半导体衬底上形成由铜布线构成的多个铜布线层；在多个所述铜布线层上方形成至少包含连接于最上层的铜布线的高熔点金属膜的最上层布线；作为所述最上层布线的一部分形成可通过能量束切断的熔丝；在所述最上层布线上形成表面保护膜。
本发明的再一个方面是一种半导体器件，具有：在形成多个半导体元件的半导体衬底上配置的由铜布线构成的多个铜布线层；配置在最上层的所述铜布线上的氮化硅膜；配置在所述氮化硅膜上的氧化硅膜；配置在所述氧化硅膜上、至少包含连接于所述最上层的铜布线的高熔点金属膜和配置在所述高熔点金属膜上的Al系金属膜的最上层布线；作为所述最上层布线的一部分形成、可通过能量束切断的熔丝；包括配置在所述最上层布线上的氧化硅膜和配置在所述氧化硅膜上的氮化硅膜的表面保护膜；配置在所述表面保护膜上的有机树脂膜。
根据本发明，由于形成有熔丝的最上层布线上仅形成表面保护膜10，切断熔丝前，剩余不妨碍熔丝切断的膜厚，不必要预先去除在熔丝上成膜的绝缘膜，容易切断熔丝。在铜布线层中不必要形成熔丝，因此，不必要把在铜布线层上成膜的层间绝缘膜和表面保护膜减薄到不妨碍熔丝切断的厚度范围内。另外，由于熔丝上形成保护膜，露出部分的熔丝腐蚀了，不用担心杂质离子从露出部分进入，造成缺陷。
此外，由于可去掉用于控制熔丝的绝缘膜的膜厚的蚀刻工序，提高生产效率，降低生产成本。熔丝的图案形成时不使用各向同性的蚀刻处理的侧蚀刻，熔丝的切断部分的图案宽度等的设计自由度不变小。势垒金属(凸点用下层金属膜)的形成工序和焊锡球的形成工序之前，作为布线层的一部分，形成熔丝，因此在进行布线工序的生产线上，实施半导体芯片的动作测试，实施熔丝熔断不良的位置与预置元件的置换。从而，仅对于动作测试中选择的合格品芯片实施势垒金属形成工序和凸点形成工序等的组装工序，生产率提高。
附图说明
图1是表示本发明的实施例的半导体器件的结构内包括熔丝的特征部分的剖面图。
图2A～C是表示本发明的实施例的半导体器件的制造方法中的主要制造工序的剖面图(其一)。
图3A～C是表示本发明的实施例的半导体器件的制造方法中的主要制造工序的剖面图(其二)。
图4A和图4B是表示本发明的实施例的半导体器件的制造方法中的主要制造工序的剖面图(其三)。
图5是表示在最上层布线与第二铜布线之间形成的电容器的结构的剖面图。
图6是表示在与图1的第二铜布线层与高熔点金属膜的连接处的正上方不同的部分中配置势垒金属和焊锡球时的结构剖面图。
图7A是表示相关技术的半导体芯片的器件区域与焊盘区域的布局的平面图。
图7B是表示本发明的实施例的半导体芯片的器件区域与焊盘区域的布局的平面图。
具体实施方式
下面将参考附图说明本发明的各个实施例。注意整个图中相同或类似的参考序号适用于相同或相似的部件和元件，省略或简化对相同或相似部件和元件的说明。
如图1所示，本发明实施例的半导体器件具有：半导体衬底；在半导体衬底的表面上形成的多个半导体元件；相互连接多个半导体元件的由铜构成的多个铜布线层1，2；配置在多个铜布线层1，2上方、至少包含连接于最上层的铜布线2的高熔点金属膜8的最上层布线8，9；作为最上层布线8，9的一部分形成的可通过能量束切断的熔丝；配置在最上层布线8，9上的表面保护膜10；配置在表面保护膜10上、相对表面保护膜10具有很大的蚀刻选择比的有机树脂膜(聚酰亚胺)11；配置在聚酰亚胺11上、连接于最上层布线8，9的凸点用下层金属膜(势垒金属)14；配置在凸点用下层金属膜14上的凸点(焊锡球)15。图1中，表示出多个铜布线层的一部分1，2、最上层布线8，9；表面保护膜10；聚酰亚胺11；势垒金属14；焊锡球15，省略了半导体衬底、半导体元件、铜布线层的剩余部分。
铜布线配置在形成多个半导体元件的半导体衬底上，通过多个半导体元件相互连接，在半导体衬底上形成半导体集成电路。多个铜布线层1，2经层间绝缘膜3，4层叠，通过上下不同的铜布线1，2在配置于层间绝缘膜3，4内的连接处(线接触)连接，形成具有多层布线结构的半导体集成电路。铜布线不限于仅以铜为材料的情况，以铜和其他金属的合金为材料也无妨。
最上层布线是在最上层的铜布线2和表面保护膜10之间配置的布线，至少具有在与最上层的铜布线2的连接中抑制铜扩散的高熔点金属膜8。因此，最上层布线8，9具有多个膜结构的情况下，最下层配置的膜为与最上层的铜布线2连接的高熔点金属膜8。高熔点金属膜8例如以钛(Ti)、钽(Ta)、钼(Mo)、钨(W)及含有这些金属的合金为材料。最上层布线8，9还有配置在高熔点金属膜8上的Al系金属膜9。
作为最上层布线8，9的一部分形成电极焊盘，经该电极焊盘供给半导体元件动作必须的功率，或者输入输出半导体集成电路的信号。在电极焊盘的键合方法是引线键合方法的情况下，希望在高熔点金属膜上形成500nm左右的Al系金属膜9。使用凸点的倒装片安装等的无引线键合方法的情况下，最上层布线8，9仅用高熔点金属膜8构成即可。
熔丝是构成半导体集成电路的一部分的电路器件，不只作为多晶硅等构成的半导体元件或铜布线的一部分形成，可作为最上层布线8，9的一部分形成。熔丝例如包括构成用于替换半导体芯片上的缺陷部分和预置元件的冗余电路的一部分的熔丝等。此外，还包括目的在于在半导体器件制造结束后照射能量束来打算切断的熔丝。
表面保护膜10是用于保护半导体芯片的功能的膜，通过CVD法等成膜。由于表面保护膜10是在熔丝上形成的绝缘膜，表面保护膜10的膜厚可选择在不妨碍熔丝切断的范围，例如50到1000nm的范围内。
凸点15表示倒装片安装等的无引线键合技术中的突出电极，连接于选择性去除了表面保护膜的电极焊盘。凸点以锡(Sn)、铅(Pb)、银(Ag)等的合金为材料。这里，说明使用焊锡球15的情况。
凸点用下层金属膜(势垒金属)14配置在电极焊盘与凸点15之间，是用于提高电极焊盘与凸点15之间的结合性的金属膜。层叠钛(Ti)、铬(Cr)、Cu、金(Au)、镍(Ni)等的金属膜而成。
图1中，作为多个铜布线层的一部分，表示出第一铜布线层1和第二铜布线层2。在第一铜布线层下配置第一层间绝缘膜3，在第一铜布线层和第二铜布线层之间配置第二层间绝缘膜4。第二铜布线层2具有双金属镶嵌结构。即，第二铜布线层2的一部分作为接触栓塞配置在第二层间绝缘膜4内，经该接触栓塞连接第一铜布线层1和第二铜布线层2。图1中，在右侧、中央、左侧3个位置处配置铜布线1，2，从右侧到中央表示形成熔丝的熔丝区域12、左侧表示形成电极焊盘的焊盘区域13。图1未示出，但在第一铜布线层1和半导体衬底之间配置不同的铜布线层。
第二铜布线层2上配置氮化硅膜6。氮化硅膜6上配置氧化硅膜7。氧化硅膜7上配置高熔点金属膜8。高熔点金属膜8上配置Al系金属膜9。最上层布线具有高熔点金属膜8和Al系金属膜9构成的层叠结构。最上层布线8，9选择地配置在熔丝区域12和焊盘区域13上。高熔点金属膜8分别连接于右侧、中央、左侧的第二铜布线2。熔丝区域12的中央、右侧的第二铜布线2经高熔点金属膜8连接。Al系金属膜9上配置表面保护膜10。表面保护膜10上配置聚酰亚胺11。焊盘区域13的Al膜9上替代表面保护膜10和聚酰亚胺11配置势垒金属14，部分势垒金属14分别配置在表面保护膜10和聚酰亚胺11上。势垒金属14上配置焊锡球15。熔丝区域12的表面保护膜10上不配置聚酰亚胺11，而露出表面保护膜10。
接着，参考图2～图4说明图1所示的半导体器件的制造方法。图2～图4是表示图1所示的半导体器件的制造方法的主要制造工序的剖面图。
(1)首先，在超净间内的生产线上配置半导体晶片，准备进行衬底·布线工序。接着，启动生产线，在衬底工序中，在半导体晶片上形成多个半导体元件。具体说，反复成膜工序、PEP工序、蚀刻工序等，形成用于分离相邻的半导体元件的器件分离区域，在器件区域中形成MOS·FET、双极晶体管等的半导体元件。
(2)接着，在布线工序中，通过金属镶嵌法形成连接于半导体衬底上的半导体元件的铜布线，形成半导体集成电路。具体说，首先，在半导体衬底上成膜层间绝缘膜。在连接于铜布线的半导体元件的各电极部分形成具有窗口的抗蚀剂图案。经该抗蚀剂图案进行各向异性蚀刻，选择地去除半导体元件的各电极部分的层间绝缘膜，形成露出半导体元件的各电极部分的接触孔。
接着，使用溅射法，在接触孔内埋置钛(Ti)、氮化钛(TiN)构成的势垒金属，通过CVD法埋置钨(W)。通过CMP(化学机械研磨)等去除绝缘膜上的剩余的Ti、TiN、W，形成选择地埋置在接触孔内部的W栓塞。接着，再次成膜层间绝缘膜。在布线图案部分形成具有窗口的抗蚀剂图案，经该抗蚀剂图案进行各向异性蚀刻，选择地去除布线图案部分的层间绝缘膜，形成露出W栓塞的金属镶嵌布线沟。之后，在金属镶嵌布线沟内壁上淀积钽(Ta)、氮化钽(TaN)等高熔点金属构成的势垒层。接着，使用真空蒸镀法、电镀等淀积Cu埋入到金属镶嵌布线沟。通过CMP法等去除层间绝缘膜上淀积的剩余的高熔点金属和Cu，形成由选择地埋置在金属镶嵌布线沟内部的高熔点金属和Cu构成的铜布线。经过以上工序，可在半导体衬底上形成层间绝缘膜并在其上形成铜布线层。反复进行以上工序，交互形成层间绝缘膜和铜布线，形成多层布线。
这里，与半导体衬底上的半导体元件的连接部分中使用的W栓塞在第二层以上的布线层中不使用。替代W栓塞，在接触孔与金属镶嵌布线沟中埋置由高熔点金属构成的势垒层和Cu，形成具有图2A所示的双金属镶嵌结构的第二铜布线层2。
(3)接着，如图2A所示，形成第二铜布线层2后，在晶片整个面上作为绝缘膜通过CVD法淀积膜厚为100nm的氮化硅膜6。接着，通过CVD法淀积膜厚为400nm的氧化硅膜7。氮化硅膜6是具有防止铜从第二铜布线层2扩散的功能的绝缘膜。不用说，替代氮化硅膜6，可构成由具有相同功能的其他材料构成的绝缘膜。这里，在第二铜布线层2上淀积最一般的氮化硅膜6。
(4)接着，使用旋涂法，在旋转的晶片上涂布抗蚀剂液，在氧化硅膜7上同样形成抗蚀剂膜。如图2B所示，通过在右侧、中央、左侧的各第二铜布线2上经具有窗口的掩模曝光抗蚀剂膜、显像抗蚀剂膜，在右侧、中央、左侧的各第二铜布线2上形成具有开口部分的抗蚀剂图案17。以抗蚀剂图案17作为掩模使用RIE法进行氧化硅膜7的各向异性蚀刻，选择去除各第二铜布线层2上的氧化硅膜7，露出部分氮化硅膜6。之后，通过灰化(ashing)处理去除抗蚀剂图案17。
(5)接着，如图2C所示，以氧化硅膜7作为掩模进行氮化硅膜6的各向异性蚀刻，选择去除氮化硅膜6，露出各第二铜布线2。这里，使用抗蚀剂图案17，同时蚀刻氧化硅膜7和氮化硅膜6时，抗蚀剂图案17抛光处理时露出的第二铜布线2也一起被氧化了，在电特性方面恶化。因此，通过形成组合了氧化硅膜7和氮化硅膜6等的蚀刻比非常大的2种绝缘膜的层叠膜，可避免第二铜布线2的氧化。不用说，若组合具有非常大的蚀刻比的2种绝缘膜，除此以外的绝缘膜组合也可以。或者，在使用露出的铜不氧化、去除抗蚀剂图案17的处理方法的情况下，替代氧化硅膜7和氮化硅膜6，在第二铜布线层2上形成单层层间绝缘膜，实施一次蚀刻处理即可。使用任何一种方法不会影响本发明的实施例的效果。
(6)接着，如图3A所示，使用溅射法，淀积高熔点金属膜8。高熔点金属膜未必是层叠结构，可以是钽(Ta)、氮化钽(TaN)的单层膜。这里，作为高熔点金属膜8，淀积膜厚为10到60nm的TaN膜，在其上淀积膜厚5nm～20nm的Ta。高熔点金属膜8上使用溅射法淀积膜厚为500nm的Al系金属膜9，形成高熔点金属膜8和Al系金属膜9构成的最上层布线。Al系金属膜9的膜厚是满足熔丝的电阻规格，而且可进行激光熔断的膜厚即可。Al系金属膜9可以是向Al添加几个wt％左右的Cu的AlCu膜或者向Al分别添加几个wt％左右的Cu和硅(Si)的AlSiCu膜。实施例中，假定还进行引线键合的芯片布线，形成仅由膜厚为500nm左右的Al构成的Al膜9。另外，Al的膜厚根据需要不变也可。不进行引线键合而进行焊锡球15的无引线键合结合时，仅用高熔点金属膜8构成最上层布线，不形成Al膜9也可。在实施例中，考虑可相对原来的Al布线原样使用焊锡凸点处理的优点，形成Al膜9。
(7)接着，使用旋涂法在旋转的晶片上涂布抗蚀剂液，在氧化硅膜7上同样形成抗蚀剂膜。如图3B所示，通过规定的掩模曝光抗蚀剂膜、显像抗蚀剂膜，在熔丝区域12和焊盘区域13上选择地形成抗蚀剂图案18。以抗蚀剂图案18作为掩模通过RIE法进行Al膜9和高熔点金属膜8的各向异性蚀刻，选择去除熔丝区域12和焊盘区域13以外的Al膜9和高熔点金属膜8。之后，通过灰化(ashing)处理去除抗蚀剂图案18。替代RIE法等的干蚀刻，通过湿蚀刻选择地去除Al膜9和高熔点金属膜8也可以。通过最上层布线8，9的蚀刻方法不对实施例的效果产生影响。
(8)接着，如图3C所示，使用CVD法等，淀积表面保护膜10。表面保护膜10是形成Al布线时通常使用的氮化硅膜、氮化硅膜与氧化硅膜的层叠膜等构成的保护膜。在实施例中，考虑在焊锡凸点形成工序中使用酸性蚀刻液的情况，表面保护膜10具有淀积膜厚为300nm左右的氧化硅膜，在其上淀积200nm左右的耐酸性的氮化硅膜的层叠结构。表面保护膜10是氮化硅膜的单层膜的情况下，担心氮化硅膜的应力断开最上层布线8，9。因此，Al膜9上淀积吸收氮化硅膜的应力的氧化硅膜，其上淀积耐酸性的氮化硅膜。不用说，用膜应力较小的氮化硅膜，用氮化硅膜的单层膜构成表面保护膜10也无妨。
表面保护膜10的膜厚选择在不妨碍熔丝流动的范围内。通常的熔丝熔断的情况下，通过在熔丝上形成1000nm以下膜厚的绝缘膜，熔丝可熔断。熔丝部分的最上层布线8，9露出时，由于产生腐蚀、污染等，必须层叠50nm以上膜厚的表面保护膜10，该膜厚是保护半导体集成电路功能必须的膜厚。即表面保护膜10可选择在50到1000nm的范围内。实施例中，组合氮化硅膜和氧化硅膜膜厚为500nm。由于熔丝上的绝缘膜的膜厚由层叠膜厚确定，与使用下层布线层形成熔丝，选择地去除熔丝上的绝缘膜的已有方式相比，熔丝上的绝缘膜的膜厚偏差小，可稳定进行熔丝熔断。
(9)接着，使用旋涂法在旋转的晶片上涂布抗蚀剂液，在表面保护膜10上同样形成抗蚀剂膜。如图3C所示，通过规定的掩模曝光抗蚀剂膜、显像抗蚀剂膜，在焊盘区域13上形成具有窗口的抗蚀剂图案19。以抗蚀剂图案19作为掩模通过干蚀刻或湿蚀刻法选择地去除焊盘区域13上的表面保护膜10，露出焊盘区域13的Al膜9。之后，通过灰化处理去除抗蚀剂图案19。
(10)接着，如图4A所示，在表面保护膜10上层叠聚酰亚胺11。从可靠性看可使用聚酰亚胺11，但并不一定使用。聚酰亚按11具有感光性的和非感光性的，但可根据需要选择。实施例中，表示出使用可简化工序的感光性聚酰亚胺的情况。接着，如图4B所示，通过通常的光刻工序，选择地去除熔丝区域12和焊盘区域13的聚酰亚胺11，露出熔丝区域12的表面保护膜10，露出焊盘区域13的Al膜9。由于表面保护膜10相对聚酰亚胺11具有非常大的蚀刻选择比，在露出保护膜的时刻结束蚀刻，从而去除熔丝区域12的聚酰亚胺11，容易露出表面保护膜10。
以上的(1)到(10)的各制造工序通常在1个晶片生产线上连续实施。对结束了以上工序的半导体晶片在晶片检查工序中进行动作测试。例如，半导体存储器的情况下，探针对准各芯片的各电极焊盘(焊盘区域13的Al膜9)，测试各存储器单元的动作。在测试中，对于具有不正常动作的不良存储器单元的芯片，通过激光熔断作为芯片内的冗余电路的一部分的熔丝(熔丝区域12的最上层布线8，9)，用预置存储器单元置换缺陷存储器单元。修补具有不正常动作的存储器单元的缺陷芯片。对于结束了动作测试的晶片，再实施上述探针测试，对通过冗余电路也不能修复的缺陷芯片加上失效标记。接着，从晶片生产线取出半导体晶片，把动作测试判断为合格的芯片配置在进行下面所示的组装工序的生产线上。
(11)最后，对于动作测试中为合格品的芯片，实施通常的焊锡凸点形成处理，分别形成势垒金属14和焊锡球15。经过以上工序，可制造图1所示的半导体器件。
如上说明，根据本实施例，由于形成熔丝的最上层布线8，9上仅形成表面保护膜10，切断熔丝前，剩余不妨碍熔丝切断的膜厚，不必要预先去除在熔丝上成膜的绝缘膜，容易切断熔丝。在铜布线层1，2中不必要形成熔丝，因此，不必要把在铜布线层1，2上成膜的层间绝缘膜3，4和表面保护膜10减薄到不妨碍熔丝切断的厚度范围内。另外，由于熔丝上形成保护膜，露出部分的熔丝腐蚀了，不用担心杂质离子从露出部分进入，造成缺陷。
由于可去掉用于控制熔丝的绝缘膜的膜厚的蚀刻工序，提高生产效率，降低生产成本。熔丝的图案形成时不使用各向同性的蚀刻处理的侧蚀刻，熔丝的切断部分的图案宽度等的设计自由度不变小。势垒金属(凸点用下层金属膜)14的形成工序和焊锡球15的形成工序之前，作为布线层的一部分，形成熔丝，因此在进行布线工序的生产线上，实施半导体芯片的动作测试，实施熔丝熔断不良的位置与预置元件的置换。从而，仅对于动作测试中选择的合格品芯片实施势垒金属形成工序和凸点形成工序等的组装工序，生产率提高。
这样，根据本实施例，可提供一种熔丝熔断容易，并且熔丝上的绝缘膜的膜厚控制容易的半导体器件及其制造方法。
根据本实施例，可提供一种在衬底·布线工序(晶片工序)中形成熔断容易的熔丝的半导体器件及其制造方法。
在本发明的实施例中，如图5所示，在最上层布线8，9和第二铜布线层2之间形成电容器。此时，最上层布线8，9和第二铜布线层2中分别形成平行平板的电极，在氮化硅膜6与氧化硅膜7中形成电场。不增加制造工序形成电容器，可向整个芯片稳定供给电源电压。
焊盘区域13可配置在半导体芯片上的任何位置。即，不仅在不配置半导体芯片外周的半导体元件的区域中配置焊盘区域13，还可在配置半导体元件的器件区域上配置。可对应于使用突出电极(凸点)的倒装片安装中的多管脚化。具体说，势垒金属14和焊锡球15可配置在半导体元件上。如图6所示，在与第二铜布线2和高熔点金属膜8的连接位置的正上方不同的部分中可配置焊盘区域13(势垒金属14和焊锡球15)。
另外，使用最上层布线8，9，可把焊盘区域13引向半导体芯片上的任意部分。图7A表示原有的半导体芯片的布局，图7B表示本发明的半导体芯片的布局。如图7A所示，原来，在芯片中央配置器件区域，在芯片外周配置焊盘区域13。但是，如图7B所示，使用最上层布线8，9，把势垒金属14和焊锡球15引向半导体芯片上的任意部分，使得可把焊盘区域13配置在半导体芯片上的任意部分中。在倒装片安装等的无引线键合技术中，可进行对应于多管脚化的高密度安装。
如上所述，本发明由1个实施例记载，但不应理解为把本发明限定在对公开的部分的说明和附图中。本领域技术人员容易发现另外的优点并作修改。因此，本发明在其更广义方面不限于这里所示和所述的特定细节和代表性实施例。从而，在不背离后附权利要求及它们的等价物所限定的一般性概念的精神或范围的情况下可进行各种修改。

Claims (20)

1.一种半导体器件，其特征在于具有：
在形成多个半导体元件的半导体衬底上配置的由铜布线构成的多个铜布线层；
配置在多个所述铜布线层上方、至少包含连接于最上层的所述铜布线的高熔点金属膜的最上层布线；
作为所述最上层布线的一部分形成、可通过能量束切断的熔丝；
配置在所述最上层布线上的表面保护膜。
2.根据权利要求1的半导体器件，其特征在于还具有：配置在所述表面保护膜上、连接于所述最上层布线的凸点用下层金属膜；配置在所述凸点用下层金属膜上的凸点。
3.根据权利要求1的半导体器件，其特征在于还具有：在所述最上层的铜布线上形成的、包含氮化硅膜和氧化硅膜中的至少一种的绝缘膜，通过在该绝缘膜上形成所述最上层布线，在所述最上层布线和所述最上层的铜布线之间形成电容器。
4.根据权利要求2的半导体器件，其特征在于所述凸点用下层金属膜和所述凸点配置在所述半导体元件的上方。
5.根据权利要求1的半导体器件，其特征在于所述最上层布线还包括配置在所述高熔点金属膜上的Al系金属膜。
6.根据权利要求1的半导体器件，其特征在于所述表面保护膜具有不妨碍所述熔丝切断的膜厚范围。
7.根据权利要求1的半导体器件，其特征在于所述多个铜布线层的至少一部分具有双金属镶嵌结构。
8.一种半导体器件的制造方法，其特征在于具有：
经层间绝缘膜在半导体衬底上形成由铜布线构成的多个铜布线层；
在多个所述铜布线层上方形成至少包含连接于最上层的铜布线的高熔点金属膜的最上层布线；
作为所述最上层布线的一部分形成可通过能量束切断的熔丝；
在所述最上层布线上形成表面保护膜。
9.根据权利要求8的半导体器件的制造方法，还具有：在所述表面保护膜上形成连接于所述最上层布线的凸点用下层金属膜；在所述凸点用下层金属膜上形成凸点。
10.根据权利要求8的半导体器件的制造方法，其特征在于：
在所述最上层的铜布线上还形成包含氮化硅膜和氧化硅膜中的至少一种的绝缘膜，通过在该绝缘膜上形成所述最上层布线，将所述最上层的铜布线的一部分形成为电容器的一个电极，将所述最上层布线的一部分形成为所述电容器的另一个电极。
11.根据权利要求9的半导体器件的制造方法，所述凸点用下层金属膜和所述凸点形成在所述半导体元件的上方。
12.根据权利要求8的半导体器件的制造方法，作为所述最上层布线的一部分，还在所述高熔点金属膜上形成Al系金属膜。
13.根据权利要求8的半导体器件的制造方法，所述表面保护膜的膜厚为50到1000nm。
14.根据权利要求8的半导体器件的制造方法，所述多个铜布线层的至少一部分通过金属镶嵌法形成。
15.一种半导体器件，其特征在于具有：
在形成多个半导体元件的半导体衬底上配置的由铜布线构成的多个铜布线层；
配置在最上层的所述铜布线上的氮化硅膜；
配置在所述氮化硅膜上的氧化硅膜；
配置在所述氧化硅膜上、至少包含连接于所述最上层的铜布线的高熔点金属膜和配置在所述高熔点金属膜上的Al系金属膜的最上层布线；
作为所述最上层布线的一部分形成、可通过能量束切断的熔丝；
包括配置在所述最上层布线上的氧化硅膜和配置在所述氧化硅膜上的氮化硅膜的表面保护膜；
配置在所述表面保护膜上的有机树脂膜。
16.根据权利要求15的半导体器件，还具有：配置在所述有机树脂膜上、连接于所述最上层布线的凸点用下层金属膜；配置在所述凸点用下层金属膜上的凸点。
17.根据权利要求15的半导体器件，其特征在于：
通过所述最上层的铜布线、叠层形成在所述铜布线上的所述氮化硅膜和氧化硅膜以及形成在所述氧化硅膜上的所述最上层布线，在所述最上层布线和所述最上层的铜布线之间形成电容器。
18.根据权利要求16的半导体器件，所述凸点用下层金属膜和所述凸点配置在所述半导体元件的上方。
19.根据权利要求15的半导体器件，所述表面保护膜具有不妨碍所述熔丝切断的膜厚范围。
20.根据权利要求15的半导体器件，所述多个铜布线层的至少一部分具有双金属镶嵌结构。
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