KR100476938B1 - 듀얼 다마신 공정의 퓨즈 형성방법 - Google Patents
듀얼 다마신 공정의 퓨즈 형성방법 Download PDFInfo
- Publication number
- KR100476938B1 KR100476938B1 KR10-2003-0012766A KR20030012766A KR100476938B1 KR 100476938 B1 KR100476938 B1 KR 100476938B1 KR 20030012766 A KR20030012766 A KR 20030012766A KR 100476938 B1 KR100476938 B1 KR 100476938B1
- Authority
- KR
- South Korea
- Prior art keywords
- fuse
- forming
- pattern
- pad
- opening
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
- H01L23/5256—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive
- H01L23/5258—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive the change of state resulting from the use of an external beam, e.g. laser beam or ion beam
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
Claims (9)
- 기판에 듀얼 다마신 공정을 사용하여 배선 패턴 및 퓨즈 패턴을 형성하는 단계;상기 배선 패턴 및 퓨즈 패턴이 형성된 기판 전면에 패시베이션막을 형성하는 단계;상기 패시베이션막을 패터닝하여 상기 배선 패턴의 일부분을 노출시키는 패드 오프닝을 형성하는 단계;상기 패드 오프닝 내의 상기 배선 패턴 상에 상기 패드 오프닝에 인접한 패시베이션막 상으로 신장된 부분을 갖는 금속 패드를 형성하는 단계; 및상기 퓨즈 패턴 상부의 상기 패시베이션막을 부분식각하여 퓨즈 오프닝을 형성하는 단계를 포함하는 퓨즈 형성방법.
- 제1 항에 있어서,상기 패시베이션막은 복수층의 절연막을 적층하여 형성하는 것을 특징으로 하는 퓨즈 형성방법.
- 제1 항에 있어서,상기 배선 패턴 및 상기 퓨즈 패턴은 구리 듀얼다마신 공정을 적용하여 형성하는 것을 특징으로 하는 퓨즈 형성방법.
- 제3 항에 있어서,상기 패시베이션막을 형성하기 전에,상기 배선 패턴 및 상기 퓨즈 패턴이 형성된 기판 상에 구리 확산 방지막을 형성하는 단계를 더 포함하는 것을 특징으로 하는 퓨즈 형성방법.
- 제4 항에 있어서,상기 구리 확산 방지막은 실리콘질화막(silicon nitride), 실리콘산화질화막(silicon oxynitride) 및 실리콘탄화막(silicon cabide)로 구성된 그룹 중 선택된 하나로 형성하는 것을 특징으로 하는 퓨즈 형성방법.
- 제4 항에 있어서,상기 퓨즈 오프닝을 형성하는 단계에서,상기 퓨즈 오프닝 내에 상기 구리 확산 방지막을 노출시키는 것을 특징으로 하는 퓨즈 형성방법.
- 제4 항에 있어서,상기 퓨즈 오프닝을 형성하는 단계에서,상기 구리 확산 방지막 상에 소정 두께의 패시베이션막을 잔존시키는 것을 특징으로 하는 퓨즈 형성방법.
- 제1 항에 있어서,상기 금속 패드를 형성하는 단계는,상기 패드 오프닝을 갖는 상기 패시베이션막 상에 상기 패드 오프닝을 통하여 상기 배선 패턴에 전기적으로 접속된 금속층을 형성하는 단계;및상기 금속층을 패터닝하는 단계를 포함하는 퓨즈 형성방법.
- 제8 항에 있어서,상기 금속층은 알루미늄층을 포함하는 것을 특징으로 하는 퓨즈 형성방법.
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR10-2003-0012766A KR100476938B1 (ko) | 2003-02-28 | 2003-02-28 | 듀얼 다마신 공정의 퓨즈 형성방법 |
US10/787,680 US7101804B2 (en) | 2003-02-28 | 2004-02-25 | Method for forming fuse integrated with dual damascene process |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR10-2003-0012766A KR100476938B1 (ko) | 2003-02-28 | 2003-02-28 | 듀얼 다마신 공정의 퓨즈 형성방법 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR20040077268A KR20040077268A (ko) | 2004-09-04 |
KR100476938B1 true KR100476938B1 (ko) | 2005-03-16 |
Family
ID=32906578
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR10-2003-0012766A KR100476938B1 (ko) | 2003-02-28 | 2003-02-28 | 듀얼 다마신 공정의 퓨즈 형성방법 |
Country Status (2)
Country | Link |
---|---|
US (1) | US7101804B2 (ko) |
KR (1) | KR100476938B1 (ko) |
Families Citing this family (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20060009444A (ko) * | 2004-07-22 | 2006-02-01 | 삼성전자주식회사 | 반도체 소자의 배선 및 그 형성방법. |
KR100595856B1 (ko) * | 2004-12-29 | 2006-06-30 | 동부일렉트로닉스 주식회사 | 반도체 소자 제조 방법 |
KR100770696B1 (ko) * | 2006-06-20 | 2007-10-29 | 삼성전자주식회사 | 퓨즈 구조물 및 그 형성 방법 |
US7622395B2 (en) * | 2006-12-27 | 2009-11-24 | United Microelectronics Corp. | Two-step method for etching a fuse window on a semiconductor substrate |
KR20090070826A (ko) * | 2007-12-27 | 2009-07-01 | 주식회사 하이닉스반도체 | 퓨즈를 구비한 반도체 소자 및 그 제조 방법 |
US7642176B2 (en) * | 2008-04-21 | 2010-01-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Electrical fuse structure and method |
TWI387025B (zh) * | 2009-02-12 | 2013-02-21 | Vanguard Int Semiconduct Corp | 具有熔絲元件之半導體裝置之製造方法 |
KR101079204B1 (ko) | 2009-07-03 | 2011-11-03 | 주식회사 하이닉스반도체 | 반도체 장치의 퓨즈 및 그 제조방법 |
US8623735B2 (en) | 2011-09-14 | 2014-01-07 | Globalfoundries Inc. | Methods of forming semiconductor devices having capacitor and via contacts |
CN103137544B (zh) * | 2011-11-22 | 2015-11-11 | 北大方正集团有限公司 | 一种半导体芯片结构和芯片中金属熔丝的制作方法 |
US9178009B2 (en) | 2012-10-10 | 2015-11-03 | Globalfoundries Inc. | Methods of forming a capacitor and contact structures |
US8809149B2 (en) | 2012-12-12 | 2014-08-19 | Globalfoundries Inc. | High density serial capacitor device and methods of making such a capacitor device |
US8999767B2 (en) * | 2013-01-31 | 2015-04-07 | International Business Machines Corporation | Electronic fuse having an insulation layer |
CN108630664B (zh) * | 2017-03-17 | 2020-06-09 | 中芯国际集成电路制造(上海)有限公司 | 熔丝结构及其形成方法 |
CN109887881B (zh) * | 2019-01-15 | 2020-09-29 | 上海华虹宏力半导体制造有限公司 | 金属保险丝顶部的钝化层窗口的形成方法 |
US11769725B2 (en) * | 2020-11-05 | 2023-09-26 | Changxin Memory Technologies, Inc. | Integrated circuit device and formation method thereof |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0737988A (ja) | 1993-07-20 | 1995-02-07 | Hitachi Ltd | 半導体集積回路装置の製造方法 |
US6677226B1 (en) * | 1998-05-11 | 2004-01-13 | Motorola, Inc. | Method for forming an integrated circuit having a bonding pad and a fuse |
US6440833B1 (en) * | 2000-07-19 | 2002-08-27 | Taiwan Semiconductor Manufacturing Company | Method of protecting a copper pad structure during a fuse opening procedure |
JP3977578B2 (ja) * | 2000-09-14 | 2007-09-19 | 株式会社東芝 | 半導体装置および製造方法 |
US6864124B2 (en) * | 2002-06-05 | 2005-03-08 | United Microelectronics Corp. | Method of forming a fuse |
JP3600598B2 (ja) * | 2002-06-12 | 2004-12-15 | 株式会社東芝 | 半導体装置及びその製造方法 |
US6911386B1 (en) * | 2002-06-21 | 2005-06-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated process for fuse opening and passivation process for CU/LOW-K IMD |
-
2003
- 2003-02-28 KR KR10-2003-0012766A patent/KR100476938B1/ko active IP Right Grant
-
2004
- 2004-02-25 US US10/787,680 patent/US7101804B2/en active Active
Also Published As
Publication number | Publication date |
---|---|
KR20040077268A (ko) | 2004-09-04 |
US20040171263A1 (en) | 2004-09-02 |
US7101804B2 (en) | 2006-09-05 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR100476938B1 (ko) | 듀얼 다마신 공정의 퓨즈 형성방법 | |
US6124194A (en) | Method of fabrication of anti-fuse integrated with dual damascene process | |
US7545037B2 (en) | Semiconductor chips having redistributed power/ground lines directly connected to power/ground lines of internal circuits and methods of fabricating the same | |
US20020063305A1 (en) | Semiconductor device having fuses or anti-fuses | |
TWI311790B (en) | Semiconductor device having bonding pad above low-k kielectric film and manufacturing method therefor | |
KR100524963B1 (ko) | 금속 배선 및 금속 저항을 포함하는 반도체 소자 및 그제조 방법 | |
KR100438206B1 (ko) | Soi구조를 갖는 반도체장치 및 그 제조방법 | |
US20060250139A1 (en) | Bond pad structure comprising multiple bond pads with metal overlap | |
KR20050076800A (ko) | 반도체 장치 및 그 제조 방법 | |
KR20020021342A (ko) | 반도체 장치 및 그 제조 방법 | |
US6818539B1 (en) | Semiconductor devices and methods of fabricating the same | |
KR20040042850A (ko) | 반도체 장치 및 그 제조방법 | |
JP3701877B2 (ja) | キャパシタを有する集積回路 | |
US20050087844A1 (en) | Chip structure and process for forming the same | |
JPH1140564A (ja) | 半導体装置およびその製造方法 | |
KR20010095178A (ko) | 퓨즈를 구비한 반도체장치 | |
KR20060009444A (ko) | 반도체 소자의 배선 및 그 형성방법. | |
US8247289B2 (en) | Capacitor and manufacturing method thereof | |
KR20010017503A (ko) | 반도체 집적회로의 커패시터 제조방법 | |
KR100457044B1 (ko) | 반도체 소자의 제조 방법 | |
JP3123948B2 (ja) | 半導体装置 | |
KR100594219B1 (ko) | 퓨즈를 포함하는 반도체 장치를 제조하는 방법 | |
KR101062820B1 (ko) | 반도체 장치의 퓨즈 및 그 제조방법 | |
KR100244255B1 (ko) | 안티퓨즈 및 그 제조방법 | |
KR19990025489A (ko) | 안티 퓨즈 및 그 형성 방법 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A201 | Request for examination | ||
E701 | Decision to grant or registration of patent right | ||
GRNT | Written decision to grant | ||
FPAY | Annual fee payment |
Payment date: 20130228 Year of fee payment: 9 |
|
FPAY | Annual fee payment |
Payment date: 20140228 Year of fee payment: 10 |
|
FPAY | Annual fee payment |
Payment date: 20150302 Year of fee payment: 11 |
|
FPAY | Annual fee payment |
Payment date: 20170228 Year of fee payment: 13 |
|
FPAY | Annual fee payment |
Payment date: 20180228 Year of fee payment: 14 |
|
FPAY | Annual fee payment |
Payment date: 20200228 Year of fee payment: 16 |