CN111919387B - 具有用于相位检测和相位插值的加权输出段的动态加权异或门 - Google Patents

具有用于相位检测和相位插值的加权输出段的动态加权异或门 Download PDF

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CN111919387B
CN111919387B CN201980019194.0A CN201980019194A CN111919387B CN 111919387 B CN111919387 B CN 111919387B CN 201980019194 A CN201980019194 A CN 201980019194A CN 111919387 B CN111919387 B CN 111919387B
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阿明·塔亚丽
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Kandou Labs SA
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    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0331—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock
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    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
    • H03K19/21—EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical
    • H03K19/215—EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical using field-effect transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/0807—Details of the phase-locked loop concerning mainly a recovery circuit for the reference signal
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/087—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using at least two phase detectors or a frequency and phase detector in the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0079—Receiver details
    • H04L7/0087—Preprocessing of received signal for synchronisation, e.g. by code conversion, pulse generation or edge detection
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

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Abstract

所描述的方法和系统：由包括多个逻辑分支的动态加权XOR门接收参考时钟信号以及本地振荡器信号相位；生成相位误差信号的多个加权段，该多个加权段包括正加权段和负加权段，所述相位误差信号的每一个加权段具有由所述多个逻辑分支当中的相应的逻辑分支所施加的相应的权重；通过将所述相位误差信号的各加权段加总来生成总控制信号；以及将所述总控制信号作为电流模式输出结果输出，以对生成所述本地振荡器信号的相位的本地振荡器进行控制，其中，所述本地振荡器用于响应于所述总控制信号在所述本地振荡器信号中引发相位偏移。

Description

具有用于相位检测和相位插值的加权输出段的动态加权异 或门
相关申请的交叉引用
本申请要求申请号为15/881,509，申请日为2018年1月26日，发明人为ArminTajalli，名称为“具有用于相位检测和相位插值的加权输出段的动态加权异或门”的美国临时申请的权益，并通过引用将其整体并入本文，以供所有目的之用。
参考文献
以下在先申请通过引用整体并入本文，以供所有目的之用：
申请号为15/494，439，申请日为2017年4月21日，发明人为Armin Tajalli，名称为“高性能锁相环”的美国专利申请，下称《Tajalli I》；
申请号为15/602，080，申请日为2017年5月22日，发明人为Armin Tajalli，名称为“用于锁相环的数据驱动型相位检测元件”的美国专利申请，下称《TajalliII》。
技术领域
本发明实施方式总体涉及通信系统电路，尤其涉及利用锁相环从芯片间通信所用高速多线路接口中获得稳定且相位正确的接收器时钟信号。
背景技术
在现代数字系统中，数字信息必须得到高效可靠的处理。在这一背景下，数字信息应理解为含于离散值(即非连续值)内的信息。数字信息不但可由比特和比特集合表示，而且还可由有限集合内的数字表示。
为了提高总带宽，大多数芯片间或装置间通信系统采用多条线路进行通信。这些线路当中的每一条或每一对均可称为信道或链路，而且多个信道组成电子器件之间的通信总线。在物理电路层级上，芯片间通信系统内的总线通常由芯片与主板之间的封装电导体、印刷电路板(PCB)上的封装电导体、或PCB间线缆和连接器内的封装电导体构成。此外，在高频应用中，还可采用微带或带状PCB线路。
常用总线线路信号传输方法包括单端信令法和差分信令法。在需要高速通信的应用中，这些方法还可以在功耗和引脚利用率方面(尤其高速通信中的这些方面)进一步优化。最近提出的向量信令法可在芯片间通信系统的功耗、引脚利用率及噪声稳健性方面实现更加优化的权衡取舍。此类向量信令系统将发送器的数字信息转换为向量码字形式这一不同表示空间，并且根据传输信道的特性和通信系统的设计约束选择不同的向量码字，以在功耗、引脚利用率及速度之间做出更优的权衡取舍。这一过程在本申请中称为“编码”。编码后的码字以一组信号的形式从发射器发送至一个或多个接收器。接收器将所接收的与码字对应的信号反转为最初的数字信息表示空间。这一过程在本申请中称为“解码”。
无论采取何种编码方法，均须对接收装置所接收的信号进行间隔采样(或者以其他方式记录其信号值)，而且无论传输信道的延迟、干扰及噪声条件如何，该采样间隔均须使得采样值能够以最佳方式表示最初的发送值。这一时钟和数据恢复(CDR)操作不但要能够确定合适的采样时间，而且还要能够持续不断地确定合适的采样时间，从而才能对不断变化的信号传播条件进行动态补偿。许多已知的CDR系统通过锁相环(PLL)或延迟锁定环(DLL)合成具有适于实现精确接收数据采样的频率和相位的本地接收时钟。
发明内容
所描述的方法和系统：由含多个逻辑分支的动态加权XOR门接收参考时钟信号以及本地振荡器信号的相位；生成相位误差信号的多个加权段，所述多个加权段包括(i)由所述多个逻辑分支的第一子组在所述参考时钟信号与所述本地振荡器信号的所述相位具有相同逻辑电平时所生成的正加权段以及(ii)由所述多个逻辑分支的第二子组在所述参考时钟信号与所述本地振荡器信号的所述相位具有不同逻辑电平时所生成的负加权段，所述相位误差信号的每一个加权段具有由所述多个逻辑分支中的相应的逻辑分支所施加的相应的权重；通过将所述相位误差信号的各所述加权段加总来生成总控制信号；以及将所述总控制信号作为电流模式输出结果输出，以对生成所述本地振荡器信号的所述相位的本地振荡器进行控制，其中，所述本地振荡器用于响应于所述总控制信号在所述本地振荡器信号中引发相位偏移。
为了对经通信系统发送的数据值进行可靠检测，接收器必须在精心选择的时间点上精确测量接收信号值的幅度。目前，已有各种可促进此类接收测量的已知方法，包括：接收与发送数据流相关的一个或多个专用时钟信号；从发送数据流中提取内嵌时钟信号；以及根据发送数据流的已知属性合成本地接收时钟。
一般而言，此类定时方法的接收器实现方式采用某种形式的时钟数据恢复(CDR)，而且常常利用锁相环(PLL)或延迟锁定环(DLL)合成具有所需频率和相位特性的本地接收时钟。在此类实施方式中，先由相位检测器通过将接收参考信号的相对相位(有时为相对频率)与本地时钟信号相比较来生成误差信号，然后再以该误差信号校正本地时钟源的相位和/或频率，从而最大程度减小所述误差。
在《Tajalli I》和《Tajalli II》所述的实施方式中，通过生成接收参考时钟和/或本地时钟的多个相位或多个时间偏移实例并对其进行相位比较而实现额外时间信息的提取。在此类所谓的“矩阵”相位比较中，将多个相位比较结果的求和结果或加权求和结果作为锁相环的误差反馈信号。本文所述实施方式通过将相位检测功能与可调节或可配置的输出加权法相结合而促进其在矩阵相位比较中的用途。
附图说明
图1所示为用作对参考时钟信号Ck_Ref与包括相位VCO_000、VCO_090、VCO_180、VCO_270在内的本地振荡器信号相位进行比较的相位比较器的多个XOR门。
图2为将本地振荡器信号相位VCO_000和VCO_090与Ck_Ref进行比较的一种相位控制环路实施方式框图。
图3为每一个XOR门分支均可用于生成相位误差信号的加权段的一种动态加权XOR门实施方式示意图。
图4A和图4B为含钟控加权功能的动态加权XOR门实施方式的示意图。
图5为输出加权功能操作时序图。
图6，图7，图8，图9，图10所示为根据一些实施方式的各种参考时钟信号与本地振荡器信号关系下的各种总误差信号。
图11所示为如何利用可调节时间间隔加权法对相位比较器的传输特性进行逼近。
图12A和图12B所示为一进制选择器通过启动一系列元件而提供相位控制信号的两种实施方式。
图13为根据一些实施方式的方法流程图。
图14，图15，图16，图17，图18，图19所示为在一种实施方式中为了获得各种相位角度结果而打开和关闭分支段晶体管的方式。
具体实施方式
如印刷电路板上集成电路间的数据通信等现有技术的短距离有线数据通信的多线路并行通信信道数据速率为每线路10Gbps以上。如此高的数据速率要求对时序，尤其接收器数据采样操作的时序进行精确的控制。《Tajalli I》和《Tajalli II》中描述了一种以含“矩阵”相位比较操作的锁相环(PLL)或延迟锁定环(DLL)系统生成此类定时时钟的方法，其中，先通过在不同相位下对参考时钟相位和本地时钟进行多项比较而获得多个比较结果，然后通过对这些比较结果进行求和而获得能够对时钟误差以更为精确或更富信息的方式进行衡量的求和结果。
本领域中存在多种形式的已知相位检测器。作为非限制性的一例，可利用简单的XOR门或XNOR门，对两个方波信号进行比较。熟悉本领域的技术人员可以看出，此类数字XOR输出为可变占空比波形，而且当该波形经低通滤波处理为模拟误差信号时，所得比例误差信号在所述两个输入信号具有90度相位偏移关系时，其中心位于模拟信号范围内。在图1中，在参考时钟信号Ck_Ref与本地振荡器信号包括VCO_000、VCO_090、VCO_180、VCO_270在内的相位之间进行多项动态加权XOR相位比较，以获得总控制信号。如《Tajalli I》和《Tajalli II》中所述，可以通过对各相位误差分量的权重进行恰当调节而对含所述矩阵相位比较器的锁相环的所得锁定相位进行调节，从而实现在锁相环的闭环响应中引入额外极点或零点等目的。
《Tajalli I》和《Tajalli II》进一步公开如下内容：数字XOR门或XNOR门可分解为晶体管级别的门，其含有表示对分量进行AND运算的子元件，各AND运算随后一并通过OR运算处理而实现所需的复合功能。在本文所述实施方式中，每一个此类子元件可分别加权，以生成可更加精细调节的相位误差信号，该相位误差信号可进一步与接收所述本地振荡器信号其他相位的其他动态加权XOR门的相位误差信号组合，以生成总控制信号，从而实现插值。图3为该技术的一例，其中，XOR门113分解为各个AND运算项310，320，330，340，每一个该AND运算项均含有阻性加权元件，而且所有这些AND运算项一并进行OR运算处理，以产生可用于控制本地振荡器相位调节的总控制信号Iout。与CMOS逻辑的标准做法一致，NMOS子元件320和340实现低电平有效功能部分PMOS子元件310和330实现高电平有效功能部分/>因此，XOR门113的所得相位误差输出信号同时由正加权段(高电平有效)和负加权段(低电平有效)构成，从而同时实现对输出电流的主动拉流和灌流。
在图4A和图4B所示的其他实施方式中，已分解数字门(如图3数字门)的加权操作通过启动输入比特t0，t1，t2，t3的方式实现，而非通过可配置模拟电阻实现。具体而言，此两图所示为图3中四分之一电路部分330的两个版本，其他三个四分之一电路部分310，320，340的实现方式与330类似。每一个输入比特t0，t1，t2，t3的启动均使得多个并行分支段或分支路径当中的一个分支段或分支路径中的启动晶体管导通，所述多个并行分支段或分支路径当中的每个分支段或分支路径均向结果K贡献固定量的电流。因此，处于启动状态的此类分支段的数目控制着总的幅度，即总结果Iout的加权状况。在实际实施方式中，每一路径的电流量可通过恰当选择晶体管的几何尺寸进行控制，这一做法为本领域众所周知的做法。作为非限制性的两例，图4A所示晶体管几何尺寸选为使得每条并行路径均贡献相等的电流量，而图4B所示晶体管几何尺寸选择为使得并行路径的电流贡献逐次加倍。因此，图4A实施方式可与例如通过温度计码对输入比特t0，t1，t2，t3进行一进制(即直接计数)选择法结合使用，而图4B可与输入比特t0，t1，t2，t3的二进制数表示法结合使用。
图5所示为图3中每一个四分之一电路部分均采用图4A电路时获得的结果。其中，通过启动330中t0，t1，t2，t3当中的一者、两者、三者或全部，可以实现加权段510的信号幅度加权。类似地，通过调节340可实现对加权段520的配置，通过调节310可实现对加权段530的配置，通过调节320可实现对加权段540的配置。在每一个分支均具有四个分支段路径的该例中，组合所得输出Iout可共有16种可能的信号幅度。在一些实施方式中，还可通过始终启动相等数目的PMOS和NMOS(即正加权以及负加权)分支段而施加额外约束，以例如实现保持信号对称性的目的。
作为另外一例，通过有意控制处于启动状态的信号路径数目，可在不导入专用相位插值器件的情况下实现调节锁定相位的功能。其中，采用与图1类似的矩阵相位比较器构造。但是，出于简化描述的目的，以下仅考虑双相比较元件113的情形。所得锁相环构造的简化框图示于图2，其中，第一双相比较元件113将本地振荡器信号相位VCO_000与Ck_Ref比较，第二双相比较元件113将所述本地振荡器信号相位VCO_090与Ck_Ref比较。其中，先通过调节207，208每一个相位比较器的分支段权重而生成加权段，随后通过将这些加权段进行组合和低通滤波处理230来生成可用于控制压控振荡器(VCO)240的总控制信号，所述VCO通过生成本地振荡器信号相位VCO_000和VCO_090以在本地振荡器信号的这些相位中引发相位偏移。
相位插值控制信号发生器205接收输入相位值，并生成控制信号207，208，这些控制信号通过选择性地在第一动态加权XOR门和第二动态加权XOR门中启动一定数目的分支段而控制每一个相位比较器实例对所述总控制信号的相对贡献量，所述总控制信号可在低通滤波处理230后提供给VCO240。
在一些实施方式中，可利用多个分解后的XOR门对所述VCO进行插值处理。在一些实施方式中，可在插值处理中使用所述本地振荡器信号的两个以上相位，以提高所述本地振荡器信号的环路带宽和抖动跟踪功能。图14至图18所示为利用四个VCO相位生成插值相位的方法。图14所示为一种实施方式的分支段晶体管布置方式，该布置方式通过在所述本地振荡器信号的四个相位之间进行插值而获得可调节相位结果。图中，已启动的PMOS和NMOS分支段晶体管示为阴影，而未启动晶体管示为空白。因此，可以看出，由于0度、45度、90度、135度输入相位的所有关联分支晶体管已启动，而180度输入相位的所有关联分支晶体管未启动，因此极坐标图中所示67.5度结果为0度、45度、90度、135度输入相位的均等求和结果。产生这一已启动分支段晶体管布置方式的一组总控制信号的关联内部相位插值器代码为“0”，因此这一具体输出相位的关联内部相位插值器代码为“0”。需要注意的是，相位为67.5度的插值相位信号也可通过仅对与(本例中)所需的该67.5度相位紧邻的45度和90度相位进行均等加权的方式获得。然而，如果仅对所述相邻相位进行组合，则无法纳入0度和135度相位中存在的抖动信息(因而无法对该抖动进行校正)。通过使所生成的VCO控制信号不但含有所需插值相位紧邻相位的相位比较数据还含有其非紧邻相位的相位比较数据，可以实现带宽极度增大且响应性和准确度更高的相位控制。
在上述实施方式中，当将相位插值器代码改为“1”时，将产生图15所示的结果。其中，除了与输入相位0关联的一个NMOS分支段晶体管被关闭外，所有其他分支晶体管均仍采取与图14所示相同的构造。如此，对于该输入相位，负加权段(即当参考时钟信号与本地振荡器信号的相位具有不同逻辑电平时，对求和结果有贡献作用的加权段)的权重略微低于正加权段(即当参考时钟信号与本地振荡器信号的相位具有相同逻辑电平时，对求和结果有贡献作用的加权段)的权重，而该正加权段的权重与图14所示相同。由于相位0对0度、45度、90度、135度相位误差信号加权段的求和结果的贡献度降低，因此在相位0对求和结果贡献度降低的作用下，输出相位约为69度。
同样，在上例中，图16所示为该实施方式中当相位插值器代码为“2”时的结果。其中，与输入相位0关联的一个NMOS分支段晶体管和一个PMOS分支段晶体管关闭，从而使得相位0对所述加权求和结果的贡献度进一步降低，并使得输出相位约为72度。
图17所示为该实施方式中与内部相位插值器代码为“5”时对应的相位调节。其中，与输入相位0关联的两个PMOS分支段晶体管和三个NMOS分支段晶体管关闭，从而进一步降低该相位对加权求和结果的贡献度。图18所示为该实施方式中内部相位插值器代码为“7”时的构造，其中，与输入相位0关联的三个PMOS分支段晶体管和四个NMOS分支段晶体管关闭，从而进一步降低该相位对加权求和结果的贡献度。如图19所示，当与相位0关联的所有分支段均关闭时，可以开始打开相位180的分支段，以生成90度以上的插值信号。
图6至图10为根据一些实施方式的总控制信号形成时序图。虽然下文参考图3进行描述，但是需要注意的是，类似示例和概念还可扩展至其他类似系统。图6所示为本地振荡器信号相位VCO_000和VCO_090间插值时序图。如图所示，图6中相位误差信号error_000和error_090加权段的状态为将如图3所示接收参考时钟信号和本地振荡器信号相位VCO_000的电路分支330和340关闭且将如图3所示接收参考时钟信号和本地振荡器信号相位VCO_090的电路分支330和340打开后的即时状态。如图所示，加权段error_000和error_090阴影部分加总后的结果最负，因此使得本地振荡器发生旋转，从而使得总控制信号的平均值为零，即达到锁定状态。
图7所示为达到锁定状态时本地振荡器信号相位VCO_000和VCO_090相对于参考时钟信号的关系。如图所示，由于相位VCO_000和VCO_090已相对于参考时钟信号发生相移，因此图中的45度相位锁定至相位检测器的90度锁定点。可以理解的是，所述相移的原因在于，接收相位VCO_000的XOR检测器打开一半，而且接收相位VCO_090的XOR检测器也打开一半，从而使得此两相位对总控制信号的贡献度相等。还需进一步注意的是，如此，相位误差信号error_000和error_090加权段的加总结果平均为0，从而使得VCO处于相位VCO_000和VCO_090已相对于上述90度锁定点经历-45度相移的锁定状态。
图8所示情形与上述类似，其区别在于，在图8中，相位VCO_000的分支330和340关闭，而相位VCO_270的分支330和340打开。如此，相位VCO_000和VCO_270相对于前一锁定点经历+45度的相移，从而使得315度相位锁定至相位检测器的90度锁定点。
虽然出于描述简单性的目的，以上仅讨论了将各分支完全打开/关闭的示例，但是如图3所示，同一分支也可包括多个分支段，这些分支段能够在本地振荡器信号的相邻相位上各自打开/关闭，从而使得相应的AND运算可部分贡献至一个以上的相位误差信号。例如，如图3所示，t0和t1可在分别接收相位VCO_000/VCO_090的动态加权XOR门内打开/关闭，因此仅构成分支330一半。此类情形示于图9。在图9中，接收相位VCO_000的动态加权XOR中仅t0和t1关闭，在接收相位VCO_090的动态加权XOR中仅t0和t1打开。如图所示，这一构造在本地振荡器信号的相位VCO_000中成比例地引入相对于参考时钟信号90度锁定点约-11.25度较小偏移。相位误差信号error_000和error_090的加权段示于图9。如图所示，由于仅两个分支段贡献于相位误差信号error_000分支330的关联加权段，而所有的四个分支段均贡献于相位误差信号error_000的其余加权段，因此所述加权段的幅度为其余分支的一半。
在又一其他实施方式中，仅将动态加权XOR门分支的一个或多个分支段关闭即可引发相移，甚至无需将接收本地振荡器信号相邻相位的动态加权XOR门接收的相应分支段打开。此类实施方式示于图10。在图1中，接收本地振荡器信号相位VCO_000的动态加权XOR门的分支段t0和t1关闭，而接收相位VCO_090的动态加权XOR门无任何分支段打开。在此类实施方式中，在总控制信号的正向和负向部分对本地振荡器信号相位宽度的调节作用下，例如通过旋转本地振荡器信号相位而改变XOR门输出信号的占空比的作用下，本地振荡器信号的相位内引入相位偏移，以对突然出现的负向总控制信号进行补偿，直至总的正向面积与总的负向面积相等，从而实现锁定状态。可以注意到的是，图10所示实施方式引发的相移大于图9所示实施方式的相移。在图9中，总控制信号正向部分中的一部分通过相位误差信号error_090的正加权段加回其中，而在图10中，由于不存在error_090的贡献作用，因此需要在本地振荡器信号相位中引发更大的偏移才能实现补偿。
图11所示为上述相位插值操作所期望的线性传递函数与在每一调节步长内通过启动或关闭固定数目的加权段而将两个信号简单混合所得的固有非线性结果之间的比较。可以看出，使用固定步长所产生的非线性曲线始终处于所期望的线性响应的上方，因此要想实现线性化，必须减少每一步长内启动的加权段数。在一些实施方式中，在有相应需求的情况下，可以通过预先确定一系列步长的方式实现线性度更高的相位插值关系。
图12A所示为此方面的一种实施方式，其中，通过在两个相位误差信号输出中的第一输出中选择性地启动32可能存在的门控信号来实现对线性插值操作的紧密逼近。每一个元件1200均表示第一动态加权XOR门(如图3所示)中的电路子元件(如图4A所示)内的一个加权段。一进制解码器1210根据输入步长编号，选择性地启动相应数目的输出。在此类实施方式中，每一个被选输出均可控制动态加权XOR门的多个分支当中一个分支的相应分支段。由此可见，该线性化功能通过选择性地将某些元件1200与总结果Q断连的方式(即不将该加权段与相应分支段连接)实现。断连分支段例如包括由Unary16、Unary20、Unary22～Unary23，Unary25～Unary27、Unary29～Unary30启动的分支段。
在一些实施方式中，用于控制第一相位误差结果的启动分支段数目和用于控制第二相位误差结果的启动分支段数目由图2所示控制信号发生器205协调。在至少一种实施方式中，所述第二相位误差信号的分支段数目的加权权重为所述第一相位误差信号的分支段数目的加权权重的倒数。图12B所示为对接收相邻相位的第二动态加权XOR门进行控制的互补实施方式。其中，输出I和Q可分别对应于相位控制信号207和208，反之亦然。
图13为根据一些实施方式的方法流程图。如图所示，方法1300包括：由含多个逻辑分支的动态加权XOR门接收1302参考时钟信号和本地振荡器信号相位；生成1304相位误差信号的多个加权段，该多个加权段包括(i)由所述多个逻辑分支的第一子组在所述参考时钟信号与所述本地振荡器信号相位具有相同逻辑电平时生成的正加权段以及(ii)由所述多个逻辑分支的第二子组在所述参考时钟信号与所述本地振荡器信号相位具有不同逻辑电平时生成的负加权段，所述相位误差信号的每一个加权段分别具有所述多个逻辑分支当中相应逻辑分支施加的权重；通过将各相位误差信号加权段加总而生成1306总控制信号；以及将所述总控制信号作为电流模式输出结果输出1308，以控制生成所述本地振荡器信号相位的本地振荡器，所述本地振荡器用于响应所述总控制信号而在所述本地振荡器信号中引发相位偏移。
在一些实施方式中，每一个逻辑分支包括多个并联的分支段。在此类实施方式中，所述方法还包括生成含多个比特的相位控制信号。在一些实施方式中，每一个分支段均根据所述相位控制信号的多个比特当中的相应的比特启动。在一些实施方式中，每一个分支段均根据将所述相应比特接收为输入的相应的启动晶体管启动。在一些实施方式中，给定加权段的相应权重由所述逻辑分支内启动的分支段数目决定。
在一些实施方式中，给定加权段的相应的权重是部分由所述逻辑分支内的晶体管大小决定的。在替代实施方式中，给定加权段的相应的权重是部分由与所述逻辑分支相连的可调阻抗决定的。
在一些实施方式中，所述总控制信号还根据以所述参考时钟信号和与所述本地振荡器信号上述相位相邻的本地振荡器信号第二相位生成的第二相位误差信号加权段生成。在一些此类实施方式中，所述第二相位误差信号加权段的加权权重为所述第一相位误差信号加权段加权权重的倒数。在一些实施方式中，所引发的相位偏移对应于所述总控制信号的非零平均值。
在一些实施方式中，一种方法包括：接收参考时钟信号以及本地振荡器信号的第一和第二相位；通过将所述参考时钟信号分别与所述本地振荡器信号的第一和第二相位相比较而生成第一和第二相位误差信号的相应的各组加权段，每组相应加权段均由相应动态加权XOR门的多个逻辑分支生成，其中，所述第一和第二相位误差信号的加权段分别含有第一和第二组权重，所述第一和第二组权重根据预设相位偏移值选择；通过对所述第一和第二相位误差信号的各加权段进行求和而生成总控制信号；以及将所述总控制信号输出为电流模式输出信号，以控制生成所述本地振荡器信号的第一和第二相邻相位的本地振荡器，所述本地振荡器用于响应所述总控制信号而在所述本地振荡器信号的第一和第二相位中引发相位偏移，该偏移量与所述预设相位偏移值相关联。
在一些实施方式中，所述第一和第二成段相位误差信号中的每一者的加权段均包括(i)由所述多个逻辑分支的第一子组在所述参考时钟信号与所述本地振荡器信号相位具有相同逻辑电平时生成的正加权段以及(ii)由所述多个逻辑分支的第二子组在所述参考时钟信号与所述本地振荡器信号相位具有不同逻辑电平时生成的负加权段。
在一些实施方式中，所述第一和第二组权重对应于相应动态加权XOR门中已启动的逻辑分支段总数。
在一些实施方式中，所述第一和第二组权重根据表示所述本地振荡器信号第一和第二相位的预设相位偏移值的相位控制信号选择。在一些此类实施方式中，所述相位控制信号由相位控制信号发生器生成。在一些实施方式中，所述相位控制信号发生器包括查找表，并用于从该查找表中选择相位控制信号。在一些此类实施方式中，所述查找表可包括实施线性插值功能的相位控制信号步长。在一些实施方式中，所述相位控制信号可以为温度计码。在此类实施方式中，接收所述本地振荡器信号第一相位的动态加权XOR门可接收温度计码，该温度计码为接收所述本地振荡器信号第二相位的动态加权XOR门所接收的温度计码的倒数。
在一些实施方式中，所述本地振荡器信号的第一和第二相位具有45度的相位差。在一些实施方式中，所述本地振荡器信号的第一和第二相位可具有90度或180度的相位差。在一些实施方式中，所述本地振荡器信号的第一和第二相位可以为相邻相位，在该情形中，此两相位源自本地振荡器的相邻环形振荡器元件。

Claims (20)

1.一种用于相位检测和相位插值的方法，其特征在于，包括：
由包括多个逻辑分支的动态加权XOR门接收参考时钟信号以及本地振荡器信号的相位，其中，每一个逻辑分支响应于相应的所述参考时钟信号与所述本地振荡器信号的所述相位的输入逻辑组合而启动；
生成相位误差信号的多个加权段，所述多个加权段包括（i）由所述多个逻辑分支的第一子组在所述参考时钟信号与所述本地振荡器信号的所述相位具有相同逻辑电平时所生成的正加权段以及（ii）由所述多个逻辑分支的第二子组在所述参考时钟信号与所述本地振荡器信号的所述相位具有不同逻辑电平时所生成的负加权段，所述相位误差信号的每一个加权段具有由所述多个逻辑分支中的相应的逻辑分支所选择性施加的相应的权重，其中，所述多个加权段中的至少两个加权段具有不同的权重；
通过将所述相位误差信号的各所述加权段加总来生成总控制信号；以及
将所述总控制信号作为电流模式输出结果输出，以对生成所述本地振荡器信号的所述相位的本地振荡器进行控制，其中，所述本地振荡器用于响应于所述总控制信号在所述本地振荡器信号中引发相位偏移。
2.如权利要求1所述的方法，其特征在于，每一个逻辑分支包括并联连接的多个分支段。
3.如权利要求2所述的方法，其特征在于，还包括：生成包括多个比特的相位控制信号，其中，每一个分支段均根据所述相位控制信号的所述多个比特中的相应的比特启动。
4.如权利要求3所述的方法，其特征在于，每一个分支段均根据将相应的所述比特作为输入接收的相应的启动晶体管启动。
5.如权利要求3所述的方法，其特征在于，生成所述相位控制信号包括从查找表中选择与所述相位偏移相应的值。
6.如权利要求2所述的方法，其特征在于，给定加权段的相应的权重由所述逻辑分支中所启动的分支段的数目决定。
7.如权利要求1所述的方法，其特征在于，给定加权段的相应的权重是部分由所述逻辑分支中的晶体管尺寸决定的。
8.如权利要求1所述的方法，其特征在于，给定加权段的相应的权重是部分由与所述逻辑分支相连的可调阻抗决定的。
9.如权利要求1所述的方法，其特征在于，所述总控制信号还根据至少第二相位误差信号的加权段生成，所述第二相位误差信号是利用所述参考时钟信号以及所述本地振荡器信号的至少第二相位生成的，其中，所述第二相位与所述本地振荡器信号的所述相位相邻。
10.如权利要求9所述的方法，其特征在于，利用源自所述本地振荡器信号的至少三个相位的相位误差信号的加权段生成所述总控制信号。
11.一种用于相位检测和相位插值的装置，其特征在于，包括：
动态加权XOR门的多个逻辑分支，所述多个逻辑分支用于接收参考时钟信号以及本地振荡器信号的相位，并响应地生成相位误差信号的多个加权段，所述相位误差信号的每一个加权段均通过响应于相应的所述参考时钟信号与所述本地振荡器信号的所述相位的输入逻辑组合而启动的相应的逻辑分支生成以及具有由所述多个逻辑分支中的相应的逻辑分支所选择性施加的相应的权重，所述多个加权段中的至少两个加权段具有不同的权重，其中，所述多个逻辑分支包括：
所述多个逻辑分支的第一子组，用于在所述参考时钟信号与所述本地振荡器信号的所述相位具有相同逻辑电平时生成正加权段；
所述多个逻辑分支的第二子组，用于在所述参考时钟信号与所述本地振荡器信号的所述相位具有不同逻辑电平时生成负加权段；以及
与所述多个逻辑分支连接的公共节点，用于通过将所述相位误差信号的各加权段加总来生成总控制信号，并响应地将所述总控制信号作为电流模式输出结果输出以对生成所述本地振荡器信号的所述相位的本地振荡器进行控制，其中，所述本地振荡器用于响应于所述总控制信号在所述本地振荡器信号中引发相位偏移。
12.如权利要求11所述的装置，其特征在于，每一个逻辑分支包括并联连接的多个分支段。
13.如权利要求12所述的装置，其特征在于，还包括用于生成包括多个比特的相位控制信号的相位插值器控制信号发生器，其中，每一个分支段均根据所述相位控制信号的所述多个比特中的相应的比特启动。
14.如权利要求13所述的装置，其特征在于，每一个分支段均包括用于将相应的所述比特作为输入接收的相应的启动晶体管。
15.如权利要求13所述的装置，其特征在于，所述相位插值器控制信号发生器用于通过从查找表中选择与所述相位偏移相应的值来生成所述相位控制信号。
16.如权利要求12所述的装置，其特征在于，给定加权段的相应的权重由所述逻辑分支中所启动的分支段的数目决定。
17.如权利要求11所述的装置，其特征在于，给定加权段的相应的权重是部分由所述逻辑分支中的晶体管尺寸决定的。
18.如权利要求11所述的装置，其特征在于中，给定加权段的相应的权重是部分由与所述逻辑分支相连的可调阻抗决定的。
19.如权利要求11所述的装置，其特征在于，所述总控制信号还根据至少第二相位误差信号的加权段生成，所述第二相位误差信号是利用所述参考时钟信号以及所述本地振荡器信号的至少第二相位生成的，其中，所述第二相位与所述本地振荡器信号的所述相位相邻。
20.如权利要求19所述的装置，其特征在于，所述总控制信号是利用源自所述本地振荡器信号的至少三个相位的相位误差信号的加权段生成的。
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