JP3917624B2 - 低密度パリティチェック(ldpc)デコーダにおける経路指定方法およびシステム - Google Patents
低密度パリティチェック(ldpc)デコーダにおける経路指定方法およびシステム Download PDFInfo
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Description
低密度パリティチェック(LDPC)コードを効率的に復号するためのシステム、方法およびソフトウェアを説明する。以下の説明において、多くの特定の詳細は本発明を完全に理解するために説明の目的で記載されている。しかしながら、本発明はこれらの特定の詳細なしで、あるいは等価の構成により実現可能であることは当業者に明らかである。他の例において、よく知られている構造および装置は、本発明をいたずらに不明瞭にすることを避けるためにブロック図の形態で示されている。
H(n-k)xn=[A(n-k)xkB(n-k)x(n-k)]
の形式のものであり、ここで、Bは下方の三角である。
ej=aj−uj j=0,1,2
次に、8−PSKシンボル確率:pi (i=0,1,…,7)が決定される。
Claims (20)
- 低密度パリティチェック(LDPC)コード化された信号を生成するために使用された構成されたパリティチェックマトリックスに関連付けられたエッジ値を検索し、エッジ値はビットノードとチェックノードとの関係を特定し、エッジ値のセットの同時検索を可能にする予め定められた方式にしたがってメモリ内に記憶され、前記予め定められた方式はエッジ値のセットに対する隣接した物理的メモリ位置を特定し、
検索されたエッジ値に基づいてLDPCコード化された信号に対応した復号された信号を出力するステップを含んでいるLDPCコード化された信号の復号方法。 - メモリ(1501,1503)は、ビットノードの度数にしたがって区分されている請求項1記載の方法。
- n度のビットノードを有するエッジ値はメモリ(1501,1503)の第1の部分に記憶され、nより大きい度数のビットノードを有するエッジ値はメモリ(1501,1503)の第2の部分に記憶される請求項2記載の方法。
- メモリ(1501,1503)のアドレスは、読出し専用メモリ(ROM)中に記憶されている請求項1記載の方法。
- エッジ値のセットは、メモリ(1501,1503)に接続されたプロセッサの単一のクロックサイクルで検索され、MのビットノードまたはMのチェックノードのグループに隣接しており、ここでMは並列処理エンジンの数である請求項1記載の方法。
- エッジの隣接した配置は、パリティチェックマトリックスのある部分を三角であるように制限を与える請求項1記載の方法。
- LDPCコード化された信号は、8−PSK(位相シフトキーイング)、16−QAM(直交振幅変調)、16−APSK(振幅位相シフトキーイング)、32−APSKおよびQPSK(直交位相シフトキーイング)の1つを含む信号コンステレーションにしたがって変調される請求項1記載の方法。
- 検索するステップにおけるエッジ値のセットは、固定されたサイズのものである請求項1記載の方法。
- 低密度パリティチェック(LDPC)コード化された信号を復号する命令が実行されたときに、それが1以上のプロセッサに請求項1記載の方法を行わせるように構成されている命令を有しているコンピュータ読出し可能な媒体。
- 低密度パリティチェック(LDPC)コード化された信号を生成するために使用された構成されたパリティチェックマトリックスに関連付けられたエッジ値を検索する手段と、
ビットノードとチェックノードとの関係を特定するエッジ値のセットの同時検索を可能にする予め定められた方式にしたがってエッジ値を記憶するメモリ(1501,1503)と、
検索されたエッジ値に基づいてLDPCコード化された信号に対応した復号された信号を出力する手段とを備え、
前記予め定められた方式はエッジ値のセットに対する隣接した物理的メモリ位置を特定する、LDPCコード化された信号を復号するデコーダ。 - メモリ(1501,1503)は、ビットノードの度数にしたがって区分されている請求項10記載のデコーダ。
- n度のビットノードに接続されたエッジ値はメモリ(1501,1503)の第1の部分に記憶され、nより大きい度数のビットノードに接続されたエッジ値はメモリ(1501,1503)の第2の部分に記憶される請求項10記載のデコーダ。
- 構成されたパリティチェックマトリックスは、パリティチェックマトリックスのサブマトリックスが下方三角領域に制限されたパリティチェック値を含んでいる請求項10記載のデコーダ。
- LDPCコード化された信号は、8−PSK(位相シフトキーイング)、16−QAM(直交振幅変調)、16−APSK(振幅位相シフトキーイング)、32−APSKおよびQPSK(直交位相シフトキーイング)の1つを含む信号コンステレーションにしたがって変調される請求項10記載のデコーダ。
- さらに、メモリ(1501,1503)のアドレスを記憶する読出し専用メモリを備えている請求項10記載のデコーダ。
- さらに、メモリ(1501,1503)に接続されたプロセッサを備えており、エッジ値のセットはこのプロセッサの単一のクロックサイクルで検索され、MのビットノードまたはMのチェックノードのグループに隣接しており、ここでMは並列処理エンジンの数である請求項10記載のデコーダ。
- n度のビットノードに接続されており、LDPCコード化された信号を生成するために使用された構成されたパリティチェックマトリックスに関連付けられたエッジ値の第1のグループを記憶する第1の部分と、
nより大きい度数のビットノードに接続されており、(LDPC)コード化された信号を生成するために使用された構成されたパリティチェックマトリックスに関連付けられたエッジ値の第2のグループを記憶する第2の部分とを備えており、
復号された信号を出力するために第1のグループまたは第2のグループからのエッジ値のセットが検索されるLDPCコード化された信号を復号するLDPCデコーダによりアクセス可能なメモリ。 - 前記エッジ値のセットを同時検索するため、エッジ値は予め定められた方式にしたがって隣接した物理的メモリ位置に記憶される請求項17記載のメモリ。
- エッジの隣接した配置は、パリティチェックマトリックスのある部分を三角であるように制限を与える請求項18記載のメモリ。
- LDPCコード化された信号は、8−PSK(位相シフトキーイング)、16−QAM(直交振幅変調)、16−APSK(振幅位相シフトキーイング)、32−APSKおよびQPSK(直交位相シフトキーイング)の1つを含む信号コンステレーションにしたがって変調される請求項17記載のメモリ。
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