US6938196B2  Node processors for use in parity check decoders  Google Patents
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 US6938196B2 US6938196B2 US10/117,264 US11726402A US6938196B2 US 6938196 B2 US6938196 B2 US 6938196B2 US 11726402 A US11726402 A US 11726402A US 6938196 B2 US6938196 B2 US 6938196B2
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Abstract
Description
This application claims the benefit of U.S. Provisional Application Ser. No. 60/328,469 filed Oct. 10, 2001 and the benefit of U.S. Provisional Application Ser. No. 60/298,480 filed Jun. 15, 2001 and is a continuationinpart of U.S. patent application Ser. No. 09/975,331 filed Oct. 10, 2001 now, U.S. Pat. No. 6,633,856, each of which is hereby expressly incorporated by reference.
The present invention is directed to methods and apparatus for detecting and/or correcting errors in binary data, e.g., through the use of parity check codes such as low density parity check (LDPC) codes.
Error correcting codes are ubiquitous in communications and data storage systems. Recently a considerable interest has grown in a class of codes known as lowdensity paritycheck (LDPC) codes.
LDPC codes are well represented by bipartite graphs, often called Tanner graphs, in which one set of nodes, the variable nodes, corresponds to bits of the codeword and the other set of nodes, the constraint nodes, sometimes called check nodes, correspond to the set of paritycheck constraints which define the code. Edges in the graph connect variable nodes to constraint nodes. A variable node and a constraint node are said to be neighbors if they are connected by an edge in the graph. For simplicity, we generally assume that a pair of nodes is connected by at most one edge. To each variable node is associated one bit of the codeword. In some cases some of these bits might be punctured, i.e., removed from the codeword. For simplicity we shall generally assume that no puncturing is used.
A bit sequence associated onetoone with the variable node sequence is a codeword of the code if and only if, for each constraint node, the bits neighboring the constraint (via their association with variable nodes) sum to zero modulo two, i.e., they comprise an even number of ones.
The decoders and decoding algorithms used to decode LDPC codewords operate by exchanging messages within the graph along the edges and updating these messages by performing computations at the nodes based on the incoming messages. Such algorithms will be generally referred to as message passing algorithms. Each variable node in the graph is initially provided with a soft bit, termed a received value, that indicates an estimate of the associated bit's value as determined by observations from, e.g., the communications channel. Ideally, the estimates for separate bits are statistically independent. This ideal can be, and often is, violated in practice. A collection of received values constitutes a received word. For purposes of this application we may identify the signal observed by, e.g., the receiver in a communications system, with the received word.
The number of edges attached to a node, i.e., a variable node or constraint node, is referred to as the degree of the node. A regular graph or code is one for which all variable nodes have the same degree, j say, and all constraint nodes have the same degree, k say. In this case we say that the code is a (j,k) regular code. These codes were originally invented by Gallager (1961). In contrast to a “regular” code, an irregular code has constraint nodes and/or variable nodes of differing degrees. For example, some variable nodes may be of degree 4, others of degree 3 and still others of degree 2.
While irregular codes can be more complicated to represent and/or implement, it has been shown that irregular LDPC codes can provide superior error correction/detection performance when compared to regular LDPC codes.
In order to more precisely describe the decoding process we introduce the notion of a socket in describing LDPC graphs. A socket can be interpreted as an association of an edge in the graph to a node in the graph. Each node has one socket for each edge attached to it and the edges are “plugged into” the sockets. Thus, a node of degree d has d sockets attached to it. If the graph has L edges then there are L sockets on the variable node side of the graph, called the variable sockets, and L sockets on the constraint node side of the graph, called the constraint sockets. For identification and ordering purposes, the variable sockets may be enumerated 1, . . . , L so that variable sockets attached to one variable node appear contiguously. In such a case, if the first three variable nodes have degrees d_{1}, d_{2}, and d_{3 }respectively, then variable sockets 1, . . . , d_{1 }are attached to the first variable node, variable sockets d_{1}+1, . . . , d_{1}+d_{2 }are attached to the second variable node, and variable sockets d_{1}+d_{2}+1, . . . , d_{1}+d_{2}+d_{3 }are attached to the third variable node. Constraint node sockets may be enumerated similarly 1, . . . , L with constraint sockets attached to one constraint node appearing contiguously. An edge can be viewed as a pairing of sockets, one of each pair coming from each side of the graph. Thus, the edges of the graph represent an interleaver or permutation on the sockets from one side of the graph, e.g., the variable node side, to the other, e.g., the constraint node side. The permutations associated with these systems are often complex.
An exemplary bipartite graph 100 determining a (3,6) regular LDPC code of length ten and rate onehalf is shown in FIG. 1. Length ten indicates that there are ten variable nodes V_{1}V_{10}, each identified with one bit of the codeword X_{1}X_{10 }(and no puncturing in this case), generally identified by reference numeral 102. Rate one half indicates that there are half as many check nodes as variable nodes, i.e., there are five check nodes C_{1}C_{5 }identified by reference numeral 106. Rate one half further indicates that the five constraints are linearly independent, as discussed below. Each of the lines 104 represents an edge, e.g., a communication path or connection, between the check nodes and variable nodes to which the line is connected. Each edge identifies two sockets, one variable socket and one constraint socket. Edges can be enumerated according to their variable sockets or their constraint sockets. The variable sockets enumeration corresponds to the edge ordering (top to bottom) as it appears on the variable node side at the point where they are connected to the variable nodes. The constraint sockets enumeration corresponds to the edge ordering (top to bottom) as it appears on the constraint node side at the point they are connected to the constraint nodes. During decoding, messages are passed in both directions along the edges. Thus, as part of the decoding process messages are passed along an edge from a constraint node to a variable node and vice versa.
An alternative to using a graph to represent codes is to use a matrix representation such as that shown in FIG. 2. In the matrix representation of a code, the matrix H 202, commonly referred to as the parity check matrix, includes the relevant edge connection, variable node and constraint node information. For simplicity we assume that at most one edge connects any pair of nodes. In the matrix H, each column corresponds to one of the variable nodes while each row corresponds to one of the constraint nodes. Since there are 10 variable nodes and 5 constraint nodes in the exemplary code, the matrix H includes 10 columns and 5 rows. The entry of the matrix corresponding to a particular variable node and a particular constraint node is set to 1 if an edge is present in the graph, i.e., if the two nodes are neighbors, otherwise it is set to 0. For example, since variable node V_{1 }is connected to constraint node C_{1 }by an edge, a one is located in the uppermost lefthand corner of the matrix 202. However, variable node V_{5 }is not connected to constraint node C_{1 }so a 0 is positioned in the fifth position of the first row of matrix 202 indicating that the corresponding variable and constraint nodes are not connected. We say that the constraints are linearly independent if the rows of H are linearly independent vectors over GF[2]. Enumerating edges by sockets, variable or constraint, corresponds to enumerating the 1's in H. Variable socket enumeration corresponds to enumerating top to bottom within columns and proceeding left to right from column to column, as shown in matrix 208. Constraint socket enumeration corresponds to enumerating left to right across rows and proceeding top to bottom from row to row, as shown in matrix 210.
In the case of a matrix representation, the codeword X which is to be transmitted can be represented as a vector 206 which includes the bits X_{1}X_{n }of the codeword to be processed. A bit sequence X_{1}X_{n }is a codeword if and only if the product of the matrix 206 and 202 is equal to zero, that is: Hx=0.
In the context of discussing codewords associated to LDPC graphs, it should be appreciated that in some cases the codeword may be punctured. Puncturing is the act of removing bits from a codeword to yield, in effect, a shorter codeword. In the case of LDPC graphs this means that some of the variable nodes in the graph correspond to bits that are not actually transmitted. These variable nodes and the bits associated with them are often referred to as state variables. When puncturing is used, the decoder can be used to reconstruct the portion of the codeword which is not physically communicated over a communications channel. Where a punctured codeword is transmitted the receiving device may initially populate the missing received word values (bits) with ones or zeros assigned, e.g., in an arbitrary fashion, together with an indication (soft bit) that these values are completely unreliable, i.e., that these values are erased. For simplicity, we shall assume that, when used, these receiverpopulated values are part of the received word which is to be processed.
Consider for example the system 350 shown in FIG. 3. The system 350 includes an encoder 352, a decoder 357 and a communication channel 356. The encoder 350 includes an encoding circuit 353 that processes the input data A to produce a codeword X. The codeword X includes, for the purposes of error detection and/or correction, some redundancy. The codeword X may be transmitted over the communications channel. Alternatively, the codeword X can be divided via a data selection device 354 into first and second portions X′, X″ respectively by some data selection technique. One of the codeword portions, e.g., the first portion X′, may then be transmitted over the communications channel to a receiver including decoder 357 while the second portion X″ is punctured. As a result of distortions produced by the communications channel 356, portions of the transmitted codeword may be lost or corrupted. From the decoder's perspective, punctured bits may be interpreted as lost.
At the receiver soft bits are inserted into the received word to take the place of lost or punctured bits. The inserted soft bits indicate erasure of X″ bits and/or bits lost in transmission.
The decoder 357 will attempt to reconstruct the full codeword X from the received word Y and any inserted soft bits, and then perform a data decoding operation to produce A from the reconstructed codeword X.
The decoder 357 includes a channel decoder 358, e.g., an LDPC decoder, for reconstructing the complete codeword X from the received word Y and any inserted soft bits. In addition it includes a data decoder 359 for removing the redundant information included in the codeword to produce the original input data A from the reconstructed codeword X.
It will be appreciated that received words generated in conjunction with LDPC coding, can be processed by performing LDPC decoding operations thereon, e.g., error correction and detection operations, to generate a reconstructed version of the original codeword. The reconstructed codeword can then be subject to data decoding to recover the original data that was coded. The data decoding process may be, e.g., simply selecting a specific subset of the bits from the reconstructed codeword.
As mentioned above, LDPC decoding operations generally comprise message passing algorithms. There are many potentially useful message passing algorithms and the use of such algorithms is not limited to LDPC decoding. As will be discussed in detail below, the current invention is directed to methods and apparatus which provide a simple, e.g., low hardware complexity, implementation of an decoder algorithm that gives very good and often near optimal performance in many circumstances. The proposed algorithm can be viewed as an approximation of the wellknown belief propagation algorithm.
To facilitate understanding of the invention discussed in the sections which follow, we will now give a brief mathematical description of belief propagation.
Belief propagation for (binary) LDPC codes can be expressed as follows. Messages transmitted along the edges of the graph are interpreted as loglikelihoods
for the bit associated to the variable node. Here, (P_{0}, p_{1}) represents a conditional probability distribution on the associated bit where p_{x }denotes the probability that the bit takes the value x. The soft bits provided to the decoder by the receiver are also given in the form of a loglikelihood. Thus, the received values, i.e., the elements of the received word, are loglikelihoods of the associated bits conditioned on the observation of the bits provided by the communication channel. In general, a message m represents the loglikelihood m and a received value y represents the loglikelihood y. For punctured bits the loglikelihood received value y is set to 0, indicating p_{0}=p_{1}=½.
Let us consider the messagepassing rules of belief propagation. Messages are denoted by m^{C2V }for messages from check nodes to variable nodes and by m^{V2C }for messages from variable nodes to check nodes. Consider a variable node with d edges. For each edge j=1, . . . , d let m^{C2V}(i) denote the incoming message on edge i. At the initialization of the decoding process we set m^{C2V}=0 for every edge. In general, outgoing messages from variable nodes are given by
The outgoing decoded soft value from a node (not an edge message) corresponding to this operation is given by
The outgoing hard decision associated to this output is obtained from the sign of x_{out}.
At the check nodes it is often more convenient to represent the messages using their ‘sign’ and magnitudes. Thus, for a message m let m_{p}εGF[2] denote the ‘parity’of the message, i.e., m_{p}=0 if m≧0 and m_{p}=1 if m<0. Additionally let m_{r}ε[0,∞] denote the magnitude of m. Thus, we have m=−1^{m} _{ p }m_{r}. At the check node the updates for m_{p }and m_{r }are separate. We have, for a check node of degree d,
where all addition is over GF[2], and
where we define F(x):=ln coth (x/2). In both of the above equations the superscript V2C denotes the incoming messages at the constraint node. We note that F is its own inverse, i.e., F^{−1}(x)=F(x)
The present invention is directed to methods and apparatus for performing decoding operations that are used in conjunction with message passing decoding techniques. The techniques of the present invention are particularly well suited for use with LDPC codes.
In the background material of this application we provided a mathematical description of the belief propagation algorithm which can be used in conjunction with LDPC decoding. It is evident, according to our description, that the main difficulty encountered in implementing the algorithm concerns the function F and its inverse. Other required operations tend to be relatively simple to implement.
To facilitate hardware implementation of an LDPC decoder, in some embodiments of the invention, loglikelihood values are quantized to integer multiples of ½ ln 2. Loglikelihood values may be, for example, log likelihood ratios or approximations thereof.
Log likelihood ratios may be explained as follows. Let x be a bit. Assume that x, possibly together with other bits, are transmitted as a signal and that the receiver observes z as a consequence. The log likelihood ratio for x is defined as
where p(zx=i) denotes the conditional probability of observing z given the condition x=i. There are many possible methods and forms for computing y depending on the signaling scheme, the channel model, etc. Assuming that the two possibilities for x are a priori equally likely, the likelihood ratio
is equal to the ratio of the posterior probabilities of x given z, i.e.,
Thus, we often denote the log likelihood ratio as simply
where p_{i }denotes a conditional probability that x=i. During various LDPC decoding embodiments of the invention we compute, at least approximately, such log likelihood ratios (e.g. the messages) where the conditioning information is increasing with each iteration.
In a practical digital message passing decoder implementation, the decoder messages are represented by a finite number of bits. In anticipation of the use of quantization in accordance with the invention, we introduce a scaling parameter δ. In the described exemplary implementations of the invention, messages are integers m and the interpretation of the message is that it represents the loglikelihood mδ. Thus, in the exemplary embodiments our messages are integers which, when scaled by δ in accordance with the invention determine the associated loglikelihoods.
In accordance with the invention, we approximate the function F described in the background section of this application by replacing it with another function that better lends itself to implementation. In various embodiments we slightly modify the initial approximation we discuss, along with its inverse, so that the resulting decoder performs closer to a true belief propagation decoder.
The idea of the approximation can be understood by expanding F(δx) in a series in e^{−δx }as follows.
Thus, for large values of δx the function 1n(coth(δx/2)) can be well approximated by 2e^{−δx}. Bearing in mind that our goal is to find a lowcomplexity implementation, the approximation of the function F(x) by 2e^{δx }is quite attractive. If we simply replace F(x) with 2e^{δx }then the magnitude portion of the check node update takes the form
where [x] denotes the integer part of x.
Note that if we choose δ=1n2 then the computation required for the check node reliability update is particularly simple, allowing for an implementation using addition and shift operations. It turns out, for code rates above roughly ⅕, that setting δ=1n2 provides sufficient resolution to achieve nearly full belief propagation performance. For lower rates this quantization is too coarse and setting
can be preferable. The main advantage of choosing δ in this way is that it greatly simplifies calculation of the In operation.
Consider the case where δ=1n2. In this case the constraint node update computations take the form
Since it is the integer part of the log function that we use, the function can be implemented as a priority encoder, that is, one can implement the function by simply determining the location of the first 1 in the binary representation of the argument.
The approximation of 1n(coth(δx/2)) by 2e^{−δx } can result in relatively large errors in the case of small values of δx. One can compensate somewhat for the error with a mild adjustment of the forward and inverse functions. More specifically, small offsets can be, and in various embodiments of the invention are, applied during the constraint node update. Doing this, the update computations of the take the form
at the variable nodes, and take the form
at the check nodes, where C_{1 }and C_{2 }are constants and “Priority” refers to the operation of finding the first ‘1’ in a suitable binary representation of the argument. We will elaborate more on the meaning and exemplary implementations of the priority encoder in the detailed description which follows.
We turn now to hardware considerations. Note that, ignoring the transformations for the moment, the dominant computation for message updates has the simplified form:
We propose to perform the message passing operations serially in time. Incoming messages arrive, e.g., one per clock cycle. It is therefore desirable to have an efficient pipeline structure that can produce one outgoing edge message per clock cycle. The present invention also includes a description of a particular structure, a node processor, to implement the above computational rule in this manner. The particular implementation provides for an efficient streamlined computation of message passing operations.
As discussed above, the decoding methods and apparatus of the present invention will be described, for purposes of explanation, in the context of an LDPC decoder embodiment. Steps involved in decoding of an LDPC code will first be described with reference to
Variable nodes 406 process messages from the constraint nodes 402 together with the input soft values from the received word y_{1}, . . . , y_{n }to update the value of the output variables x_{1}, . . . , x_{n }corresponding to the variable nodes and to generate messages for the constraint nodes. One message is generated by a variable node for each edge connected to it. The generated message is transmitted along the edge from the variable node to the constraint node attached to the edge. For purposes of explanation, messages from variable nodes to constraint nodes will, from time to time in the present application, be indicated by using the abbreviation V2C while messages from constraint nodes to variable nodes will be indicated by using the abbreviation C2V. Indices may be added to the V and C components of this abbreviation to indicate the particular one of the variable nodes and constraint nodes which serves as the source/destination of a particular message. Each constraint node 402 is responsible for processing the messages received from the variable nodes via the edges. The V2C messages received from the variable nodes are processed by the constraint nodes 402 to generate C2V messages which are then transmitted back along the edges attached to each constraint node. The variable nodes 406 then process the C2V messages, together with the soft input values, to generate and transmit new V2C messages, and generate soft outputs, x_{i}. The sequence of performing processing at the variable nodes 406 comprising: transmitting generated messages to the check nodes 402, generating at the variable nodes soft outputs x_{i}, and receiving messages from the check nodes, may be performed repeatedly, i.e., iteratively, until the outputs x_{i }from the variable nodes 406 indicate that the codeword has been successfully decoded or some other stopping criterion, e.g., completion of a fixed number of message passing iterations, has been satisfied. It should be appreciated that the sequence of operations described above need not occur strictly in the order described. Node processing may proceed asynchronously and variable and constraint node processing may occur simultaneously. Nevertheless, the logic of the iterative process is as described.
Messages, V2C and C2V, may be one or more bits, e.g., K bits each, where K is a positive nonzero integer value. Similarly, the soft outputs x_{i }may be one or more bits. Multiple bit messages and outputs provide the opportunity to relay confidence or reliability information in the message or output. In the case of a multibit (soft) output, the sign of the soft output value may be used to provide the single bit hard output of the decoding process corresponding to a variable node, e.g., the bits of the decoded codeword. Output soft values may correspond to decoded soft values or, alternatively, to socalled extrinsic information (excluding the corresponding input information) which may be used in another larger iterative process within which the LDPC decoder is but one module.
The iterative message passing process associated with decoding an LDPC code will now be discussed further with reference to
When decoding an LDPC code, the processing at each constraint and variable node may be performed independently. Accordingly, variable and/or constraint node processing may be performed one node at time, e.g., in sequence, until some or all of the variable and constraint node processing has been completed for a particular iteration of the decoding process. This allows a single unit of processing hardware to be provided and reused, if desired, to perform the processing associated with each of the variable and/or constraint nodes. Another significant feature of LDPC decoding is that the V2C and C2V messages used during a particular processing iteration need not have been generated at the same time, e.g., during the same processing iteration. This allows for implementations where constraint and variable node processing can be performed asynchronously and in parallel without regard to the time delay since the utilized messages were last updated. Following a sufficient number of message updates and iterations wherein all the variable and constraint nodes process the received messages and generate updated messages, the (hard) output of the variable nodes will converge, assuming that the graph was properly designed and there are no remaining uncorrected errors in the received word being processed.
Given that the processing at each check node and variable node can be viewed as an independent operation, the iterative processing performed at a single exemplary check node C_{n } 502′ and variable node V_{n } 506′ will now be discussed in more detail with reference to
In
In addition to generating the V2C messages, variable node processing results in the updating of the soft output X_{n } 509′ corresponding to the variable node doing the processing. The soft output X_{n }is shown being updated in
As will be discussed further below, in accordance with some embodiments of the present invention, the soft outputs (or their associated hard decisions) may be used to determine when a codeword has been recovered from the received word, i.e., when the parity constraints have been satisfied by the output values. This indicates successful decoding (although the codeword found may be incorrect, i.e., not the one that was transmitted) thereby allowing the iterative decoding process to be halted in a timely fashion, e.g., before some fixed maximum allowed number of message passing iterations is completed.
Check node processing can be performed once a check node, e.g., check node C_{m } 502′, receives V2C messages along the edges to which it is connected. The received V2C messages are processed in the check node to generate updated C2V messages, one for each edge connected to the particular check node. As a result of check node processing, the C2V message transmitted back to a variable node along an edge will depend on the value of each of the V2C messages received on the other edges connected to the check node but (usually and preferably) not upon the V2C message received from the particular variable node to which the C2V message is being transmitted. Thus, C2V messages are used to transmit information generated from messages received from variable nodes other than the node to which the message is being transmitted.
With the receipt of updated C2V messages, variable node processing can be repeated to generate updated V2C messages and soft outputs. Then the updating of C2V messages can be further repeated and so on until the decoder stopping criterion is satisfied.
Thus, the processing shown in
The present invention concerns the form of messages passed, the computation performed thereon, and hardware structures that perform these computations. To place the invention in context we shall briefly describe an LDPC decoder implementation. This implementation is for illustrative purposes. Efficient implementation architectures are discussed in U.S. patent application Ser. No. 09/975,331 filed Oct. 10, 2001 titled: “Methods and Apparatus for Decoding LDPC codes” which is hereby expressly incorporated by reference.
In accordance with one feature of the present invention, message passing decoding input values y are in the form of loglikelihood values which are quantized to be integer multiples of ½ ln 2. The generation of quantized loglikelihood values may involve processing received values to generate therefrom loglikelihood values, e.g., ratios, or approximations thereof. The loglikelihood values are then quantized using step sizes which are integer ratios of ½ ln 2 to produce the quantized loglikelihood values. The loglikelihood values are, in various embodiments, loglikelihood ratios or approximations thereof. The use of such quantized loglikelihood ratios facilitates decoder implementation.
Circuitry for generating quantized loglikelihood values, e.g., ratios, from received values may be incorporated directly into a receiver which forms part of the communications channel 356 that precedes the message passing decoder of the present invention, e.g., decoder 600 shown in FIG. 6.
Various circuits may be used to generate quantized loglikelihood ratios in accordance with the invention. Referring now briefly to
The value y_{in }may be a value received by a receiver circuit which is processed to produce the loglikelihood ratio y_{o }supplied by a message passing decoder of the present invention. The circuit 1500 includes a multiplier 1502 for generating loglikelihood ratios by multiplying the input value Y_{in }by (2/s^{2}) where s^{2 }is a constant corresponding to the additive Gaussian noise introduced by the communications channel into the received signal. The resulting loglikelihood ratio is then quantized by quantizer 1504 to be an integer multiple of ½ ln 2. Quantizer 1504 may be implemented by dividing the loglikelihood ratio generated by multiplier 1502 by ½ ln 2 and then saturating the result to +15 or −15 when the magnitude exceeds 15 and otherwise taking the 5 lsbs (least significant bits) of the resulting value as the quantized loglikelihood ratio Y_{0 }which may then be supplied as an input to decoder circuit 600.
V2C and C2V edge memories 630, 650 each include L K bit memory locations with each K bit location corresponding to one edge and where L is the total number of edges in the LDPC graph being used and K is the number of bits per message exchanged along an edge. The output buffer 660 includes memory for storing variable node output values x, which may be either hard (1 bit) or soft (more than 1 bit) values.
The decoder control module 610 includes information describing the graph in stored form. It uses this information to control the message passing as described below. Each received value and message is assumed to be comprised of K bits. The decoder operates serially. It first performs variable node update operations and then constraint node update operations. It repeats this cycle some fixed number of times concluding after a final variable node update. Initially the C2V message memory is populated with zeroes. (Note that variable node processing and constraint node processing may be physically concurrent in time. The ordering described above indicates the flow of information during the processing.)
We will now describe a variable node update. The decoder control module 610 causes the C2V messages to be read out of the C2V message memory in variable node socket order and to be delivered to the variable node processor 620. The decoder control module 610 signals to the C2V edge message memory 650 a message identifier (e.g., memory location or pointer) indicating which message is to be read out at that point in time. Referring to
Messages for a given node are processed by the variable node processor 620. The variable node processor 620 receives from the decoder control module 610 a signal, the node clock signal, that indicates node boundaries. This signal informs the variable node processor, in effect, about the degree of the node currently being processed. The signal can, and in various embodiments is, sent, e.g., at the point in time coincident with the arrival of the last incoming messages corresponding to a particular node.
Node update computations are performed in the variable node processor 620. Outgoing V2C messages are emitted in variable socket order, i.e., corresponding to the edge order of the incoming messages, and these messages are stored in V2C edge message memory 630. Soft or hard output values are stored in the output buffer 660. Upon completion of the variable node update, unless it is the last update, the decoder proceeds to performing a constraint node update.
We will now describe a constraint node update. It is very similar to a variable node update and we will be brief. The decoder control module 610 causes the V2C messages to be read out of the V2C message memory 630 in constraint socket order and to be delivered to the constraint node processor 640. The decoder control module 610 signals to the V2C edge message memory 630 a message identifier (e.g., memory location) indicating which message is to be read out. Messages for a given constraint node are processed by the constraint node processor 640. The constraint node processor 640 receives a signal, the node clock signal, from the decoder control module 610 that indicates node boundaries. Outgoing C2V messages are emitted in constraint socket order, i.e., corresponding to the edge order of the incoming messages, and these messages are stored in C2V edge message memory 650.
Together the variable node update and the constraint node update comprise a complete iteration. (As remarked above, the variable and constraint node processing may occur concurrently.)
Various node processor features of the present invention will now be described in the context of the exemplary LDPC decoder system 600 shown in FIG. 6. We shall describe a particular set of computations and message formats which may be used for LDPC decoding in accordance with the present invention. It is to be understood that the same computations, described in implementing node processors in the serial decoder of
Let us give a precise description of an exemplary fivebit message based algorithm which embodies the present invention. Input soft values and messages are in loglikelihood ration form and quantized in multiples of δ=1n2 in accordance with the invention. Thus, the five bits of a message represent possible integer values {−15, −14, . . . , −1,0,1, . . . , 15}. In practice it is convenient to represent these soft values as “sign and magnitude”. A sign takes the value 0 or 1 indicating the preferred value, e.g., the associated hard decision, for the associated bit. The magnitude indicates the reliability of the sign: Larger magnitudes indicate higher reliability. (It is generally a good idea to limit input soft values magnitudes to the range {0, 1, . . . , M} for some M<15. Note also that in this representation there are actually two ‘0’ magnitude values, one with sign 0 and one with sign 1.) We will therefore write a message as a pair (m_{p}, m_{r}) where m_{p }denotes the sign bit and m_{r }denotes the reliability, a four bit nonnegative value in our example. Given such a message let us use m to denote the representative scaled loglikelihood ratio, i.e., m=(−1)^{m} _{ p }m_{r}. The update formula for the variable nodes is given by
When the outgoing message m^{V2C}(j) has the value 0 the sign may be chosen arbitrarily. When the outgoing message magnitude exceeds 15 it is saturated, e.g., set to 15.
Each received message is also passed through a delay line including variable delay element 760 whose duration corresponds to the degree of the node being implemented.
The first message associated to the particular variable node being processed emerges from the delay line and the message's value is subtracted from the latched total sum stored in latch 730 by adder 740. The outgoing result is subsequently passed through a saturation operator 770 to ensure that the outgoing message value is in the desired range, e.g., limited to Kbits. Unit delay elements 742 and 772 positioned before and after saturation operator 770 are used to synchronize variable node processing operations with constraint node processing operations.
We will first describe the sign update processing as performed by sign processing circuit 802. Incoming sign bits are delayed one clock cycle by unit delay element 803 prior to being supplied to an input of exclusive OR (XOR) logic circuit 810. XOR circuit 810 performs an exclusiveor or modulo 2 sum of the incoming sign bit and a previous XOR result which is delayed by a second unit delay element 815 prior to being supplied to a second input of the XOR circuit 810. In this manner, XORing of all the sign bits corresponding to the node being processed produces a total XOR result or product, SUM_{sign}, through iterative processing. The value SUM_{sign }is stored in latch 830 under control of the node clock signal 830 for subsequent XORing with delayed sign bits corresponding to the node. MUX 813 is used to output the value 0 to be XORed with the sign bit of the first message corresponding to a node. At other times it outputs the delayed XOR result.
In addition to being passed through the XOR path beginning with delay element 803, each sign bit is also passed through a delay line which includes variable delay element 820. The delay of element 820 is controlled by the node degree signal so that the duration of the delay imposed on the sign bit will correspond to the degree of the node. When all sign bits corresponding to a node have been combined the total sum (exclusiveor), which we denote as SUM_{sign }is stored in latch 830. The latching of the value SUM_{sign }occurs under the direction of an external node clock signal as in the variable node update process discussed previously. This signal is also used to control the output of MUX 813.
As in the variable node update, the sign bits emerge from the delay line in sequence. The value of the delayed sign bit is subtracted (exclusiveor operation) from SUM_{sign }in an adder 840. The result constitutes the sign of the outgoing message. Note that some additional delay elements 841, 843 have been inserted into the processor 802, to keep the sign update synchronized with magnitude update performed by circuit 804.
We will now describe the magnitude update processing performed by magnitude processing circuit 804. In the first step incoming magnitudes m_{r} ^{V2C}(i), represented using (K1) bits, are converted to constraint domain values. This amounts to replacing the message m_{r} ^{V2C }(i) with the value C2^{−m} ^{ r } ^{ V2C } ^{(i) }using transform circuit 850. The goal of this transform process is to represent the message values in a form in which constraint processing can be implemented through the use of simple sums and subtractions. In practice this transform can be implemented as a shift operation: the value C is stored in binary form and it is shifted to the right by m_{r} ^{V2C}(i) to obtain the transformed message. For the 5 bit decoder example the value C found to be effective is given by 6000 in hexadecimal notation.
See
For example, assume an input in step 902 of the 4 bits (0010) which has a decimal value of 2. In step 906, the binary constant C=110000000000000 will be shifted two places to the right and the leftmost bits will be padded with zeros resulting in a constraint node (binary) domain magnitude value of 001100000000000.
In step 908, the magnitude portion 910 (e.g., 15 bits) of the message now in constraint node form is output for further processing. The output value represents a transformed magnitude value suitable for constraint node processing through addition operations.
Referring once again to
A sum of transformed edge message magnitudes is created by using summer 860 to add the edge message output by delay element 851 to the delayed output of the summer 860 thereby creating an accumulated sum, SUM_{mag}. The accumulated sum, SUM_{mag}, is stored in latch 870 upon receipt of the node clock signal indicating that all the edge messages corresponding to the node have been summed together. The node clock signal is also used to control mux 863 to output a “0” when the first message corresponding to a node is supplied to summer 860. Thus, mux 860 allows for the resetting of the accumulated sum at the start of processing of messages corresponding to each of a plurality of nodes.
The delayed transformed edge message magnitudes subsequently emerge from the delay line 880 and their values are subtracted from the stored sum SUM_{mag }in an adder 890 prior to being supplied to unit delay element 891. Then, an inverse transform is performed on the delayed outgoing magnitude obtained from delay element 891 by transform circuit 895.
This second transform circuit, which performs a transform from the constraint node to the variable node message representation, in one exemplary embodiment, operates as follows. A priority encoder determines the location of the first 1 in the binary representation of the constraint domain magnitude message. Let us express this location from the right. Therefore, let v denote a constraint domain magnitude and let l(v) denote its “location”. In general, if the decimal integer value of v is in the range from 2^{j }and 2^{j+1}−1 inclusive, then l(v)=j. If v is 0 then l(v) is 0. If l(v) is greater than or equal to 15 (in the case of 4 bit variable node message magnitudes) then the outgoing magnitude is set to 0. Otherwise the outgoing magnitude is 15l(v).
In step 1004, the magnitude portion 1002 of a message in constraint node domain form is received and the position of the first “1” from the left is determined by counting bit positions from the right. For example, if the magnitude portion 1002 was (00000010000000000100) a priority encoder could be used to determine that the first 1 bit from the left occurs in bit position 14 as measured from the right.
Next, in step 1006, the determined bit position is compared to the maximum value which can be represented by the number of bits used to represent the message magnitudes in the variable node domain form. For example, if 4 bits were used for message magnitudes in the variable node domain the maximum value would be 15. In such a case, if the determined bit position was greater than 15 operation would proceed to step 1008. Otherwise operation proceeds from step 1006 to step 1010.
In step 1008 all the bits in the variable node domain message magnitude representation, e.g., 4 bits, are set to zero thereby generating the variable node domain form of the received constraint node message magnitude 1002.
The processing in step 1010, will now be described. In step 1010, the message magnitude in the variable domain form is generated by subtracting the number of the identified bit position obtained in step 1006 from the largest value that can be represented using the number of bits used to represent the message magnitude in the variable node domain form. For example, assuming a 4 bit magnitude representation in the variable node domain, in step 1010 the bit position from step 1006, e.g., 14 in the case of the example, would be subtracted from 15 resulting in a variable node message magnitude of (15−14=1) one represented in binary as (0001).
In step 1012 the message magnitude 1014 now in variable node domain magnitude form is output, e.g., to delay element 897.
In some implementations of the constraint node processor it will be more convenient to store reliabilities in the delay line 880 in the variable domain form rather than the constraint domain form. This can reduce complexity since the variable domain form requires significantly fewer bits than the constraint domain form. To modify
It will be appreciated that, although we use 5 bit variable node messages in the above examples (1 sign bit and 4 magnitude bits), the described rules can be applied to messages having fewer or more bits simply by decreasing or increasing the utilized range and adjusting constants as necessary.
It will also be appreciated that in some cases a spacing of 2ln2 for the loglikelihood ratios may be more desirable than the discussed exemplary ln2 spacing. This case will typically be used in conjunction with messages comprised of fewer bits. The change from ln2 to 2ln2 will change the update rules discussed above at the constraint nodes but not the variable nodes. The modification at the constraint nodes amounts to noticing that all messages are as in the case for ln2 spacing but only even valued magnitudes are allowed and, in this case, the last bit of the magnitude will always be 0 and need not, and in various embodiments will not, be passed as part of the message.
In some other cases a spacing of ½ ln2 may be preferable.
In step 1106 the constant C is shifted to the right by the number of places specified by the decimal value of the remaining bits (e.g., 4 bits) of the message magnitude and zeros are inserted into the left bit positions vacated as a result of the shift operation. Then in step 1108 the message magnitude 1110 (15 bits), now in constraint node domain magnitude form, are output to e.g., delay element 851.
In the ½ ln2 case, the inverse transformation, e.g., constraint node domain representation to variable node domain representation, involves an additional step beyond that present in the ln2 spacing case which is used to determine the least significant bit of the outgoing message. The value obtained using the ln2 spacing rule provides the other, higher order, bits in the message.
To determine the value of the least significant bit in the ½ ln2 case, some bits to the right of the first 1 of the constraint node domain magnitude are examined. A threshold is used to determine whether the least significant bit will be 0 or 1. In one particular ½ ln2 embodiment, the constraint node domain value v is compared with the threshold value t 2^{l(v) }where t is some appropriate predetermined constant. If v is larger than t 2^{l(v) }than the LSB is set to 0 otherwise it will be set to 1. It will be appreciated that there are many alternative implementations using the same threshold rule.
Processing proceeds to step 1208, as a result of a determination that the message magnitude should be set to zero. In step 1208, all bits in the variable node domain message magnitude representation are set to zero to generate the message magnitude (e.g., 00000) in the variable node domain form. With the transform complete, operation proceeds from step 1208 to step 1214.
In step 1210, which represents an alternative processing path to step 1208, the identified number, i.e., number of the bit position, is subtracted from the largest value that can be represented by the number of nonLSB bits of a message magnitude in the variable node domain form. For example, assuming a 5 bit magnitude representation in the variable node domain form, there are 4 bits in addition to the LSB. The largest number that can be represented by 4 bits is 15. Accordingly, in such an embodiment in step 1210, the number of the identified bit position would be subtracted from 15 to produce the 4 high order bits of the magnitude value in the variable node domain.
In step 1212, the LSB, e.g., the fifth bit of the 5 bit exemplary magnitude value, is determined from the value of one or more bits to the right of the leftmost “1” present in the magnitude value in the constraint node domain representation 1202 of the message magnitude.
In step 1214, the generated message magnitude 1216, e.g., 5 bits, now in variable node form is output, e.g., to unit delay element 897.
and that it is desirable to have an efficient pipeline structure that can produce one outgoing edge message per clock cycle. The hardware design of the present invention gives due consideration to the following observations and supports the listed features:

 there is no explicit dependency between input and output data, allowing the pipeline to be sufficiently deep to allow very high clock rate;
 the pipeline is able to maintain it's efficiency while processing nodes of variable degree;
 addition and subtraction in the formula above can be generalized to any operation that has an inverse and follows associative law (modulo addition/subtraction, multiplication/division etc);
 the pipeline may include additional pre and postprocessing stages such as function transform, saturation, delay elements, etc.
A message processing system 1300, representing a generalized proposed pipeline structure, is illustrated in FIG. 13. The processing system 1300 sequentially receives input messages “A”, one per clock cycle as determined by an edge clock signal used to drive the various system components. It also receives a node clock signal and a node degree signal. The node clock signal serves as a node framing signal and is asserted when a message corresponding to a new node is supplied to the message input of accumulator module 1302. As will be discussed below, the node clock signal is used to control various operations, including the initialization of a running message sum and the latching of a total sum, generated for each node. The node clock signal is generated as a function of the degree, e.g., number of messages, corresponding to the node for which processing is being implemented. The node degree signal indicates the degree of the node for which processing is being performed and thus the number of messages that correspond to the node. As will be discussed below, the node degree signal is used to control a variable delay element 1306 used to delay the received messages. Operation of the system 1300 will be discussed further below with reference to the corresponding data flow shown in FIG. 14. For simplicity any pre and postprocessing stages are skipped and simple addition and subtraction operations assumed.
The processing system 1300 comprises two computational stages, sometimes referred to as modules, i.e., an accumulation module “A” 1302 and a subtraction module “S” 1304. Since the subtraction module generates output messages it is sometimes also called a message generation module. The system 1300 also comprises a variable message delay path which includes a variable delay element 1306 which outputs delayed messages “D”.
The accumulation module “A” 1302 receives input messages in sequence and generates, for each set of messages corresponding to a node, a total sum. Accumulation module 1302 comprises a summer 1310, unit delay element 1312, a mux 1314 and a node sum latch 1316. The unit delay element 1312 is used to store a running sum generated by summer 1310. MUX 1314 supplies either a zero or the running sum output by delay element 1312, to one of the inputs of summer 1310. The MUX is controlled by the node clock signal to output the zero when the first message corresponding to a node is supplied to the other input of the summer 1310 and the running sum B at all other times. In this manner, summer will add received messages corresponding to a node to generate a total sum for the node.
The node clock signal is also used to strobe the running sum into the node sum latch 1316. At the time the node clock signal is asserted and the value latched, the running sum represents a total sum for the node.
The subtraction or message generation module “S” 1304 receives as its input the total sum generated by the accumulation module 1302 and the input messages delayed by variable delay element 1306. Stage “S” 1304 sequentially subtracts delayed input messages from the total sum “C” stored in node sum latch 1316 producing output messages for a node, e.g., node N, one message per clock cycle. The results of the subtraction operation, an output message “E” is stored in an output register 1321 prior to being output by Operation of stages “A” 1302 and “S” 1304 can be fully overlapped or folded. For example, while stage “A” 1302 is performing processing for node N+1, stage “S” can perform processing for node N.
The purpose of variable delay line which includes delay element 1306 is to supply delayed original input messages, represented as “D”, for node N to subtraction stage “S” while storing input messages for node N+1. The delay, in units of processing clock cycles, of delay element 1308, applied to messages corresponding to a node, equals the degree of the current node to which the messages correspond. For example, message corresponding to a node of degree 4 will be delayed four clock cycles by variable delay element 1306 while messages corresponding to a node of degree 2 will be delayed two clock cycles. To support multiple node degrees, in one embodiment, variable delay element 1306 is implemented with at least enough storage space to store as many messages as the highest node degree to be supported.
Use of the variable delay element 1306 and delayed message D saves message memory bandwidth by removing duplicated reads required for folded pipeline operation. Note that the delay line, including delay element 1306, can be practically implemented either with external delay value control (e.g. shift register with variable output tap) or with internal delay value control (e.g. selfcontained FIFO). The first method may be preferable for vector decoders as the delay control logic can be shared across multiple processing nodes.
The pipeline structure described above allows the node degree to be changed on the fly by altering both the frequency of the node clock signal used for node framing signal and changing the degree signal used to control the message delay imposed by delay element 1306. Via these control signals, pipeline depth can easily be changed. In this context, the pipeline depth may be interpreted as the delay from the time the first incoming message (for node N) is fed into the system 1300 for processing to the time the first outgoing message E (for node N) appears at the pipeline output. Variable depth pipeline can offer significant performance advantage where irregular LDPC codes are to be supported since the total number of cycles required per iteration is equal to the number of edge edges in the graph plus the degree spread (the difference between the maximum and minimum degrees).
In contrast, a fixed pipeline design would require (maximum edge degree) * (number of nodes) cycles per iteration which can be noticeably larger than the number of edges, especially when degree spread is large.
The second column 1402 lists the received messages A, in the order they are received, one per clock cycle. The third column 1404 lists the running sum B, during each processing clock cycle. Note that in column 1404, the node indicator, e.g., n1 from the message n1_e0, is omitted in column 1404 for the purposes of brevity. The fourth column 1406 lists the latched total sum C generated for each node as part of the message processing. The fifth column 1408 lists the delayed value D output by the delay element 1306 which is subtracted from a sum in column C to produce the output message E. The generated output messages are listed in the sixth column 1410.
Naturally, due to pipeline depth change, empty slots occur in the output data stream. If nodes are sorted by degree in monotonic order (increasing or decreasing) the total number of empty slots per iteration is equal to degree spread and is very small compared to number of messages processed, consequently very high pipeline utilization is achieved.
The above described LDPC decoding methods and node processor implementations allow for LDPC decoding to be performed on various hardware platforms such as Field Programmable Gate Arrays or in an Application Specific Integrated Circuit. The present invention is especially useful in these settings where the simple parallelism and easy to implement nodes can be explicitly exploited.
Numerous additional variations of the decoding methods and apparatus of the present invention will be apparent to those skilled in the art in view of the above description of the invention. Such variations are to be considered within the scope of the invention.
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US29848001P true  20010615  20010615  
US32846901P true  20011010  20011010  
US09/975,331 US6633856B2 (en)  20010615  20011010  Methods and apparatus for decoding LDPC codes 
US10/117,264 US6938196B2 (en)  20010615  20020404  Node processors for use in parity check decoders 
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Cited By (74)
Publication number  Priority date  Publication date  Assignee  Title 

US20040054960A1 (en) *  20020703  20040318  Mustafa Eroz  Method and system for providing low density parity check (LDPC) encoding 
US20040123230A1 (en) *  20021224  20040624  Lee SangHyun  Simplified messagepassing decoder for lowdensity paritycheck codes 
US20050010846A1 (en) *  20020827  20050113  Atsushi Kikuchi  Decoding device and decoding method 
US20050063484A1 (en) *  20020726  20050324  Mustafa Eroz  Satellite communincation system utilizing low density parity check codes 
US20050081128A1 (en) *  20031010  20050414  Jones Christopher R.  Decoding low density parity codes 
US20050166133A1 (en) *  20020703  20050728  Hughes Electronics Corporation  Method and system for decoding low density parity check (LDPC) codes 
US20050204272A1 (en) *  20040203  20050915  Hiroyuki Yamagishi  Decoding apparatus and method and information processing apparatus and method 
US20050229087A1 (en) *  20040413  20051013  Sunghwan Kim  Decoding apparatus for lowdensity paritycheck codes using sequential decoding, and method thereof 
US20050240853A1 (en) *  20030513  20051027  Takashi Yokokawa  Decoding device, decoding method, and program 
US20050257124A1 (en) *  20010615  20051117  Tom Richardson  Node processors for use in parity check decoders 
US20050262420A1 (en) *  20040521  20051124  Samsung Electronics Co., Ltd.  Apparatus and method for decoding low density parity check codes 
US20050262421A1 (en) *  20020531  20051124  Tran Hau T  Efficient front end memory arrangement to support parallel bit node and check node processing in LDPC (Low Density Parity Check) decoders 
US20050268204A1 (en) *  20040531  20051201  Kabushiki Kaisha Toshiba  Decoding apparatus and decoding circuit 
US20050271160A1 (en) *  20020703  20051208  Mustafa Eroz  Bit labeling for amplitude phase shift constellation used with low density parity check (LDPC) codes 
US20050278604A1 (en) *  20030513  20051215  Takashi Yokokawa  Decoding method, decoding device, and program 
US20060026486A1 (en) *  20040802  20060202  Tom Richardson  Memory efficient LDPC decoding methods and apparatus 
US20060085720A1 (en) *  20041004  20060420  Hau Thien Tran  Message passing memory and barrel shifter arrangement in LDPC (Low Density Parity Check) decoder supporting multiple LDPC codes 
US20060117240A1 (en) *  20041110  20060601  Vladimir Novichkov  Hierarchical design and layout optimizations for high throughput parallel LDPC decoders 
US20060156181A1 (en) *  20041027  20060713  Samsung Electronics Co., Ltd.  Method for puncturing an LDPC channel code 
US20060190797A1 (en) *  20050224  20060824  Weizhuang Xin  Low complexity decoding of low density parity check codes 
US20060242093A1 (en) *  20010615  20061026  Tom Richardson  Methods and apparatus for decoding LDPC codes 
US20070011568A1 (en) *  20020815  20070111  Texas Instruments Incorporated  HardwareEfficient Low Density Parity Check Code for Digital Communications 
US20070011567A1 (en) *  20050516  20070111  Samsung Electronics Co., Ltd.  Method for padding and puncturing low density parity check code 
US20070089016A1 (en) *  20051018  20070419  Nokia Corporation  Block serial pipelined layered decoding architecture for structured lowdensity paritycheck (LDPC) codes 
US20070089019A1 (en) *  20051018  20070419  Nokia Corporation  Error correction decoder, method and computer program product for block serial pipelined layered decoding of structured lowdensity paritycheck (LDPC) codes, including calculating checktovariable messages 
US20070127387A1 (en) *  20051205  20070607  Lee Tak K  Partialparallel implementation of LDPC (low density parity check) decoders 
US20070150789A1 (en) *  20051201  20070628  Electronics And Telecommunications Research Institute  LDPC decoding apparatus and method using typeclassified index 
US20070157062A1 (en) *  20060103  20070705  Broadcom Corporation, A California Corporation  Implementation of LDPC (Low Density Parity Check) decoder by sweeping through submatrices 
US20070157061A1 (en) *  20060103  20070705  Broadcom Corporation, A California Corporation  Submatrixbased implementation of LDPC (Low Density Parity Check ) decoder 
US20070204197A1 (en) *  20051220  20070830  Takashi Yokokawa  Decoding device, control method, and program 
US20070283213A1 (en) *  20060519  20071206  National Chiao Tung University  Method and apparatus for selfcompensation on beliefpropagation algorithm 
US20070283218A1 (en) *  20060419  20071206  Gopalakrishnan Subramanyam H  Low density parity check code decoder 
US20080028272A1 (en) *  20030226  20080131  Tom Richardson  Method and apparatus for performing lowdensity paritycheck (ldpc) code operations using a multilevel permutation 
US20080052594A1 (en) *  20060728  20080228  Yedidia Jonathan S  Method and system for replica groupshuffled iterative decoding of quasicyclic lowdensity parity check codes 
US20080082895A1 (en) *  20020726  20080403  The Directv Group, Inc.  Method and system for generating low density parity check codes 
US20080104474A1 (en) *  20041001  20080501  Joseph J Laks  Low Density Parity Check (Ldpc) Decoder 
US20080109698A1 (en) *  20060725  20080508  Legend Silicon  Hybrid minsum decoding apparatus with low bit resolution for ldpc code 
US20080178066A1 (en) *  20070118  20080724  Samsung Electronics Co., Ltd.  Method and apparatus for receiving data in communication system 
US20080276156A1 (en) *  20070501  20081106  Texas A&M University System  Low density parity check decoder for regular ldpc codes 
US20090037799A1 (en) *  20070731  20090205  ChihHao Liu  Operating method applied to low density parity check (ldpc) decoder and circuit thereof 
US20090146849A1 (en) *  20071207  20090611  ChihHao Liu  Multimode multiparallelism data exchange method and device thereof 
US20090177869A1 (en) *  20050317  20090709  Qualcomm Incorporated  Efficient check node message transform approximation for ldpc decoder 
US20090187803A1 (en) *  20080121  20090723  Anobit Technologies Ltd.  Decoding of error correction code using partial bit inversion 
US20100023834A1 (en) *  20061026  20100128  Qualcomm Incorproated  Coding schemes for wireless communication transmissions 
US20100031115A1 (en) *  20080804  20100204  Ara Patapoutian  Low density parity check decoder using multiple variable node degree distribution codes 
US20100223225A1 (en) *  20090302  20100902  Lyric Semiconductor, Inc.  Analog computation using numerical representations with uncertainty 
US7793201B1 (en)  20060511  20100907  Seagate Technology Llc  Bit error detector for iterative ECC decoder 
WO2010101944A1 (en) *  20090302  20100910  David Reynolds  Belief propagation processor 
US7818649B1 (en) *  20051130  20101019  Aquantia Corporation  Efficient message passing scheme of iterative error correcting decoders 
US20100269019A1 (en) *  20071126  20101021  Sony Corporation  Data processing apparatus and data processing method 
US20100332955A1 (en) *  20090630  20101230  Anobit Technologies Ltd.  Chien search using multiple basis representation 
US7930389B2 (en)  20071120  20110419  The Invention Science Fund I, Llc  Adaptive filtering of annotated messages or the like 
US8065404B2 (en)  20070831  20111122  The Invention Science Fund I, Llc  Layering destinationdependent content handling guidance 
US8082225B2 (en)  20070831  20111220  The Invention Science Fund I, Llc  Using destinationdependent criteria to guide data transmission decisions 
US8140930B1 (en) *  20050513  20120320  Nec Corporation  Encoder and decoder by LDPC coding 
US8266493B1 (en) *  20080109  20120911  L3 Communications, Corp.  Lowdensity parity check decoding using combined check node and variable node 
US8327242B1 (en)  20080410  20121204  Apple Inc.  Highperformance ECC decoder 
US8392793B2 (en)  20040813  20130305  Dtvg Licensing, Inc.  Code design and implementation improvements for low density parity check codes for multipleinput multipleoutput channels 
US8429498B1 (en)  20090325  20130423  Apple Inc.  Dual ECC decoder 
TWI410055B (en) *  20071126  20130921  Sony Corp  
US8595569B2 (en)  20040721  20131126  Qualcomm Incorporated  LCPC decoding methods and apparatus 
US8601352B1 (en)  20090730  20131203  Apple Inc.  Efficient LDPC codes 
US8650464B1 (en) *  20100907  20140211  Applied Micro Circuits Corporation  Symmetric diagonal interleaving and encoding/decoding circuit and method 
US8682982B2 (en)  20070619  20140325  The Invention Science Fund I, Llc  Preliminary destinationdependent evaluation of message content 
US8879640B2 (en)  20110215  20141104  Hong Kong Applied Science and Technology Research Institute Company Limited  Memory efficient implementation of LDPC decoder 
US8892979B2 (en)  20061026  20141118  Qualcomm Incorporated  Coding schemes for wireless communication transmissions 
US8972831B2 (en)  20100111  20150303  Analog Devices, Inc.  Belief propagation processor 
US8984133B2 (en)  20070619  20150317  The Invention Science Fund I, Llc  Providing treatmentindicative feedback dependent on putative content treatment 
US20150178151A1 (en) *  20131220  20150625  Sandisk Technologies Inc.  Data storage device decoder and method of operation 
US9276610B2 (en) *  20140127  20160301  Tensorcom, Inc.  Method and apparatus of a fullypipelined layered LDPC decoder 
US9374242B2 (en)  20071108  20160621  Invention Science Fund I, Llc  Using evaluations of tentative message content 
US9391817B2 (en)  20140324  20160712  Tensorcom, Inc.  Method and apparatus of an architecture to switch equalization based on signal delay spread 
US9473266B1 (en) *  20020710  20161018  Seagate Technology Llc  Scheduling strategies for iterative decoders 
US10084481B2 (en)  20141218  20180925  Apple Inc.  GLDPC soft decoding with hard decision inputs 
Families Citing this family (46)
Publication number  Priority date  Publication date  Assignee  Title 

US6938196B2 (en) *  20010615  20050830  Flarion Technologies, Inc.  Node processors for use in parity check decoders 
US6829308B2 (en) *  20020703  20041207  Hughes Electronics Corporation  Satellite communication system utilizing low density parity check codes 
US7139959B2 (en) *  20030324  20061121  Texas Instruments Incorporated  Layered low density parity check decoding for digital communications 
KR100809619B1 (en) *  20030826  20080305  삼성전자주식회사  Apparatus and method for coding/decoding block low density parity check code in a mobile communication system 
EP1536568A1 (en) *  20031126  20050601  Matsushita Electric Industrial Co., Ltd.  Belief propagation decoder cancelling the exchange of unreliable messages 
CN1301012C (en) *  20031203  20070214  北京泰美世纪科技有限公司  Framing method based on LDPC 
KR100744343B1 (en) *  20031219  20070730  삼성전자주식회사  Apparatus for transmitting and receiving coded data by encoder having unequal error probability in mobile communication system and the method therof 
US20050193320A1 (en) *  20040209  20050901  President And Fellows Of Harvard College  Methods and apparatus for improving performance of information coding schemes 
WO2005096510A1 (en) *  20040402  20051013  Nortel Networks Limited  Ldpc encoders, decoders, systems and methods 
KR100659266B1 (en)  20040422  20061220  삼성전자주식회사  System, apparatus and method for transmitting and receiving the data coded by the low density parity check code having a variable coding rate 
US7814402B2 (en)  20040514  20101012  The Governors Of The University Of Alberta  Method and apparatus for digitserial communications for iterative digital processing algorithms 
FR2871965B1 (en) *  20040617  20060901  Turboconcept Soc Par Actions S  Method and correcting code decoding device error and systems implementing them 
JP4282558B2 (en)  20040630  20090624  株式会社東芝  Lowdensity paritycheck code decoder and method 
US7181676B2 (en) *  20040719  20070220  Texas Instruments Incorporated  Layered decoding approach for low density parity check (LDPC) codes 
US7730377B2 (en) *  20040722  20100601  Texas Instruments Incorporated  Layered decoding of low density parity check (LDPC) codes 
KR20060032464A (en) *  20041012  20060417  삼성전자주식회사  Efficient decoding method and apparatus of low density parity code 
KR100703271B1 (en) *  20041123  20070403  삼성전자주식회사  Decoding Method and Apparatus of Low Density Parity Code Using Unified processing 
US7752520B2 (en)  20041124  20100706  Intel Corporation  Apparatus and method capable of a unified quasicyclic lowdensity paritycheck structure for variable code rates and sizes 
DE102004059331A1 (en) *  20041209  20060614  Robert Bosch Gmbh  Hand machine tool with a coupling 
JP4293172B2 (en) *  20050913  20090708  ソニー株式会社  Decoding apparatus and decoding method 
JP4819470B2 (en) *  20051011  20111124  三星電子株式会社Ｓａｍｓｕｎｇ Ｅｌｅｃｔｒｏｎｉｃｓ Ｃｏ．，Ｌｔｄ．  Decoding apparatus and decoding method 
US7757149B2 (en) *  20051012  20100713  Weizhuang Xin  Broadcast message passing decoding of low density parity check codes 
CN101322319B (en) *  20051201  20121128  汤姆逊许可公司  Device and method for decoding low density oddeven check coded signal 
GB2434946B (en) *  20060201  20080723  Toshiba Res Europ Ltd  Wireless communications apparatus 
KR20080104376A (en) *  20060317  20081202  미쓰비시덴키 가부시키가이샤  Communication device, decoding device, information transmission method, and decoding method 
JP4662278B2 (en)  20060428  20110330  富士通株式会社  Error correction device, an encoder, decoder, method and information storage device 
JP4253332B2 (en)  20060703  20090408  株式会社東芝  Decoding device, method, and program 
GB0624572D0 (en) *  20061208  20070117  Cambridge Silicon Radio Ltd  Data Proccessing in Signal Transmissions 
KR100976886B1 (en)  20061222  20100818  크로스텍 캐피탈, 엘엘씨  CMOS Image Sensors with Floating Base Readout Concept 
US20100122143A1 (en) *  20070327  20100513  Hughes Network Systems, Llc  Method and system for providing low density parity check (ldpc) coding for scrambled coded multiple access (scma) 
WO2009046534A1 (en) *  20071011  20090416  The Royal Institution For The Advancement Of Learning/Mcgill University  Methods and apparatuses of mathematical processing 
JP4650485B2 (en) *  20071220  20110316  住友電気工業株式会社  Decoding device 
JP4572937B2 (en) *  20080123  20101104  ソニー株式会社  Decoding apparatus and method, program, and recording medium 
KR101503058B1 (en) *  20080226  20150318  삼성전자주식회사  Channel encoding / decoding method and apparatus in a communication system using Low Density Parity Check code 
US8301979B2 (en) *  20081007  20121030  Sandisk Il Ltd.  Low density parity code (LDPC) decoding for memory with multiple log likelihood ratio (LLR) decoders 
TWI427936B (en) *  20090529  20140221  Sony Corp  Receiving apparatus, receiving method, program, and receiving system 
US8832534B1 (en) *  20100104  20140909  Viasat, Inc.  LDPC decoder architecture 
US8566668B1 (en)  20100104  20131022  Viasat, Inc.  Edge memory architecture for LDPC decoder 
JP5991580B2 (en) *  20120801  20160914  Ｎｅｃエンジニアリング株式会社  Turbo decoder, a log likelihood ratio calculation unit for use therein, the method turbo decoding, the loglikelihood ratio arithmetic method, turbo decoding program and loglikelihood ratio calculation program 
US9612903B2 (en)  20121011  20170404  Micron Technology, Inc.  Updating reliability data with a variable node and check nodes 
US9191256B2 (en) *  20121203  20151117  Digital PowerRadio, LLC  Systems and methods for advanced iterative decoding and channel estimation of concatenated coding systems 
US8930789B1 (en) *  20130123  20150106  Viasat, Inc.  Highspeed LDPC decoder 
US9094132B1 (en)  20130123  20150728  Viasat, Inc.  High data rate optical transport network using 8PSK 
KR20150031568A (en)  20130916  20150325  삼성전자주식회사  Apparatus and method for decoding low density parity check(ldpc) codes in digital video broadcasting(dvb) system 
CN103916134B (en) *  20140324  20170111  清华大学  LDPC decoding method and aliasing aliasing decoder synergistic multicore 
KR20180054518A (en) *  20151013  20180524  후아웨이 테크놀러지 컴퍼니 리미티드  Decoding device and method and signal transmission system 
Citations (35)
Publication number  Priority date  Publication date  Assignee  Title 

US3542756A (en)  19680207  19701124  Codex Corp  Error correcting 
US3665396A (en)  19681011  19720523  Codex Corp  Sequential decoding 
US4295218A (en)  19790625  19811013  Regents Of The University Of California  Errorcorrecting coding system 
US5157671A (en)  19900529  19921020  Space Systems/Loral, Inc.  Semisystolic architecture for decoding errorcorrecting codes 
US5271042A (en)  19891013  19931214  Motorola, Inc.  Soft decision decoding with channel equalization 
US5293489A (en)  19850124  19940308  Nec Corporation  Circuit arrangement capable of centralizing control of a switching network 
US5313609A (en)  19910523  19940517  International Business Machines Corporation  Optimum writeback strategy for directorybased cache coherence protocols 
US5396518A (en)  19930505  19950307  Gi Corporation  Apparatus and method for communicating digital data using trellis coding with punctured convolutional codes 
US5457704A (en)  19930521  19951010  At&T Ipm Corp.  Post processing method and apparatus for symbol reliability generation 
US5526501A (en)  19930812  19960611  Hughes Aircraft Company  Variable accuracy indirect addressing scheme for SIMD multiprocessors and apparatus implementing same 
US5615298A (en)  19940314  19970325  Lucent Technologies Inc.  Excitation signal synthesis during frame erasure or packet loss 
US5671221A (en)  19950614  19970923  Sharp Microelectronics Technology, Inc.  Receiving method and apparatus for use in a spreadspectrum communication system 
US5860085A (en)  19940801  19990112  Cypress Semiconductor Corporation  Instruction set for a content addressable memory array with read/write circuits and an interface register logic block 
US5864703A (en)  19971009  19990126  Mips Technologies, Inc.  Method for providing extended precision in SIMD vector arithmetic operations 
US5867538A (en)  19950815  19990202  Hughes Electronics Corporation  Computational simplified detection of digitally modulated radio signals providing a detection of probability for each symbol 
US5892962A (en)  19961112  19990406  Lucent Technologies Inc.  FPGAbased processor 
US5933650A (en)  19971009  19990803  Mips Technologies, Inc.  Alignment and ordering of vector elements for single instruction multiple data processing 
US5968198A (en)  19960816  19991019  Ericsson, Inc.  Decoder utilizing soft information output to minimize error rates 
US6002881A (en)  19970610  19991214  Arm Limited  Coprocessor data access control 
US6073250A (en)  19971106  20000606  Luby; Michael G.  Loss resilient decoding technique 
US6195777B1 (en)  19971106  20010227  Compaq Computer Corporation  Loss resilient code with double heavy tailed series of redundant layers 
US6247158B1 (en)  19981130  20010612  Itt Manufacturing Enterprises, Inc.  Digital broadcasting system and method 
US6298438B1 (en)  19961202  20011002  Advanced Micro Devices, Inc.  System and method for conditional moving an operand from a source register to destination register 
US20020002695A1 (en) *  20000602  20020103  Frank Kschischang  Method and system for decoding 
US6339834B1 (en)  19980528  20020115  Her Majesty The Queen In Right Of Canada, As Represented By The Minister Of Industry Through The Communication Research Centre  Interleaving with golden section increments 
US6397240B1 (en)  19990218  20020528  Agere Systems Guardian Corp.  Programmable accelerator for a programmable processor system 
US6438180B1 (en)  19970509  20020820  Carnegie Mellon University  Soft and hard sequence detection in ISI memory channels 
US6473010B1 (en)  20000404  20021029  Marvell International, Ltd.  Method and apparatus for determining error correction code failure rate for iterative decoding algorithms 
US6539367B1 (en) *  20000526  20030325  Agere Systems Inc.  Methods and apparatus for decoding of general codes on probability dependency graphs 
US20030065989A1 (en) *  20011001  20030403  Yedida Jonathan S.  Evaluating and optimizing errorcorrecting codes using projective analysis 
US6633856B2 (en)  20010615  20031014  Flarion Technologies, Inc.  Methods and apparatus for decoding LDPC codes 
US20040034828A1 (en)  20020815  20040219  Texas Instruments Incorporated  Hardwareefficient low density parity check code for digital communications 
US6718504B1 (en)  20020605  20040406  Arc International  Method and apparatus for implementing a data processor adapted for turbo decoding 
US6731700B1 (en)  20010104  20040504  Comsys Communication & Signal Processing Ltd.  Soft decision output generator 
US6754804B1 (en)  20001229  20040622  Mips Technologies, Inc.  Coprocessor interface transferring multiple instructions simultaneously along with issue path designation and/or issue order designation for the instructions 
Family Cites Families (6)
Publication number  Priority date  Publication date  Assignee  Title 

JPH04152455A (en) *  19901016  19920526  Nec Corp  Method and device for searching data 
US5337002A (en) *  19910301  19940809  Mercer John E  Locator device for continuously locating a dipole magnetic field transmitter and its method of operation 
FR2799592B1 (en)  19991012  20030926  Thomson Csf  Method for construction and simple and systematic coding codes ldpc 
JP2001352257A (en) *  20000608  20011221  Sony Corp  Decoder and decoding method 
JP4389373B2 (en) *  20001011  20091224  ソニー株式会社  Decoder for iterative decoding the binary cyclic code 
US6938196B2 (en) *  20010615  20050830  Flarion Technologies, Inc.  Node processors for use in parity check decoders 

2002
 20020404 US US10/117,264 patent/US6938196B2/en not_active Expired  Fee Related
 20021007 EP EP02800936A patent/EP1442527B1/en active Active
 20021007 KR KR1020097024971A patent/KR101093313B1/en not_active IP Right Cessation
 20021007 WO PCT/US2002/031971 patent/WO2003032499A1/en active Application Filing
 20021007 ES ES02800936T patent/ES2356767T3/en active Active
 20021007 KR KR1020047005278A patent/KR100958234B1/en not_active IP Right Cessation
 20021007 EP EP10013892A patent/EP2302803A1/en not_active Withdrawn
 20021007 DE DE60238934A patent/DE60238934D1/en active Active
 20021007 KR KR1020107026785A patent/KR20110005897A/en not_active Application Discontinuation
 20021007 JP JP2003535339A patent/JP4221503B2/en not_active Expired  Fee Related
 20021007 AT AT02800936T patent/AT495581T/en not_active IP Right Cessation
 20021008 TW TW091123226A patent/TW569548B/en not_active IP Right Cessation

2008
 20080804 JP JP2008200437A patent/JP2009010970A/en active Pending

2012
 20120727 JP JP2012166960A patent/JP5579798B2/en not_active Expired  Fee Related

2014
 20140519 JP JP2014103669A patent/JP2014180034A/en not_active Ceased

2015
 20150611 JP JP2015118386A patent/JP2015216645A/en active Pending
Patent Citations (37)
Publication number  Priority date  Publication date  Assignee  Title 

US3542756A (en)  19680207  19701124  Codex Corp  Error correcting 
US3665396A (en)  19681011  19720523  Codex Corp  Sequential decoding 
US4295218A (en)  19790625  19811013  Regents Of The University Of California  Errorcorrecting coding system 
US5293489A (en)  19850124  19940308  Nec Corporation  Circuit arrangement capable of centralizing control of a switching network 
US5271042A (en)  19891013  19931214  Motorola, Inc.  Soft decision decoding with channel equalization 
US5157671A (en)  19900529  19921020  Space Systems/Loral, Inc.  Semisystolic architecture for decoding errorcorrecting codes 
US5313609A (en)  19910523  19940517  International Business Machines Corporation  Optimum writeback strategy for directorybased cache coherence protocols 
US5396518A (en)  19930505  19950307  Gi Corporation  Apparatus and method for communicating digital data using trellis coding with punctured convolutional codes 
US5457704A (en)  19930521  19951010  At&T Ipm Corp.  Post processing method and apparatus for symbol reliability generation 
US5526501A (en)  19930812  19960611  Hughes Aircraft Company  Variable accuracy indirect addressing scheme for SIMD multiprocessors and apparatus implementing same 
US5615298A (en)  19940314  19970325  Lucent Technologies Inc.  Excitation signal synthesis during frame erasure or packet loss 
US5860085A (en)  19940801  19990112  Cypress Semiconductor Corporation  Instruction set for a content addressable memory array with read/write circuits and an interface register logic block 
US5671221A (en)  19950614  19970923  Sharp Microelectronics Technology, Inc.  Receiving method and apparatus for use in a spreadspectrum communication system 
US5867538A (en)  19950815  19990202  Hughes Electronics Corporation  Computational simplified detection of digitally modulated radio signals providing a detection of probability for each symbol 
US5968198A (en)  19960816  19991019  Ericsson, Inc.  Decoder utilizing soft information output to minimize error rates 
US5892962A (en)  19961112  19990406  Lucent Technologies Inc.  FPGAbased processor 
US6298438B1 (en)  19961202  20011002  Advanced Micro Devices, Inc.  System and method for conditional moving an operand from a source register to destination register 
US6438180B1 (en)  19970509  20020820  Carnegie Mellon University  Soft and hard sequence detection in ISI memory channels 
US6002881A (en)  19970610  19991214  Arm Limited  Coprocessor data access control 
US5864703A (en)  19971009  19990126  Mips Technologies, Inc.  Method for providing extended precision in SIMD vector arithmetic operations 
US6266758B1 (en)  19971009  20010724  Mips Technologies, Inc.  Alignment and ordering of vector elements for single instruction multiple data processing 
US5933650A (en)  19971009  19990803  Mips Technologies, Inc.  Alignment and ordering of vector elements for single instruction multiple data processing 
US6073250A (en)  19971106  20000606  Luby; Michael G.  Loss resilient decoding technique 
US6195777B1 (en)  19971106  20010227  Compaq Computer Corporation  Loss resilient code with double heavy tailed series of redundant layers 
US6339834B1 (en)  19980528  20020115  Her Majesty The Queen In Right Of Canada, As Represented By The Minister Of Industry Through The Communication Research Centre  Interleaving with golden section increments 
US6484284B2 (en)  19981130  20021119  Itt Manufacturing Enterprises, Inc.  Digital broadcasting system and method 
US6247158B1 (en)  19981130  20010612  Itt Manufacturing Enterprises, Inc.  Digital broadcasting system and method 
US6397240B1 (en)  19990218  20020528  Agere Systems Guardian Corp.  Programmable accelerator for a programmable processor system 
US6473010B1 (en)  20000404  20021029  Marvell International, Ltd.  Method and apparatus for determining error correction code failure rate for iterative decoding algorithms 
US6539367B1 (en) *  20000526  20030325  Agere Systems Inc.  Methods and apparatus for decoding of general codes on probability dependency graphs 
US20020002695A1 (en) *  20000602  20020103  Frank Kschischang  Method and system for decoding 
US6754804B1 (en)  20001229  20040622  Mips Technologies, Inc.  Coprocessor interface transferring multiple instructions simultaneously along with issue path designation and/or issue order designation for the instructions 
US6731700B1 (en)  20010104  20040504  Comsys Communication & Signal Processing Ltd.  Soft decision output generator 
US6633856B2 (en)  20010615  20031014  Flarion Technologies, Inc.  Methods and apparatus for decoding LDPC codes 
US20030065989A1 (en) *  20011001  20030403  Yedida Jonathan S.  Evaluating and optimizing errorcorrecting codes using projective analysis 
US6718504B1 (en)  20020605  20040406  Arc International  Method and apparatus for implementing a data processor adapted for turbo decoding 
US20040034828A1 (en)  20020815  20040219  Texas Instruments Incorporated  Hardwareefficient low density parity check code for digital communications 
NonPatent Citations (19)
Title 

Fossorier, M.P.C.; Mihaljevic, M.; Imai, H.; Reduced complexity iterative decoding of lowdensity parity check codes based on belief propagation; Communications, IEEE Transactions on ,vol.: 47 , Issue: 5 , May 1999; pp.: 673680. * 
Kurkoski, B.M.; Siegel, P.H.; Wolf, J.K.; Joint messagepassing decoding of LDPC codes and partialresponse channels; Information Theory, IEEE Transactions on , vol.: 48 , Issue: 6, Jun. 2002, pp.: 14101422. * 
M. Luby, M. Mitzenmacher, A. Shokrollah, D. Spielman; Analysis of low density codes and improved designs using irregular graphs; Proceedings of the thirtieth annual ACM symposium on Theory of computing; May 1998; pp.: 249258. * 
Michael G. Luby, Michael Mitzenmacher, M. Amin Shokrollahi, Daniel A. Spielman, Volker Stemann; Practical lossresilient codes; Proceedings of the twentyninth annual ACM symposium on Theory of computing; May 1997; pp.: 150159. * 
Mohammad M. Mansour, Naresh R. Shanbhag, Session 11: Lowpower VLSI decoder architectures for LDPC codes, Proceedings of the 2002 international symposium on Low power electronics and design Aug. 2002, pp.: 284289. 
NN77112415. Digital Encoding of Wide Range Dynamic Analog Signals, IBM Tech. Disclosure Bulletin, Nov. 1, 1997, vol. No. 20; Issue No. 6; pp. 24152417, whole document. 
NN9210335. Hierarchical Coded Modulation of Data with Fast Decaying Probability Distributions, IBM Tech. Disclosure Bulletin, Oct. 1992, vol. No. 35; Issue No. 5; pp. 335336, whole document. 
Paranchych et al. Performance of a digital symbol synchronizer in cochannel interference and noise, IEEE Transactions on Communications, pp.: 19451954; Nov. 2000, whole document. 
R. Blahut, "Theory and Practice of Error Control Codes", Library of Congress Cataloging in Publication Data, pp4749, (May 1984). 
Richardson et al. The capacity of lowdensity paritycheck codes under messagepassing Decoding, IEEE Transactions on Information Theory; pp.: 599618, Feb. 2001, (same inventor) whole document. 
Saied Hemati, Amir H. Banihashemi, VLSI circuits: Iterative decoding in analog CMOS, Proceedings of the 13<SUP>th </SUP>ACM Great Lakes Symposium on VLSI Apr. 2003, pp.: 1520. 
Sorokine, V. et al. Innovative coding scheme for spreadspectrum communications, The Ninth IEEE International Symposium on Indoor and Mobile Radio Communications, pp.: 14911495, vol. 3; Sep. 1998, whole document. 
T. Moors and M. Veeraraghavan, "Preliminary specification and explanation of Zing: An endtoend protocol for transporting bulk data over optical circuits", pp. 155 (May 2001). 
T. Richardson and R. Urbanke, "An Introduction to the Analysis of Iterative Coding Systems", pp. 136. 
T. Richardson and R. Urbanke, "The Capacity of LowDensity ParityCheck Codes under MessagePassing Decoding", pp. 144 (Mar. 2001). 
T. Richardson, A. Shokrollahi, R. Urbanke, "Design of CapacityApproaching Irregular LowDensity ParityCheck Codes", pp. 143 (Mar. 2001). 
W. W. Peterson and E.J. Weldon, Jr., "ErrorCorrecting Codes", Second Edition, The Massachusetts Institute of Technology, pp212213, 261263, 263, (1986). 
Weiss, Y.; Freeman, W.T.; On the optimality of solutions of the maxproduct beliefpropagation algorithm in arbitary graphs; Information Theory, IEEE Transations on , vol.: 47, Issue: 2, Feb. 2001; pp.: 736744. * 
Wiberg, Niclas; Codes and Decoding on General Graphs; PhD dissertation No. 440; Dept. of Electrical Engineering; Linkoping University, Sweden; Oct. 30, 1996; pp. ix, 196. * 
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Publication number  Priority date  Publication date  Assignee  Title 

US7673223B2 (en) *  20010615  20100302  Qualcomm Incorporated  Node processors for use in parity check decoders 
US20060242093A1 (en) *  20010615  20061026  Tom Richardson  Methods and apparatus for decoding LDPC codes 
US7552097B2 (en) *  20010615  20090623  Qualcomm Incorporated  Methods and apparatus for decoding LDPC codes 
US20050257124A1 (en) *  20010615  20051117  Tom Richardson  Node processors for use in parity check decoders 
US20050262421A1 (en) *  20020531  20051124  Tran Hau T  Efficient front end memory arrangement to support parallel bit node and check node processing in LDPC (Low Density Parity Check) decoders 
US7587659B2 (en) *  20020531  20090908  Broadcom Corporation  Efficient front end memory arrangement to support parallel bit node and check node processing in LDPC (Low Density Parity Check) decoders 
US7203887B2 (en) *  20020703  20070410  The Directtv Group, Inc.  Method and system for routing in low density parity check (LDPC) decoders 
US20090187811A1 (en) *  20020703  20090723  The Directv Group, Inc.  Method and system for providing low density parity check (ldpc) encoding 
US20050166133A1 (en) *  20020703  20050728  Hughes Electronics Corporation  Method and system for decoding low density parity check (LDPC) codes 
US20040054960A1 (en) *  20020703  20040318  Mustafa Eroz  Method and system for providing low density parity check (LDPC) encoding 
US7577207B2 (en)  20020703  20090818  Dtvg Licensing, Inc.  Bit labeling for amplitude phase shift constellation used with low density parity check (LDPC) codes 
US7954036B2 (en) *  20020703  20110531  Dtvg Licensing, Inc.  Method and system for providing low density parity check (LDPC) encoding 
US20040153960A1 (en) *  20020703  20040805  Mustafa Eroz  Method and system for routing in low density parity check (LDPC) decoders 
US8145980B2 (en) *  20020703  20120327  Dtvg Licensing, Inc.  Method and system for decoding low density parity check (LDPC) codes 
US8102947B2 (en)  20020703  20120124  Dtvg Licensing, Inc.  Bit labeling for amplitude phase shift constellation used with low density parity check (LDPC) codes 
US7424662B2 (en)  20020703  20080909  The Directv Group, Inc.  Method and system for providing low density parity check (LDPC) encoding 
US7398455B2 (en) *  20020703  20080708  The Directv Group, Inc.  Method and system for decoding low density parity check (LDPC) codes 
US7962830B2 (en) *  20020703  20110614  Dtvg Licensing, Inc.  Method and system for routing in low density parity check (LDPC) decoders 
US20080065947A1 (en) *  20020703  20080313  The Directv Group, Inc.  Method and system for decoding low density parity check (ldpc) codes 
US20070113142A1 (en) *  20020703  20070517  Mustafa Eroz  Method and system for providing low density parity check (LDPC) encoding 
US20070168834A1 (en) *  20020703  20070719  Mustafa Eroz  Method and system for routing in low density parity check (LDPC) decoders 
US20050271160A1 (en) *  20020703  20051208  Mustafa Eroz  Bit labeling for amplitude phase shift constellation used with low density parity check (LDPC) codes 
US7191378B2 (en)  20020703  20070313  The Directv Group, Inc.  Method and system for providing low density parity check (LDPC) encoding 
US9473266B1 (en) *  20020710  20161018  Seagate Technology Llc  Scheduling strategies for iterative decoders 
US10033408B2 (en)  20020710  20180724  Seagate Technology Llc  Scheduling strategies for iterative decoders 
US7864869B2 (en)  20020726  20110104  Dtvg Licensing, Inc.  Satellite communication system utilizing low density parity check codes 
US20080082895A1 (en) *  20020726  20080403  The Directv Group, Inc.  Method and system for generating low density parity check codes 
US20050063484A1 (en) *  20020726  20050324  Mustafa Eroz  Satellite communincation system utilizing low density parity check codes 
US8095854B2 (en) *  20020726  20120110  Dtvg Licensing, Inc.  Method and system for generating low density parity check codes 
US20110055655A1 (en) *  20020815  20110303  Texas Instruments Incorporated  HardwareEfficient Low Density Parity Check Code for Digital Communications 
US20070011568A1 (en) *  20020815  20070111  Texas Instruments Incorporated  HardwareEfficient Low Density Parity Check Code for Digital Communications 
US7669109B2 (en) *  20020815  20100223  Texas Instruments Incorporated  Hardwareefficient low density parity check code for digital communications 
US7103819B2 (en) *  20020827  20060905  Sony Corporation  Decoding device and decoding method 
US20050010846A1 (en) *  20020827  20050113  Atsushi Kikuchi  Decoding device and decoding method 
US7178081B2 (en) *  20021224  20070213  Electronics And Telecommunications Research Institute  Simplified messagepassing decoder for lowdensity paritycheck codes 
US20040123230A1 (en) *  20021224  20040624  Lee SangHyun  Simplified messagepassing decoder for lowdensity paritycheck codes 
US20080028272A1 (en) *  20030226  20080131  Tom Richardson  Method and apparatus for performing lowdensity paritycheck (ldpc) code operations using a multilevel permutation 
US7966542B2 (en)  20030226  20110621  Qualcomm Incorporated  Method and apparatus for performing lowdensity paritycheck (LDPC) code operations using a multilevel permutation 
US7318186B2 (en) *  20030513  20080108  Sony Corporation  Decoding method, decoding apparatus, and program to decode low density parity check codes 
US20050240853A1 (en) *  20030513  20051027  Takashi Yokokawa  Decoding device, decoding method, and program 
US7299397B2 (en) *  20030513  20071120  Sony Corporation  Decoding apparatus, decoding method, and program to decode low density parity check codes 
USRE44420E1 (en)  20030513  20130806  Sony Corporation  Decoding apparatus, decoding method, and program to decode low density parity check codes 
US20050278604A1 (en) *  20030513  20051215  Takashi Yokokawa  Decoding method, decoding device, and program 
US20050081128A1 (en) *  20031010  20050414  Jones Christopher R.  Decoding low density parity codes 
US7340671B2 (en)  20031010  20080304  Regents Of The University Of California  Decoding low density parity codes 
US20050204272A1 (en) *  20040203  20050915  Hiroyuki Yamagishi  Decoding apparatus and method and information processing apparatus and method 
US7676734B2 (en) *  20040203  20100309  Sony Corporation  Decoding apparatus and method and information processing apparatus and method 
US20050229087A1 (en) *  20040413  20051013  Sunghwan Kim  Decoding apparatus for lowdensity paritycheck codes using sequential decoding, and method thereof 
US7590914B2 (en) *  20040413  20090915  Electronics And Telecommunications Research Institute  Decoding apparatus for lowdensity paritycheck codes using sequential decoding, and method thereof 
USRE44421E1 (en) *  20040413  20130806  Electronics And Telecommunications Research Institute  Decoding apparatus for lowdensity paritycheck codes using sequential decoding, and method thereof 
US7631241B2 (en) *  20040521  20091208  Samsung Electronics Co., Ltd.  Apparatus and method for decoding low density parity check codes 
US20050262420A1 (en) *  20040521  20051124  Samsung Electronics Co., Ltd.  Apparatus and method for decoding low density parity check codes 
US20050268204A1 (en) *  20040531  20051201  Kabushiki Kaisha Toshiba  Decoding apparatus and decoding circuit 
US8683289B2 (en)  20040721  20140325  Qualcomm Incorporated  LDPC decoding methods and apparatus 
US8595569B2 (en)  20040721  20131126  Qualcomm Incorporated  LCPC decoding methods and apparatus 
US7376885B2 (en) *  20040802  20080520  Qualcomm Incorporated  Memory efficient LDPC decoding methods and apparatus 
US20070168832A1 (en) *  20040802  20070719  Tom Richardson  Memory efficient LDPC decoding methods and apparatus 
US20060026486A1 (en) *  20040802  20060202  Tom Richardson  Memory efficient LDPC decoding methods and apparatus 
US7127659B2 (en) *  20040802  20061024  Qualcomm Incorporated  Memory efficient LDPC decoding methods and apparatus 
US8392793B2 (en)  20040813  20130305  Dtvg Licensing, Inc.  Code design and implementation improvements for low density parity check codes for multipleinput multipleoutput channels 
US20080104474A1 (en) *  20041001  20080501  Joseph J Laks  Low Density Parity Check (Ldpc) Decoder 
US20060085720A1 (en) *  20041004  20060420  Hau Thien Tran  Message passing memory and barrel shifter arrangement in LDPC (Low Density Parity Check) decoder supporting multiple LDPC codes 
US20060156181A1 (en) *  20041027  20060713  Samsung Electronics Co., Ltd.  Method for puncturing an LDPC channel code 
US7657824B2 (en) *  20041027  20100202  Samsung Electronics Co., Ltd.  Method for puncturing an LDPC channel code 
US20060117240A1 (en) *  20041110  20060601  Vladimir Novichkov  Hierarchical design and layout optimizations for high throughput parallel LDPC decoders 
US7617432B2 (en) *  20041110  20091110  Qualcomm Incorporated  Hierarchical design and layout optimizations for high throughput parallel LDPC decoders 
US7441178B2 (en) *  20050224  20081021  Keyeye Communications  Low complexity decoding of low density parity check codes 
US20110078548A1 (en) *  20050224  20110331  Weizhuang Xin  Low complexity decoding of low density parity check codes 
US8219897B2 (en)  20050224  20120710  Vintomie Networks B.V., Llc  Low complexity decoding of low density parity check codes 
US20060190797A1 (en) *  20050224  20060824  Weizhuang Xin  Low complexity decoding of low density parity check codes 
US7856593B2 (en)  20050224  20101221  Weizhuang Xin  Low complexity decoding of low density parity check codes 
US8095863B2 (en)  20050224  20120110  Vintomie Networks B.V., Llc  Low complexity decoding of low density parity check codes 
US20090217128A1 (en) *  20050224  20090827  Weizhuang Xin  Low complexity decoding of low density parity check codes 
US8495119B2 (en)  20050317  20130723  Qualcomm Incorporated  Efficient check node message transform approximation for LDPC decoder 
US20090177869A1 (en) *  20050317  20090709  Qualcomm Incorporated  Efficient check node message transform approximation for ldpc decoder 
US8140930B1 (en) *  20050513  20120320  Nec Corporation  Encoder and decoder by LDPC coding 
US8006162B2 (en) *  20050516  20110823  Samsung Electronics Co., Ltd.  Method for padding and puncturing low density parity check code 
US20070011567A1 (en) *  20050516  20070111  Samsung Electronics Co., Ltd.  Method for padding and puncturing low density parity check code 
US20070089019A1 (en) *  20051018  20070419  Nokia Corporation  Error correction decoder, method and computer program product for block serial pipelined layered decoding of structured lowdensity paritycheck (LDPC) codes, including calculating checktovariable messages 
US20070089016A1 (en) *  20051018  20070419  Nokia Corporation  Block serial pipelined layered decoding architecture for structured lowdensity paritycheck (LDPC) codes 
US20070089017A1 (en) *  20051018  20070419  Nokia Corporation  Error correction decoder, method and computer program product for block serial pipelined layered decoding of structured lowdensity paritycheck (LDPC) codes with reduced memory requirements 
US7818649B1 (en) *  20051130  20101019  Aquantia Corporation  Efficient message passing scheme of iterative error correcting decoders 
US20070150789A1 (en) *  20051201  20070628  Electronics And Telecommunications Research Institute  LDPC decoding apparatus and method using typeclassified index 
US8122315B2 (en) *  20051201  20120221  Electronics And Telecommunications Research Institute  LDPC decoding apparatus and method using typeclassified index 
US20070127387A1 (en) *  20051205  20070607  Lee Tak K  Partialparallel implementation of LDPC (low density parity check) decoders 
US7661055B2 (en) *  20051205  20100209  Broadcom Corporation  Partialparallel implementation of LDPC (Low Density Parity Check) decoders 
US20070204197A1 (en) *  20051220  20070830  Takashi Yokokawa  Decoding device, control method, and program 
US7937648B2 (en)  20051220  20110503  Sony Corporation  Decoding device, control method, and program 
US7617433B2 (en) *  20060103  20091110  Broadcom Corporation  Implementation of LDPC (low density parity check) decoder by sweeping through submatrices 
US20070157061A1 (en) *  20060103  20070705  Broadcom Corporation, A California Corporation  Submatrixbased implementation of LDPC (Low Density Parity Check ) decoder 
US20070157062A1 (en) *  20060103  20070705  Broadcom Corporation, A California Corporation  Implementation of LDPC (Low Density Parity Check) decoder by sweeping through submatrices 
US7530002B2 (en) *  20060103  20090505  Broadcom Corporation  Submatrixbased implementation of LDPC (Low Density Parity Check) decoder 
US20070283218A1 (en) *  20060419  20071206  Gopalakrishnan Subramanyam H  Low density parity check code decoder 
US7941737B2 (en) *  20060419  20110510  Tata Consultancy Services Limited  Low density parity check code decoder 
US7793201B1 (en)  20060511  20100907  Seagate Technology Llc  Bit error detector for iterative ECC decoder 
US7631250B2 (en)  20060519  20091208  National Chiao Tung University  Method and apparatus for selfcompensation on beliefpropagation algorithm 
US20070283213A1 (en) *  20060519  20071206  National Chiao Tung University  Method and apparatus for selfcompensation on beliefpropagation algorithm 
US20080109698A1 (en) *  20060725  20080508  Legend Silicon  Hybrid minsum decoding apparatus with low bit resolution for ldpc code 
US20080052594A1 (en) *  20060728  20080228  Yedidia Jonathan S  Method and system for replica groupshuffled iterative decoding of quasicyclic lowdensity parity check codes 
US8453030B2 (en)  20061026  20130528  Qualcomm Incorporated  Coding schemes for wireless communication transmissions 
US20100023834A1 (en) *  20061026  20100128  Qualcomm Incorproated  Coding schemes for wireless communication transmissions 
US8892979B2 (en)  20061026  20141118  Qualcomm Incorporated  Coding schemes for wireless communication transmissions 
US20080178066A1 (en) *  20070118  20080724  Samsung Electronics Co., Ltd.  Method and apparatus for receiving data in communication system 
US8359522B2 (en)  20070501  20130122  Texas A&M University System  Low density parity check decoder for regular LDPC codes 
US8656250B2 (en)  20070501  20140218  Texas A&M University System  Low density parity check decoder for regular LDPC codes 
US10141950B2 (en)  20070501  20181127  The Texas A&M University System  Low density parity check decoder 
US20080276156A1 (en) *  20070501  20081106  Texas A&M University System  Low density parity check decoder for regular ldpc codes 
US8555140B2 (en)  20070501  20131008  The Texas A&M University System  Low density parity check decoder for irregular LDPC codes 
US8418023B2 (en)  20070501  20130409  The Texas A&M University System  Low density parity check decoder for irregular LDPC codes 
US20080301521A1 (en) *  20070501  20081204  Texas A&M University System  Low density parity check decoder for irregular ldpc codes 
US9112530B2 (en)  20070501  20150818  The Texas A&M University System  Low density parity check decoder 
US8984133B2 (en)  20070619  20150317  The Invention Science Fund I, Llc  Providing treatmentindicative feedback dependent on putative content treatment 
US8682982B2 (en)  20070619  20140325  The Invention Science Fund I, Llc  Preliminary destinationdependent evaluation of message content 
US20090037799A1 (en) *  20070731  20090205  ChihHao Liu  Operating method applied to low density parity check (ldpc) decoder and circuit thereof 
US8108762B2 (en)  20070731  20120131  National Chiao Tung University  Operating method and circuit for low density parity check (LDPC) decoder 
US8082225B2 (en)  20070831  20111220  The Invention Science Fund I, Llc  Using destinationdependent criteria to guide data transmission decisions 
US8065404B2 (en)  20070831  20111122  The Invention Science Fund I, Llc  Layering destinationdependent content handling guidance 
US9374242B2 (en)  20071108  20160621  Invention Science Fund I, Llc  Using evaluations of tentative message content 
US7930389B2 (en)  20071120  20110419  The Invention Science Fund I, Llc  Adaptive filtering of annotated messages or the like 
US20100269019A1 (en) *  20071126  20101021  Sony Corporation  Data processing apparatus and data processing method 
TWI410055B (en) *  20071126  20130921  Sony Corp  
US8499214B2 (en) *  20071126  20130730  Sony Corporation  Data processing apparatus and data processing method 
US7719442B2 (en)  20071207  20100518  National Chiao Tung University  Multimode multiparallelism data exchange method and device thereof 
US20090146849A1 (en) *  20071207  20090611  ChihHao Liu  Multimode multiparallelism data exchange method and device thereof 
US8266493B1 (en) *  20080109  20120911  L3 Communications, Corp.  Lowdensity parity check decoding using combined check node and variable node 
US8255758B2 (en)  20080121  20120828  Apple Inc.  Decoding of error correction code using partial bit inversion 
US20090187803A1 (en) *  20080121  20090723  Anobit Technologies Ltd.  Decoding of error correction code using partial bit inversion 
US8327242B1 (en)  20080410  20121204  Apple Inc.  Highperformance ECC decoder 
US8166364B2 (en) *  20080804  20120424  Seagate Technology Llc  Low density parity check decoder using multiple variable node degree distribution codes 
US20100031115A1 (en) *  20080804  20100204  Ara Patapoutian  Low density parity check decoder using multiple variable node degree distribution codes 
WO2010101944A1 (en) *  20090302  20100910  David Reynolds  Belief propagation processor 
CN102439853A (en) *  20090302  20120502  三菱电机研究实验室股份有限公司  Belief propagation processor 
US8458114B2 (en)  20090302  20130604  Analog Devices, Inc.  Analog computation using numerical representations with uncertainty 
US8799346B2 (en)  20090302  20140805  Mitsubishi Electric Research Laboratories, Inc.  Belief propagation processor 
US20100223225A1 (en) *  20090302  20100902  Lyric Semiconductor, Inc.  Analog computation using numerical representations with uncertainty 
CN102439853B (en) *  20090302  20141224  三菱电机研究实验室股份有限公司  Belief propagation processor 
US8429498B1 (en)  20090325  20130423  Apple Inc.  Dual ECC decoder 
US20100332955A1 (en) *  20090630  20101230  Anobit Technologies Ltd.  Chien search using multiple basis representation 
US8453038B2 (en)  20090630  20130528  Apple Inc.  Chien search using multiple basis representation 
US8601352B1 (en)  20090730  20131203  Apple Inc.  Efficient LDPC codes 
US8972831B2 (en)  20100111  20150303  Analog Devices, Inc.  Belief propagation processor 
US8650464B1 (en) *  20100907  20140211  Applied Micro Circuits Corporation  Symmetric diagonal interleaving and encoding/decoding circuit and method 
US8879640B2 (en)  20110215  20141104  Hong Kong Applied Science and Technology Research Institute Company Limited  Memory efficient implementation of LDPC decoder 
US20150178151A1 (en) *  20131220  20150625  Sandisk Technologies Inc.  Data storage device decoder and method of operation 
US9553608B2 (en) *  20131220  20170124  Sandisk Technologies Llc  Data storage device decoder and method of operation 
US9276610B2 (en) *  20140127  20160301  Tensorcom, Inc.  Method and apparatus of a fullypipelined layered LDPC decoder 
US9391817B2 (en)  20140324  20160712  Tensorcom, Inc.  Method and apparatus of an architecture to switch equalization based on signal delay spread 
US10084481B2 (en)  20141218  20180925  Apple Inc.  GLDPC soft decoding with hard decision inputs 
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US20030023917A1 (en)  20030130 
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JP2009010970A (en)  20090115 
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WO2003032499A1 (en)  20030417 
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