MX2009001546A - Metodo para corregir errores de mensaje con el uso de la prueba de redundancia ciclica. - Google Patents

Metodo para corregir errores de mensaje con el uso de la prueba de redundancia ciclica.

Info

Publication number
MX2009001546A
MX2009001546A MX2009001546A MX2009001546A MX2009001546A MX 2009001546 A MX2009001546 A MX 2009001546A MX 2009001546 A MX2009001546 A MX 2009001546A MX 2009001546 A MX2009001546 A MX 2009001546A MX 2009001546 A MX2009001546 A MX 2009001546A
Authority
MX
Mexico
Prior art keywords
crc
parity
check matrix
message
errors
Prior art date
Application number
MX2009001546A
Other languages
English (en)
Inventor
Quentin Spencer
Original Assignee
Aclara Power Line Systems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Aclara Power Line Systems Inc filed Critical Aclara Power Line Systems Inc
Publication of MX2009001546A publication Critical patent/MX2009001546A/es

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/09—Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1105—Decoding
    • H03M13/1111—Soft-decision decoding, e.g. by means of message passing or belief propagation algorithms

Landscapes

  • Physics & Mathematics (AREA)
  • Probability & Statistics with Applications (AREA)
  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Error Detection And Correction (AREA)
  • Detection And Prevention Of Errors In Transmission (AREA)
  • Detection And Correction Of Errors (AREA)

Abstract

Un método para corregir errores en un mensaje transmitido sobre un canal de comunicación digital, donde el mensaje se codificó utilizando una CRC para propósitos de detección de errores. La representación matriz de prueba de paridad de la CRC se calcula para cualquier mensaje de extensión fija, y esa matriz de prueba de paridad se combina con la matriz de prueba de paridad para cualquier código de corrección de errores que se utilizó en conjunto con la CRC. La matriz de prueba de paridad combinada se extiende al expandir algoritmos para permitirle funcionar correctamente bajo un descodificador de paso de mensajes (MPD). Los mensajes recibidos se descodifican con el uso del descodificador de paso de mensajes, haciendo posible la corrección de más errores en lugar de la CRC descodificada de forma convencional.
MX2009001546A 2006-08-11 2007-08-09 Metodo para corregir errores de mensaje con el uso de la prueba de redundancia ciclica. MX2009001546A (es)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US83734906P 2006-08-11 2006-08-11
PCT/US2007/075547 WO2008021930A2 (en) 2006-08-11 2007-08-09 Method of correcting message errors using cyclic redundancy checks

Publications (1)

Publication Number Publication Date
MX2009001546A true MX2009001546A (es) 2009-12-15

Family

ID=39082948

Family Applications (1)

Application Number Title Priority Date Filing Date
MX2009001546A MX2009001546A (es) 2006-08-11 2007-08-09 Metodo para corregir errores de mensaje con el uso de la prueba de redundancia ciclica.

Country Status (5)

Country Link
US (2) US7831884B2 (es)
EP (1) EP2062364A2 (es)
CA (1) CA2661264C (es)
MX (1) MX2009001546A (es)
WO (1) WO2008021930A2 (es)

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WO2009004248A1 (fr) * 2007-06-19 2009-01-08 France Telecom Methode a base de codes correcteurs d'erreurs applicable a un flux de donnees multimedia a debit variable
JP5466953B2 (ja) * 2008-02-08 2014-04-09 富士通株式会社 バックアップ方法及びディスクアレイシステム
GB2503128B8 (en) * 2008-10-09 2014-03-12 Sonicwall Inc Computer networks
CN101795175B (zh) * 2010-02-23 2014-03-19 中兴通讯股份有限公司 数据的校验处理方法及装置
KR101854954B1 (ko) 2011-07-29 2018-05-04 샌디스크 테크놀로지스 엘엘씨 치환 소행렬의 합을 사용하는 체크섬
WO2013078105A1 (en) 2011-11-22 2013-05-30 Aclara Power-Line Systems Inc. Metrology timekeeping systems and methods
US8775897B2 (en) * 2012-05-07 2014-07-08 Lsi Corporation Data processing system with failure recovery
CN102801501B (zh) * 2012-08-21 2015-03-11 中国电子科技集团公司第三十六研究所 一种bch缩短码的编码参数的识别方法
US9577675B1 (en) * 2013-12-03 2017-02-21 Marvell International Ltd. System and method for encoding user data with low-density parity-check codes with flexible redundant parity check matrix structures
US9906270B2 (en) * 2015-03-26 2018-02-27 Aclara Technologies Llc Concurrent outbound communications in a TWACS
AU2016288726A1 (en) * 2015-07-02 2018-02-22 Nextivity, Inc. Method and system for maximizing channel bandwidth while employing error control coding
US9747790B1 (en) * 2016-02-12 2017-08-29 King Fahd University Of Petroleum And Minerals Method, device, and computer-readable medium for correcting at least one error in readings of electricity meters
CN108400787B (zh) * 2018-03-07 2021-04-13 中山大学 一种基于bch编码的并行fir滤波器容错方法
CN114124111A (zh) * 2020-09-01 2022-03-01 华为技术有限公司 一种编码方法及装置
CN115037414B (zh) * 2022-05-31 2023-12-22 江苏屹信航天科技有限公司 基于crc的纠错解码的方法、装置、终端

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DE69317766T2 (de) * 1993-06-10 1998-07-30 Bull Hn Information Syst Fehlerkorrekturgerät für digitale Daten zur Korrektur von Einfachfehlern (sec), von Doppelfehlern (ded) und Vielfacheinzelbytefehlern (sbd) und zur Korrektur von Einzelbytefehlern ungerader Anzahl (odd sbc)
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US7143336B1 (en) * 2001-08-15 2006-11-28 Regents Of The Univerisity Of Minnesota Decoding parallel concatenated parity-check code
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KR100684168B1 (ko) * 2004-12-09 2007-02-20 한국전자통신연구원 최적붙임방법을 이용한 다중 부호율 ｌｄｐｃ 부호의디자인 방법

Also Published As

Publication number Publication date
CA2661264A1 (en) 2008-02-21
US20080040644A1 (en) 2008-02-14
US7831884B2 (en) 2010-11-09
EP2062364A2 (en) 2009-05-27
WO2008021930A3 (en) 2008-10-16
CA2661264C (en) 2014-06-10
WO2008021930A2 (en) 2008-02-21
US20090259917A1 (en) 2009-10-15

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