CN106576087B - 带内嵌时钟的正交差分向量信令码 - Google Patents

带内嵌时钟的正交差分向量信令码 Download PDF

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CN106576087B
CN106576087B CN201580041726.2A CN201580041726A CN106576087B CN 106576087 B CN106576087 B CN 106576087B CN 201580041726 A CN201580041726 A CN 201580041726A CN 106576087 B CN106576087 B CN 106576087B
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CN106576087A (zh
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布赖恩·霍尔登
阿明·肖克罗拉
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Kang Du Laboratories Inc
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
    • H04L25/40—Transmitting circuits; Receiving circuits
    • H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/26—Systems using multi-frequency codes
    • H04L27/2601—Multicarrier modulation systems
    • H04L27/2626—Arrangements specific to the transmitter only
    • H04L27/2627—Modulators
    • H04L27/2637—Modulators with direct modulation of individual subcarriers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4247—Bus transfer protocol, e.g. handshake; Synchronisation on a daisy chain bus
    • G06F13/426—Bus transfer protocol, e.g. handshake; Synchronisation on a daisy chain bus using an embedded synchronisation, e.g. Firewire bus, Fibre Channel bus, SSA bus
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076—Timing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4093—Input/output [I/O] data interface arrangements, e.g. data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1066—Output synchronization
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1093—Input synchronization
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
    • H04L25/40—Transmitting circuits; Receiving circuits
    • H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems
    • H04L25/4917—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using multilevel codes
    • H04L25/4919—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using multilevel codes using balanced multilevel codes
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

描述了用于支持编码子信道的正交差分向量信令码，所述正交差分向量信令码允许在相同传输介质上传输不同的时间对准式数据以及时钟信号。本发明实施例中所描述的增型LPDDR接口既适合在常规高速CMOS工艺中实施，也适合在DRAM集成电路工艺中实施。

Description

带内嵌时钟的正交差分向量信令码
相关申请的交叉引用
本申请要求申请号为62,032,175，申请日为2014年8月1日，发明人为布赖恩〃霍尔登(Brian Holden)和阿明〃肖克罗拉(Amin Shokrollahi)，名称为“带内嵌时钟的正交差分向量信令码”的美国临时专利申请的优先权，并通过引用将其内容整体并入本文，以供所有目的之用。
参考文献
以下参考文献通过引用整体并入本文，以供所有目的之用：
公开号为2011/0268225，申请号为12/784,414，申请日为2010年5月20日，发明人为Harm Cronie和Amin Shokrollahi，名称为“正交差分向量信令”的美国专利申请，下称《Cronie 1》；
申请号为13/030,027，申请日为2011年2月17日，发明人为Harm Cronie、AminShokrollahi和Armin Tajalli，名称为“利用稀疏信令码进行抗噪声干扰、高引脚利用率、低功耗通讯的方法和系统”的美国专利申请，下称《Cronie 2》；
申请号为14/158,452，申请日为2014年1月17日，发明人为John Fox、BrianHolden、Peter Hunt、John D Keay、Amin Shokrollahi、Richard Simpson、Anant Singh、Andrew Kevin John Stewart和Giuseppe Surace，名称为“低同步开关噪声芯片间的通信”的美国专利申请，下称《Fox 1》；
申请号为13/842,740，申请日为2013年3月15日，发明人为Brian Holden、AminShokrollahi和Anant Singh，名称为“芯片间通信的向量信令码中的偏斜耐受方法以及用于芯片间通信的向量信令码的高级检测器”的美国专利申请，下称《Holden 1》；
申请号为61/934,804，申请日为2014年2月2日，发明人为Ali Hormati和AminShokrollahi，名称为“利用ISI比进行代码评价的方法”的美国临时专利申请，下称《Hormati 1》；
申请号为61/934,807，申请日为2014年2月2日，发明人为Amin Shokrollahi，名称为“高引脚利用率向量信令码及其在芯片间通信及存储中的应用”，下称《Shokrollahi 1》；
申请号为61/839,360，申请日为2013年6月23日，发明人为Amin Shokrollahi，名称为“低接收器复杂度的向量信令码”的美国临时专利申请，下称《Shokrollahi 2》；
申请号为61/946,574，申请日为2014年2月28日，发明人为AminShokrollahi，BrianHolden和RichardSimpson，名称为“内嵌时钟的向量信令码”的美国临时专利申请，下称《Shokrollahi 3》；
申请号为62/015,172，申请日为2014年7月10日，发明人为Amin Shokrollahi和Roger Ulrich，名称为“高信噪比特性向量信令码”的美国临时专利申请，下称《Shokrollahi 4》；
申请号为13/895,206，申请日为2013年3月15日，发明人为Roger Ulrich和PeterHunt，名称为“用于通过差和高效检测芯片间通信用的向量信令码的电路”的美国专利申请，下称《Ulrich 1》；
申请号为62/026,860，申请日为2014年7月21日，发明人为Roger Ulrich和AminShokrollahi，名称为“总线可逆正交差分向量信令码”的美国临时专利申请，下称《Ulrich2》；
此外，本申请中还引用了以下现有技术参考文献：
专利号为7,053,802，申请日为2004年4月22日，授权公告日为2006年5月30日，发明人为William Cornelius，名称为“带内嵌定时功能的单端平衡编码型接口”的美国专利，下称《Cornelius》；
专利号为8,064,535，申请日为2007年3月2日，授权公告日为2011年11月22日，发明人为George Wiley，名称为“三相三极编码型串行接口”的美国专利，下称《Wiley》；
专利号为8,649,460，申请日为2010年3月11日，授权公告日为2014年2月11日，发明人为Frederick Ware和Jade Kizer，名称为“利用嵌入式时钟进行多线路编码的技术”的美国专利，下称《Ware》。
背景技术
通信系统中的一个目的在于将信息从一个物理位置传输至另一物理位置。一般而言，此类信息传输的目标在于，可靠、快速且消耗最少的资源。一种常见的信息传输媒介为串行通信链路，此种链路可以以将地面或其他常用基准作为比较对象的单个有线电路或将地面或其他常用基准作为比较对象的多个此类有线电路为基础。常见的一例为使用单端信令(SES)。单端信令的工作原理为，在一条线路中发送信号，然后在接收器端以固定基准值为比较对象测定所述信号。串行通信链路也可以以相互间作为比较对象的多个电路为基础。此方面的常见的一例为使用差分信令(DS)。差分信令的工作原理在于，在一条线路中发送信号，并在配对线路中发送所述信号的相反信号。所述信号的信息由上述两线路之间的差值，而非其相对于地面或其他固定基准值的绝对值表示。
与差分信令相比，有多种信令方法可在增加引脚利用率的同时，保持相同的有益特性。向量信令为一种信令方法。通过向量信令，多条线路中的多个信号在保持每个信号的独立性的同时可视为一个整体。该信号整体中的每个信号均称为向量分量，而所述多条线路的数目称为向量“维数”。在一些实施方式中，与差分信令对的情况相同，一条线路中的信号完全取决于另一线路中的信号。因此，在某些情况下，向量维数可指多条线路内的信号的自由度数，而非该多条线路的数目。
向量信令码的任何合适子集均为该码的“子码”。此类子码可本身为一种向量信令码。在二元向量信令中，每个向量分量(或称“符号”)的取值为两个可能取值当中的一值。在非二元向量信令中，每个符号的取值为从由两个以上可能取值所组成的集合中选出的一值。当作为物理信号在通信介质中传输时，符号可由适合于该介质的具体物理值表示。例如，在一种实施方式中，可由150mV的电压表示符号“+1”，50mV的电压表示符号“-1”；而在另一实施方式中，“+1”可由800mV表示，“-1”可由-800mV表示。
在本文中，向量信令码为由具有相同长度N的向量(称作码字)组成的集合C。集合C大小的二进制对数与长度N之间的比值称为该向量信令码的引脚利用率。向量信令码的示例见《Cronie 1》、《Cronie 2》、《Fox 1》、《Shokrollahi 1》、《Shokrollahi 2》及《Shokrollahi 3》中的正交差分向量信令码，该码在本文中用于描述目的。
图1所示为采用向量信令码的通信系统。比特S0，S1，S2从分块100进入编码器112。该分块的大小可变且取决于所述向量信令码的参数。所述编码器生成该向量信令码的码字，而且所述系统为针对该向量信令码而设计的系统。运行时，所述编码器可生成信息，该信息用于控制驱动器118内的PMOS和NMOS晶体管，从而在N条通信线路125上生成电压或电流，且该N条通信线路包括通信信道120。接收器132读取所述线路中的电压或电流，此过程有可能涉及放大、频率补偿和共模信号消除。接收器132将其结果提供于解码器138，该解码器重新在140处生成上述输入比特，此处表示为接收比特R0，R1，R2。
根据所使用向量信令码的不同，可不设置解码器，或不设置编码器，或既不设置解码器也不设置编码器。举例而言，对于《Cronie 2》中公开的8b8w码，既设置了编码器112，也同时设置了解码器138。另一方面，对于《Cronie 1》中公开的阿达玛码，可无需明确设置解码器，这是因为该系统可设置为使得接收器132直接生成输出比特。
为了保证所述通信系统的正确运行，必须使发送装置110的操作(包括输入数据100和元件112和118)与接收装置130的操作(包括元件132，可选元件138以及输出数据140)完全同步化。在一些实施方式中，该同步化由所述发送器和接收器共享的外部时钟实现。在其他实施方式中，与众所周知的用于串行通信的双相编码的情况相同，所述时钟功能可与一条或多条数据信道相结合。
此方面的重要一例为存储接口，在该接口中，在控制器内生成时钟，并与存储器共享。该存储器既可将所述时钟信息用于其内部存储操作，也可将其用于输入/输出。由于存储操作的突发性和非同步性，所述输入/输出功能并不随时处于可用状态。此外，主时钟和数据线路可能因偏斜而互不对齐。在这些情形下，须使用额外的选通信号对何时进行数据读写进行指示。
发明内容
公开一种可实现数据与时钟信号传输的正交差分向量信令码，该代码既适合在常规高速CMOS工艺中实施，也适合在DRAM集成电路工艺中实施。以下描述了从现有低功率DDR4接口实践中获得的例示信道，以及具有更快速度及更大信号完整性的适度信道改进。
附图说明
图1显示了采用向量信令码的通信系统。
图2显示了ODVS通信系统的一种实施方式，其中，无需分立的解码功能。
图3为一种实施方式的框图，该实施方式利用ODVS码发送数据及时钟信号，并含有可促进接收器与现有DRAM实践的集成的元件。
图4为采用5b6w码(也称透翅码)在所提出LPDDR5信道上实施传输的实施方式框图。
图5为采用8b9w码在所提出LPDDR5信道上实施传输的实施方式框图。
图6为采用ENRZ码在所提出LPDDR5信道上实施传输的实施方式框图。
图7A，7B和7C所示分别为在6.4G波特和8.4G波特的信令速率下工作的透翅码，ENRZ码和8b9w码实施方式的比较接收眼图。
图8所示为根据至少一个实施例的方法。
具体实施方式
图1所示为采用向量信令码的通信系统。发射器110的输入源数据(图示为S0，S1，S2)通过分块100进入编码器112。该分块的大小可变且取决于所述向量信令码的参数。编码器112生成该向量信令码的码字，而且所述系统为针对该向量信令码所设计的系统。运行时，由编码器112生成的所述码字用于控制驱动器118内的PMOS和NMOS晶体管，从而能够在通信信道120的N条通信线路125当中的每条线路上产生两个，三个或更多个不同的电压或电流，以表示所述码字的N个符号。在通信接收器130内，接收器132读取所述N条线路125中的电压或电流(此过程有可能涉及放大、频率补偿和共模信号消除)，并将其结果提供于解码器138，该解码器将所述输入比特重新生成为接收结果140(图示为R0，R1，R2)。容易理解的是，不同代码可与不同分块大小和不同码字大小相关联；为了描述的方便性，图1示例为采用ODVS码的系统，但这并不构成任何限制，该代码可编码在四条线路上传输的三个二进制比特值，即所谓的3b4w码。
根据所使用向量信令码的不同，可不设置解码器，或不设置编码器，或既不设置解码器也不设置编码器。举例而言，对于《Cronie 2》中公开的8b8w码，既设置了编码器112，也同时设置了解码器138。另一方面，对于《Cronie 1》中公开的H4码(本文中也称为ENRZ码)，可无需明确设置解码器，这是因为该系统可设置为使得接收器132直接生成接收结果140。
为了保证所述通信系统的正确运行，必须使通信发射器110的操作与通信接收器130的操作完全同步化。在一些实施方式中，该同步化由所述发送器和接收器共享的外部时钟实现。在其他实施方式中，与众所周知的用于串行通信的双相编码的情况相同，所述时钟功能可与所述数据信道中的一条或多条相结合。
此方面的重要一例为存储接口，在该接口中，在控制器内生成时钟，并与存储器共享。该存储器既可将所述时钟信息用于其内部存储操作，也可将其用于输入/输出。由于存储操作的突发性和非同步性，所述输入/输出功能并不随时处于可用状态。此外，主时钟和数据线路可能因偏斜而互不对齐。在这些情形下，须使用额外的选通信号对何时进行数据读写进行指示。
历经数代设计，系统存储控制器与多个动态RAM器件之间的接口在传输速度和低功耗方面已获得极大优化。现有技术的DRAM接口LPDDR4包括8条数据线，1条DMI信号线，2条选通线，以及其他相关非数据传输线。
人们对于将LPDDR4扩展至以相同或更少的功耗支持更高性能具有极大兴趣，然而仅对现有技术的性能进行改进似乎存在着问题。在使用现有单端互连的情况下，如果单单提高数据传输速率，将使得信号完整性降低，从而使得此方式不可行。此外，众所周知，即使在当前的时钟速度下，接收的DRAM数据与其选通信号之间的不能对准仍然是一个问题。然而，新技术的引入又受到如下限制：人们极其希望尽可能多地保留总线布局、信号分布、时钟设置等方面的现有实践；所述新技术需要满足既可在用于存储控制器的高速CMOS工艺中实施，又可在用于制造具有相对较慢数字和接口逻辑的极小型、高电容、低泄漏存储器单元的高度专用DRAM制造工艺中实施。
由于此逻辑速度较慢，因此现有的DRAM设计中采用两个或更多处理逻辑阶段处理现有LPDDR4数据传输速率，例如，一个处理逻辑阶段用于捕获数据传输选通信号的上升沿数据，另一处理逻辑阶段用于捕获选通信号的下降沿数据。此类多阶段处理实施方式的一个潜在限制在于其难于从连续接收单元间隔提取差分类信息，这是因为连续单元间隔仅为不同处理阶段下的一个概念。因此，对于分别使用依赖于对连续单元间隔内接收的数据值进行比较的跃迁编码数据方案及内嵌时钟式或自时钟式数据方案的两种代码而言，多阶段处理存在问题。
在所述通信接收器实施方式中，上述时钟提取及跃迁或变化检测问题最难解决，因此本文中示例集中于，在所述实施方式中所述相对较慢的DRAM器件为上述接收器。但是，这不构成限制，因为熟悉本领域的人员容易理解的是，以DRAM器件实施双向数据通信易于理解，且适于实施DRAM接收的例示实施方式同样也可满足更为简单的发送要求。
使用多输入比较器的接收器
如《Holden 1》中所述，系数为a0,a1,…,am-1的多输入比较器为一种电路，该电路接收输入向量(x0,x1,…,xm-1)，并输出：
结果＝(a0×x0+…+am-1×xm-1) (式1)
由于多种实施方式需要输出为二进制值，因此使用模拟比较器对该结果值进行分割，以生成二进制判定输出。由于用法较为常见，因此所述电路的通俗名称中包括“比较器”一词，但其他实施方式也可能使用PAM-3或PAM-4分割器获得三进制或四进制输出，或可实际上保留式1的模拟输出，以用于进一步计算。在至少一种实施方式中，根据与用于生成所述ODVS码的非简单正交矩阵或单位矩阵的行对应的子信道向量，选择上述系数。
作为一例，根据《Ulrich1》的教示内容，可使用相同四位输入的多输入比较器的三个实例对所述ODVS码(本文称为ENRZ码)进行检测，以执行以下运算：
R0＝(A+C)-(B+D) (式2)
R1＝(C+D)-(A+B) (式3)
R2＝(C+B)-(D+A) (式4)
可易于通过系数为[+1,+1,-1,-1]的多输入比较器的三个完全相同的实例以及所述四个输入值的不同排列组合形式执行如式2～4所描述的运算。
ODVS子信道
通常，将图1编码器112的数据输入视为待原子式地编码为码字的数据向量(即数据字)，该码字经信道120传输，然后被接收器132检测，并最终被138解码，从而生成所发送向量或数据字的接收重构形式。
然而，所述通信系统可以稍微不同的方式但以同等的准确性进行建模。由于此替代模型可在无需其他解码器的系统中得到最好的理解，为了描述目的，采用基于图2所示的ENRZ码的具体实施方式，但这不构成限制。图2中，与图1元件功能相同的元件采用相同编号，但图2在下文中还展示了其他内部结构以及图1中泛述的组成特征。
图2中，进入通信发射器110的输入数据向量100明确示为扩展为其各个比特S0，S1，S2并进入编码器112。表示编码器112的输出码字符号的各个信号示为对各个线路驱动器118进行控制，以使其向包括通信信道120的线路125发射信号。由于任何一条传输所述ENRZ码的线路均可取四个不同信号值当中的一个值，因此每条线路的线路驱动器均示为由两个控制信号控制。
如上所述，在此实施方式中，通信接收器130无需明确设置解码器。接收器132的内部结构图示为包括从线路125接收信号的四个接收前端(如131)，而且根据通信信道120的特性的要求，可选包括放大和均衡功能。如图所示，三个多输入比较器的输入端连接于式2，式3和式4所述的四个接收线路信号。为了避免混淆，所述多输入比较器如图所示为包括计算功能133以及其后的分割功能134，该分割功能自所述输入值的运算组合中产生数字输出R0，R1，R2。
熟悉本领域的技术人员可注意到的是，所述ODVS编码器接收一组输入数据并在每个发送单元间隔内输出一个码字。如果与上述多种实施方式中的情形一样，所述编码器包括组合数字逻辑(即无额外内部状态)，则此周期性码字输出可易于视作在编码变换、后续传输等之前向所述输入数据实施的采样功能。类似地，如果与此处所述由多输入比较器执行检测的情形一样，所述接收器内的检测运算同样为组合运算，则给定输出元素的状态仅由一定数量的信道线路上的接收信号电平确定。因此，每个独立信号输入(例如S0)及其等效独立信号输出(如R0)均可视为虚拟通信信道，本文称其为所述ODVS编码系统的“子信道”。给定子信道既可以为二进制信道(即传送双状态值)，也可表示更高阶的值。实际上，正如《Shokrollahi4》中所述，给定ODVS码的子信道的独立性足以使其采用不同码集(及码集大小)描述其所传送的值。
ODVS系统内包括子信道内的状态变化在内的所有数据通信均以码字形式在整个信道内发送。在一种实施方式中，如《Holden 1》和《Ulrich 1》中所述，可将输入值的特定映射与码字相关联，并将这些映射与特定检测器结果相关联，但此类关联不应与通信介质本身的分区、子分区或子信道相混淆。
ODVS子信道的概念并不因上述例示实施方式而限制于特定ODVS代码、发射器实施方式或接收器实施方式。保持内部状态的编码器和/或解码器也可为实施方式的部件。子信道既可由各个信号表示，也可由多个信号传送的状态表示。
子信道内的定时信息
由于ODVS通信系统必须将数据输入的每种组合以编码传输的形式进行发送，而且此类编码传输的速率必然受通信介质的容量限制，因此待传输数据的变化速率必须处于奈奎斯特极限之内，其中，码字的传输速率表示采样间隔。举例而言，如果二进制时钟或选通信号在每个码字传输时的时钟边沿数不超过一个，则其可在ODVS子信道内传输。
在ODVS编码器和关联线路驱动器的一种实施方式中，其可在数据输入中发生任何变化时以非同步方式工作。在其他实施方式中，可例如通过内部定时时钟将多个数据处理阶段相结合，以生成单个高速输出流。在此类实施方式中，码字所有元素的输出均以内在同步的方式进行，因此所述代码子信道内传送的选通或时钟信号在所述接收器处表现为数据对准式时钟(例如，其跃迁边沿与该代码其他子信道内的数据边沿同步)。在无时钟或非同步实施方式中也通常设定类似的定时关系。
图3为ODVS通信系统的框图，在该系统内，子信道内承载数据对准式选通信号(类似于与已知LPDDR4信道相关联的选通信号)，而该代码的其他子信道承载N个比特的数据。在接收器内，一系列多输入比较器132对所接收信息进行检测，并输出数据345及所接收的数据对准式选通信号346。此外，通过引入半个单元间隔的延时350，使所接收的选通信号发生偏移，以生成眼图对准式选通信号356，该信号的跃迁边沿处于最佳采样时间，从而实现数据345的锁存。作为多种DRAM实施方式中的一种通常做法，图示中为用于数据采样的两个处理阶段：处理阶段360对眼图对准式选通信号356负边沿上的数据345进行采样，而处理阶段370对眼图对准式选通信号356正边沿上的数据345进行采样。通过LPDDR接口实现延时350的方法及其可能所需的任何关联调整或校准手段均为本领域所熟知。
LPDDR通信至ODVS系统的映射
现有的LPDDR4规范规定了8条数据线路，1条DMI线路以及2条选通线路，共11条线路。利用ODVS编码，可通过数种方式将这些现有连接映射至一种新的协议模式，本文称为LPDDR5。
根据《Holden1》的教示内容，多输入比较器的噪声特性取决于其输入端尺寸及配置。根据《Shokrollahi 4》的教示内容，式1中各种运算所产生的信号幅度可表示不同接收眼图特性。因此，在优选实施方式中，当可用子信道的特性可变时，将指定质量较高(如眼开度较大)的子信道承载时钟、选通或其它定时信息。
透翅码
第一实施方式在本文中称为透翅(Glasswing)码并示于图4的框图中，该实施方式新增1条线路，从而共提供12条线路，这些线路以逻辑方式分为两个六线组。每个六线组用于承载ODVS码的一个实例，以在6条线路上传输5个比特(以下称为5b6w码)，从而共提供10条子信道。其中，8条子信道用于承载8个数据比特，1条子信道用于承载掩码比特(通常在DRAM写操作期间用于防止单独字节写入)，还有1条子信道用于承载数据对准式选通信号。该5b6w码为平衡码，任何给定码字内的所有符号的和为零，而且其构造使得每个码字恰好包含一个+1和一个-1，而其余码字符号包括符号+1/3和-1/3。对于本领域的技术人员而言容易理解的是，实施方式中可使用合适码字集合的多种排列组合形式以及相应的比较器检测系数。
透翅码中，每个5b6w接收器包括五个多输入比较器。在一种优选实施方式中，5b6w码的每个实例的码字如表1所示，而且所述一组比较器为：
x0-x1
(x0+x1)/2-x2
x4-x5
x3-(x4+x5)/2
(x0+x1+x2)/3-(x3+x4+x5)/3
其中，每个六线组的线路表示为x0,x1...x5。
表1
5b6w码的其他信息可参见《Ulrich 2》。
8b9w码
第二实施方式在本文中称为“8b9w”码并示于图5的框图中，该实施方式保留现有LPDDR4的11条数据传输线路。其中，9条线路用于承载8b9w码，该码本身包含本文称为4.5b5w码的五线码，以及本文称为3.5b4w码的四线码，此两种代码合并提供288个不同码字组合，编码器使用其中的257个。在这257个码字当中，256个码字用于在掩码输入为假时编码8个比特数据，而另1个码字用于在掩码输入为真时标记“不写入”这一条件。数据对准式选通信号利用现有手段发送，即使用上述两条现有的LPDDR4选通线路。
在至少一种实施方式中，每个4.5b5w接收器包括七个多输入比较器，其使用如表2所示的4.5b5w码的码字以及以下一组比较器：
x0-x1
x0-x2
x0-x3
x1-x2
x1-x3
x2-x3
(x0+x1+x2+x3)/4-x4
其中，每个五线组的线路表示为x0，x1...x4。
表2
前6个比较器的符号间干扰比为2，而最后一个比较器的符号间干扰比为1(见《Hormati 1》)。
在该实施方式中，所述3.5b4w码的码字如表3所示。
表3
每个3.5b4w接收器包括六个多输入比较器。如果每个四线组的线路表示为x0,x1...x3，则所述比较器为：
x0-x1
x0-x2
x0-x3
x1-x2
x1-x3
x2-x3
所有上述比较器的符号间干扰比为2(见《Hormati 1》)。
ENRZ码
第三实施方式在本文中称为“ENRZ”码并示于如图6所示的框图中，该实施方式在现有LPDDR4方案中新增1条线路，从而共提供12条线路，这些线路以逻辑方式分为三个四线组。每个四线组用于承载ENRZ码的一个实例，因此每个实例具有八个唯一码字。在至少一种实施方式中，每个实例的一个码字保留为重复码，而每个实例的7个剩余码字由编码器组合，以提供7×7×7＝343个唯一组合形式，从而足以编码上例所述的8个数据比特及一个掩码条件。在另一实施方式中，不指定重复码字。相反的，如《Shokrollahi3》中所述，发射器可将最后发送的码字保存，并为下一单位间隔(UI)生成与所发送码字不同的码字。所述数据对准式选通信号用于为发射器的码字发射定时，而且每当当前待发送码字与前一单元间隔所发送的码字相同时，则发送每个实例的重复码。在接收机器中，使用本领域已知的时钟恢复电路从所接收码字的边沿提取定时信息，并由一个数据值历史缓冲器在检测到所接收重复码字时重新生成所复制的数据值。
此实施方式的进一步描述可参见《Shokrollahi3》。
图7A，7B和7C所示为各种实施方式的比较，其中所示透翅码，ENRZ码和8b9w实施方式的接收眼图分别得自6.4G波特和8.4G波特的信令速率。
本文实施例描述了向量信令码在点对点线路通信中的使用。然而，这不应视为对所描述实施方式的范围进行了任何限制。本申请中所公开的方法同样适用于包括光学和无线通信在内的其他通信介质。因此，“电压”和“信号电平”等描述性词语应视为包括其在其他度量系统中的同等概念，如“光强”、“射频调制”等。本文所使用的“物理信号”一词包括可传送信息的物理现象的任何适用形态和/或属性。此外，此类物理信号可以为有形的非暂时性信息。
实施方式
在至少一种实施方式中，一种方法800包括：在步骤802中，在多个多输入比较器(MIC)处接收向量信令码的码字的一个符号集，所述符号集表示以非简单正交矩阵或单位矩阵对输入向量所做的变换，所述输入向量包括多条子信道，其中，至少一条子信道对应于输入数据信号，而且至少一条子信道对应于数据对准式选通信号；在步骤804中，根据所述码字的多个符号子集之间的多个比较，形成一组多输入比较器输出信号，其中，对于每个比较，每个符号子集具有由相应多输入比较器决定且施加于该符号子集的一组输入系数，所述一组多输入比较器输出信号包括至少一个数据输出信号以及至少一个所接收的数据对准式选通信号；以及在步骤806中，根据所述至少一个所接收的数据对准式选通信号对所述至少一个数据输出信号进行采样。
在至少一种实施方式中，在所述至少一个所接收的数据对准式选通信号的上升沿采样所述至少一个数据输出信号。在另一实施例中，在所述至少一个所接收的数据对准式选通信号的下降沿采样所述至少一个输出数据信号。
在至少一种实施方式中，所述输入向量包括对应于输入数据信号的4条子信道以及对应于数据对准式选通信号的1条子信道。在至少一种实施方式中，所述符号集中的每个符号具有选自由至少两个值组成的集合中的值。在另一实施方式中，所述符号集中的每个符号具有选自值集{+1,+1/3,-1/3,-1}的值。
在至少一种实施方式中，每个多输入比较器的所述一组输入系数均由所述非简单正交矩阵或单位矩阵决定。
在至少一种实施方式中，所述码字为均衡码字。
在至少一种实施方式中，该方法还包括通过分割所述一组多输入比较器输出信号形成一组输出比特。
在至少一种实施方式中，该方法还包括：从多条线路上接收所述输入向量；使用编码器生成所述码字的符号集，该符号集表示子信道向量的加权和，所述子信道向量对应于所述非简单正交矩阵或单位矩阵的行，其中，每个子信道向量的加权值由相应的输入向量子信道决定；以及将所述码字的符号提供于多线路总线。
在至少一种实施方式中，一种装置包括：多线路总线，用于接收向量信令码的码字的一个符号集，所述符号集表示以非简单正交矩阵或单位矩阵对输入向量所做的变换，所述输入向量包括多条子信道，其中，至少一个条所述信道对应于输入数据信号，而且至少一条所述子信道对应于数据对准式选通信号；多个多输入比较器(MIC)，用于根据所述码字的多个符号子集之间的多个比较，形成一组多输入比较器输出信号，其中，对于每个比较，每个所述符号子集具有由相应的多输入比较器决定且施加于该符号子集的一组输入系数，所述一组多输入比较器输出信号包括至少一个数据输出信号以及至少一个所接收的数据对准式选通信号；以及多个采样电路，用于根据所述至少一个所接收的数据对准式选通信号对所述至少一个数据输出信号进行采样。
在至少一种实施方式中，至少一个采样电路用于在所述至少一个所接收的数据对准式选通信号的上升沿采样所述至少一个数据输出信号。在另一实施方式，至少一个采样电路用于在所述至少一个所接收的数据对准式选通信号的下降沿采样所述至少一个输出数据信号。
在至少一种实施方式中，所述输入向量包括对应于输入数据信号的4条子信道以及对应于数据对准式选通信号的1条子信道。在至少一种实施方式中，所述符号集中的每个符号具有选自由至少两个值组成的集合中的值。在另一实施方式中，所述符号集中的每个符号具有选自值集{+1,+1/3,-1/3,-1}的值。
在至少一种实施方式中，每个多输入比较器的所述一组输入系数均由所述非简单正交矩阵或单位矩阵决定。
在至少一种实施方式中，所述码字为均衡码字。
在至少一种实施方式中，该装置还包括多个分割器，用于通过分割所述一组多输入比较器输出信号形成一组输出比特。
在至少一种实施方式中，一种装置包括：多条线路，用于接收所述输入向量，该输入向量包括多条子信道，其中至少一条所述子信道对应于数据信号，且至少一条所述子信道对应于数据对准式选通信号；编码器，用于生成所述码字的符号集，该符号集表示子信道向量的加权和，所述子信道向量对应于所述非简单正交矩阵或单位矩阵的行，其中，每个所述子信道向量的加权值由相应的输入向量子信道决定；以及多个线路驱动器，用于向多线路总线发送所述码字的所述符号。

Claims (15)

1.一种方法，其特征在于，包括：
通过多线路总线，在多个多输入比较器处接收平衡向量信令码的码字的一个符号集，其中，任何一条线路均能取四个不同信号值当中的一个值，任何给定码字内的所有符号的和为零，所述符号集表示以与非简单正交矩阵或单位矩阵的行对应的子信道向量对输入向量所做的变换，所述输入向量包括多条子信道，其中至少一条所述子信道对应于输入数据信号，而且至少一条所述子信道对应于数据对准式选通信号；
根据所述码字的多个符号子集之间的多个比较，形成一组多输入比较器输出信号，其中，对于每个比较，每个所述符号子集分别具有由相应的多输入比较器施加于该符号子集的一组输入系数，每一组输入系数根据与所述非简单正交矩阵或单位矩阵的相应行对应的子信道向量选择，所述一组多输入比较器输出信号包括至少一个数据输出信号以及至少一个所接收的数据对准式选通信号；以及
根据所述至少一个所接收的数据对准式选通信号对所述至少一个数据输出信号进行采样。
2.如权利要求1所述的方法，其特征在于，在所述至少一个所接收的数据对准式选通信号的上升沿采样所述至少一个数据输出信号。
3.如权利要求1所述的方法，其特征在于，在所述至少一个所接收的数据对准式选通信号的下降沿采样所述至少一个输出数据信号。
4.如权利要求1所述的方法，其特征在于，所述输入向量包括对应于输入数据信号的4条子信道以及对应于所述数据对准式选通信号的1条子信道。
5.如权利要求4所述的方法，其特征在于，所述符号集中的每个符号具有选自值集{+1,+1/3,-1/3,-1}的值。
6.如权利要求5所述的方法，其特征在于，每个码字是[+1,-1/3,-1/3,-1/3]或[-1,+1/3,+1/3,+1/3]的排列组合。
7.如权利要求1所述的方法，其特征在于，还包括通过分割所述一组多输入比较器输出信号形成一组输出比特。
8.如权利要求1的所述方法，其特征在于，还包括：
从多条线路上接收所述输入向量；
使用编码器生成所述码字的符号集，所述符号集表示子信道向量的加权和，所述子信道向量对应于所述非简单正交矩阵或单位矩阵的行，其中，每个所述子信道向量的加权值由相应的输入向量子信道决定；以及
将所述码字的所述符号提供于多线路总线。
9.一种装置，其特征在于，包括：
多线路总线，用于接收平衡向量信令码的码字的一个符号集，其中，任何一条线路均能取四个不同信号值当中的一个值，任何给定码字内的所有符号的和为零，所述符号集表示以与非简单正交矩阵或单位矩阵的行对应的子信道向量对输入向量所做的变换，所述输入向量包括多条子信道，其中至少一条所述子信道对应于输入数据信号，而且至少一条所述子信道对应于数据对准式选通信号；
多个多输入比较器，用于根据所述码字的多个符号子集之间的多个比较，形成一组多输入比较器输出信号，其中，对于每个比较，每个所述符号子集分别具有由相应的多输入比较器施加于该符号子集的一组输入系数，每一组输入系数根据与所述非简单正交矩阵或单位矩阵的相应行对应的子信道向量选择，所述一组多输入比较器输出信号包括至少一个数据输出信号以及至少一个所接收的数据对准式选通信号；以及
多个采样电路，用于根据所述至少一个所接收的数据对准式选通信号对所述至少一个数据输出信号进行采样。
10.如权利要求9所述的装置，其特征在于，至少一个采样电路用于在所述至少一个所接的收数据对准式选通信号的上升沿采样所述至少一个数据输出信号。
11.如权利要求9所述的装置，其特征在于，至少一个采样电路用于在所述至少一个所接收的数据对准式选通信号的下降沿采样所述至少一个输出数据信号。
12.如权利要求9所述的装置，其特征在于，所述输入向量包括对应于输入数据信号的4条子信道以及对应于数据对准式选通信号的1条子信道。
13.如权利要求9所述的装置，其特征在于，所述符号集中的每个符号具有选自值集{+1,+1/3,-1/3,-1}的值。
14.如权利要求13所述的装置，其特征在于，每个码字是[+1,-1/3,-1/3,-1/3]或[-1,+1/3,+1/3,+1/3]的排列组合。
15.如权利要求9所述的装置，其特征在于，还包括多个分割器，用于通过分割所述一组多输入比较器输出信号形成一组输出比特。
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