CN106105123B - 用于发送时钟嵌入式向量信令码的方法和系统 - Google Patents
用于发送时钟嵌入式向量信令码的方法和系统 Download PDFInfo
- Publication number
- CN106105123B CN106105123B CN201580010265.2A CN201580010265A CN106105123B CN 106105123 B CN106105123 B CN 106105123B CN 201580010265 A CN201580010265 A CN 201580010265A CN 106105123 B CN106105123 B CN 106105123B
- Authority
- CN
- China
- Prior art keywords
- data
- code
- subchannel
- vector signaling
- vector
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
- H04L25/40—Transmitting circuits; Receiving circuits
- H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
- H04L25/03006—Arrangements for removing intersymbol interference
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
- H04L25/03006—Arrangements for removing intersymbol interference
- H04L25/03012—Arrangements for removing intersymbol interference operating in the time domain
- H04L25/03019—Arrangements for removing intersymbol interference operating in the time domain adaptive, i.e. capable of adjustment during data reception
- H04L25/03057—Arrangements for removing intersymbol interference operating in the time domain adaptive, i.e. capable of adjustment during data reception with a recursive structure
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/08—Modifications for reducing interference; Modifications for reducing effects due to line faults ; Receiver end arrangements for detecting or overcoming line faults
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/08—Modifications for reducing interference; Modifications for reducing effects due to line faults ; Receiver end arrangements for detecting or overcoming line faults
- H04L25/085—Arrangements for reducing interference in line transmission systems, e.g. by differential transmission
Abstract
公开了可实现在每单位发送间隔内发生保证数目次转态的向量信令码及其发生系统和用途。该结构可包括多个通信子系统,每个通信子系统具有其自身的通信线路组或子信道,时钟嵌入式信令代码,用于保证所需代码转态密度的预处理和后处理级,以及用于先为各子系统分配数据元素,然后从其所接收的子系统元素中重建所接收数据的全局编码和解码级。
Description
相关申请的交叉引用
本申请要求申请号为61/946,574,申请日为2014年2月28日的美国临时申请的优先权,并通过引用将其内容整体并入本文。
本发明技术领域总体涉及通过向量信令码传送信息的通信系统。
参考文献
以下参考文献通过引用整体并入本文,以供所有目的之用:
公开号为2011/0268225,申请号为12/784,414,申请日为2010年5月20日,发明人为Harm Cronie和Amin Shokrollahi,名称为《正交差分向量信令》的美国专利申请,下称“《Cronie I》”;
申请号为13/030,027,申请日为2011年2月17日,发明人为Harm Cronie、AminShokrollahi和Armin Tajalli,名称为《利用稀疏信令码进行抗噪声干扰、高引脚利用率、低功耗通讯的方法和系统》的美国专利申请,下称“《Cronie II》”;
申请号为61/753,870,申请日为2013年1月17日,发明人为John Fox、BrianHolden、Peter Hunt、John D Keay、Amin Shokrollahi、Richard Simpson、Anant Singh、Andrew Kevin John Stewart和Giuseppe Surace,名称为《低同步开关噪声芯片间通信方法和系统》的美国临时专利申请,下称“《Fox I》”;
申请号为13/842,740,申请日为2013年3月15日,发明人为Brian Holden、AminShokrollahi和Anant Singh,名称为《芯片间通信用向量信令码中偏斜耐受方法以及用于芯片间通信用向量信令码的高级检测器》的美国专利申请,下称“《Holden I》”;
申请号为61/934,804,申请日为2014年2月2日,发明人为Ali Hormati和AminShokrollahi,名称为《利用ISI比的代码评价方法》的美国临时专利申请,下称“《HormatiI》”;
申请号为61/934,807,申请日为2014年2月2日,发明人为Amin Shokrollahi,名称为《高引脚利用率向量信令码及其在芯片间通信及存储中的应用》,下称“《ShokrollahiI》”;
申请号为61/839,360,申请日为2013年6月23日,发明人为Amin Shokrollahi,名称为《低接收器复杂度向量信令》的美国临时专利申请,下称“《Shokrollahi II》”;
此外,本申请中还引用了以下现有技术参考文献:
专利号为7,053,802,申请日为2004年4月22日,授权日为2006年5月30日,发明人为William Cornelius,名称为《带内嵌定时功能的单端平衡编码型接口》的美国专利,下称“《Cornelius》”;
专利号为8,064,535,申请日为2007年3月2日,授权日为2011年11月22日,发明人为George Wiley,名称为《三相三极编码型串行接口》的美国专利,下称“《Wiley》”。
技术领域
本发明总体涉及通信领域,尤其涉及对可在集成电路器件内部或集成电路器件之间传送信息的信号的发送。
背景技术
通信系统中的一个目的在于将信息从一个物理位置传输至另一物理位置。一般而言,此类信息传输的目标在于可靠、快速且消耗最少的资源。一种常见的信息传输媒介为串行通信链路,此种链路可以以将地面或其他常用基准作为比较对象的单个有线电路或将地面或其他常用基准作为比较对象的多个此类有线电路为基础。常见的一例为对单端信令(Singled-ended Signaling,SES)的使用。单端信令的工作原理为,在一条线路中发送信号,然后在接收器端以固定基准值为比较对象测定所述信号。串行通信链路也可以以相互间作为比较对象的多个电路为基础。此方面的常见的一例为对差分信令(DifferentialSignaling,DS)的使用。差分信令的工作原理在于,在一条线路中发送信号,并在配对线路中发送所述信号的相反信号。所述信号的信息由上述两线路之间的差值,而非其相对于地面或其他固定基准值的绝对值表示。
与差分信令相比,有多种信令方法可在保持相同有益特性的同时,增加引脚利用率。向量信令为一种信令方法。通过向量信令,多条线路中的多个信号在保持每个信号的独立性的同时可视为一个整体。该信号整体中的每个信号均称为向量分量,而所述多条线路的数目称为向量“维数”。在一些实施方式中,与差分信令对的情况相同,一条线路中的信号完全取决于另一线路中的信号。因此,在某些情况下,向量维数可指多条线路内的信号的自由度数,而非确切指该多条线路的数目。
在二元向量信令中,每个向量分量(或称“符号”)的取值为两个可能取值当中的一值。在非二元向量信令中,每个符号的取值为从由两个以上可能取值所组成的集合中选出的一值。向量信令码的任何合适子集均为该码的“子码”。此类子码可本身为一种向量信令码。
在本文中,向量信令码为由长度均为N的称作码字的向量组成的集合C。集合C大小的二进制对数与长度N之间的比值称为该向量信令码的引脚利用率。
图1所示为使用向量信令码的现有技术通信系统。比特x0,x1,…以分块100的形式进入编码器105。该分块的大小可变且取决于所述向量信令码的参数。所述编码器生成所述向量信令码的码字,所述系统为针对该向量信令码设计的系统。运行时,所述编码器可生成信息,该信息用于控制驱动器110内的PMOS和NMOS晶体管,从而在N条通信线路115上生成电压或电流。接收器120读取所述线路中的电压或电流,此过程有可能涉及放大、频率补偿和共模信号消除。接收器120将其结果提供于解码器125,该解码器重新生成所述输入比特130。
根据所使用向量信令码的不同,可不设置解码器,或不设置编码器,或既不设置解码器也不设置编码器。举例而言,对于《Cronie II》中公开的8b8w码,既设置编码器105,也同时设置解码器125。另一方面,对于《Cronie I》中公开的阿达玛(Hadamard)码,可无需明确设置解码器,这是因为该系统可设置为使得接收器120直接生成输出比特130。
为了保证所述通信系统能正常工作,必须使元件100、105和110组成的发射器与元件120、125和130组成的接收器的运行完全同步化。在一些实施方式中,该同步化由所述发送器和接收器共享的外部时钟实现。在其他实施方式中,与众所周知的串行通信用双相编码的情况相同,所述时钟功能可与一条或多条数据信道相结合。
此方面的重要一例为存储接口,在该接口中,在控制器内生成时钟,并与存储器共享。该存储器既可将所述时钟信息用于其内部存储操作,也可将其用于输入/输出。由于存储操作的突发性和非同步性,所述输入/输出功能并不随时处于可用状态。此外,主时钟和数据线路可能因偏斜而互不对齐。在这些情形下,须使用选通信号对何时进行数据读写进行指示。
发明内容
本文所描述的为,可实现在每单位发送间隔内发生保证数目次转态的向量信令码及其一般性系统结构。该结构的元件可包括多个通信子系统,每个通信子系统具有其自身的通信线路组或子信道,时钟嵌入式信令代码,用于保证所需代码转态密度的预处理和后处理级,以及用于先为各子系统分配数据元素,然后从其所接收的子系统元素中重建所接收数据的全局编码和解码级。此外,本文还描述了每一结构元件的例示实施方式,以及适用于子信道通信的例示代码实施方式。
附图说明
图1所示为使用向量信令码的现有技术通信系统。
图2所示为带内嵌时钟信息的向量信令通信系统的实施方式。
图3为历史记录预编码器的一种实施方式的框图。
图4为历史记录后解码器的一种实施方式的框图。
图5为全局编码器的一种实施方式的流程图。
图6为预编码单元的一种实施方式的流程图。
图7为后解码器单元的一种实施方式的流程图。
图8为全局解码器的一种实施方式的流程图。
图9为ENRZ3通信系统发送器编码部分的一种实施方式的框图。
图10为ENRZ3通信系统的接收器解码部分的一种实施方式的框图。
图11为S34通信系统的发送编码部分编码器的一种实施方式的框图。
图12所示为作为S34编码器的一种实施方式的两电路示意图。
图13为S34通信系统的接收器解码部分的一种实施方式的框图。
图14所示为S4向量信令码的编码器的一种实施方式。
图15所示为P3向量信令码编码器的一种实施方式。
图16所示为采用模拟迟滞加判定反馈高通滤波时钟方案的一种时钟提取实施方式。
图17所示为采用数字迟滞加判定反馈高通滤波时钟方案的一种时钟提取实施方式。
图18所示为采用模拟异或时钟方案的一种时钟提取实施方式。
图19所示为采用每码字检测器及数字迟滞的一种时钟提取实施方式。
图20为编码器实施方式框图,着重展示出其开环和闭环处理电路部分。
图21为图20所示编码器实施方式的框图,其中,采用了并行的多个所述电路开环部分。
图22为解码器实施方式框图,着重展示出其开环和闭环处理电路部分。
图23为图22所示解码器实施方式的框图,其中,采用了并行的多个所述电路开环部分。
图24为一种发送方法流程图。
图25为一种接收方法流程图。
具体实施方式
图2所示为带内嵌时钟信息的向量信令通信系统的实施方式。在后续附图中,将对此系统的各元件进行参考及进一步描述。
图2中的通信系统由k个不同通信子系统组成,每个子系统均包括历史记录预编码器单元220、编码器105、驱动器110、n[i]条通信线路、接收器120、时钟恢复单元(CR)235、解码器125、历史记录后解码器单元245。其中,共有n[1]+n[2]+...+n[k]条通信线路,分为k个组,各组分别具有n[1],n[2],...,n[k]条线路。每个通信子系统i使用码字具有n[i]个坐标的向量信令码。
如该图所例示说明的一样,比特x(0),...,x(N-1)作为分块进入“全局编码器”单元205。在一些实施方式中,该单元仅将该输入比特200以分组形式发送,而在其他实施方式中,该单元还可对该输入比特进行进一步计算。全局编码器205输出k组比特210,每个通信子系统一组。
第i组比特210进入第i个历史记录预编码器单元220,该单元进一步输出另一组比特230,该组比特被发送至相应通信子系统的编码器105。编码器105生成其相应向量信令码的码字,驱动器110将该码字的坐标作为电压或电流在相应的n[i]条通信线路上驱动。
所述通信线路上的电压或电流由接收器120接收为信号,而且该接收器可对所接收的信号进行进一步均衡和处理,并可为时钟恢复单元235生成信息,该时钟恢复单元根据所接收的信号对时钟信息进行恢复。所接收的信号被进一步发送于解码器125,该解码器生成一组比特240,并将其发送于相应历史记录后解码器单元245。该单元计算出一组可能为新组的比特250,并将其发送于全局解码器260。在与相应的全局编码器联用时,在一些实施方式中,全局解码器260仅通过对输入250进行衔接或组合而获得输出比特270,而在另一些实施方式中,全局解码器260对从各个历史记录后解码器单元接收的比特250进行进一步计算,以重新生成输出比特x(0),...,x(N-1)270。在下文中,图2所示第i个通信子系统所使用向量信令码的码字的数目记为M(i)。
根据至少一种实施方式,对各单位间隔内码字的接收均提供自定时功能。因此,解码器125可将每次前一单位间隔结束后开始的新单位间隔(产生新的码字解码需求)视为其输入端的新码字(即不同于前一码字)。在此类实施方式中,对于每个单位间隔,每个通信子系统内所传输的码字均与前一单位间隔内所发送的码字不同。因此,所有通信子系统可传输的码字数为:
(M(1)-1)*(M(2)-1)*...*(M(k)-1) (式1)
图3所示为历史记录预编码器单元220的实施方式。该单元的一个任务在于,确保在相继的两个单位间隔内不在相应通信线路(也称为子信道)上发送所述向量信令码的相同码字。当所述向量信令码接收器使用比较器检测码字时,上述条件可保证所述比较器中的至少一个比较器的输出值在相继单位间隔之间发生变更。如此,即可利用该值的变化对时钟信息进行恢复,以下将对此进行更加详细的说明。
如图3所示,所述历史记录预编码器单元包括预编码器305以及历史记录存储器单元320。当从全局编码器205接收所述比特b(0),...,b(L-1)分块后,预编码器305利用这些比特以及320中的历史记录比特计算其输出。之后,其将所得比特230发送至编码器105,并同时以这些比特替换历史记录存储器320的值。在下述的一些实施方式中,历史记录存储器320可保持前一时钟周期内发送的向量信令码字,并使用可保证下一发送码字与前一发送码字不同的预编码器。以下,针对各种类型的向量信令码,均给出这一方面的实施例。
类似地,图4所示为历史记录后解码器单元245的实施方式。该单元包括后解码器单元405以及历史记录存储器单元420。当从编码器125接收比特分块240后,所述后解码器根据240中的比特及其历史记录单元420中的比特计算出一个可能为新分块的比特分块,然后将新比特250发送于全局解码器260,并以这些比特替代其历史记录单元中的比特。
图5为全局编码器205例示实施方式的流程图。该全局编码器的主要任务在于,根据给定的比特x(0),...,x(N-1)分块计算出k个比特分块,图2中每个通信子系统对应一个分块,从而使得这些分块可由输入比特200唯一确定,反之亦然。在图5所示流程中,步骤520利用510中的输入比特x(0),...,x(N-1)计算出减模整数y(1),y(2),...,y(k)的二进制表示形式,其中,每个y(i)均为0~M(i)-2(含端点)的整数(需要注意的是y(i)严格小于M(i)-1,因此在本文中称为具有减模),M(i)为图2中第i个通信子系统所使用向量信令码的码字的数目。
可预想到的是,当将一个数转化为其混合基数表示形式(即混合模数),每个位置的数字范围可以为0~M-1,其中模数M由可存在的信号数目M决定。也就是说,如果存在M个可表示上述数字的信号或代码(例如,基数10使用0~9这十个数字,基数5使用0~4这五个数字),典型转化中可使用0~M-1这M个值。然而,需要注意的是,本文中转化所使用的数字为0~M-2,因此相对于一组M个信号或向量代码码字正常情况下应该拥有的模数而言,所使用的模数为减模M-1。以下对使用减模值的优点进行描述。
在步骤520中,上述计算的具体实现方法为对二进制表示形式为x(0),...,x(N-1)的整数X进行表示,其中,x(0)为最低位,x(N-1)为最高位:
如本领域技术人员所知,此计算可通过多种不同算法实现。例如,当0≤X≤257时,N=9,M(1)=M(2)=12,M(3)=6,则我们可得y(1)=X mod 11,y(2)=(X-y(1))/11mod 11,y(3)=(X-y(1)-11*y(2))/121。
图6为预编码单元220的一般流程实施方式概略图。假设图3中历史记录存储器单元320内的比特在图6中表示一个整数,称作h。当接收到作为全局编码器205的第i个输出210的由L个比特y(0,i),...,y(L-1,i)组成的分块时,所述预编码器在步骤620中计算整数b=(y+1+h)mod M(i),其中y为具有二进制表示形式y(0,i),...,y(L-1,i)的整数,M(i)为第i个向量信令码的码字的数目。假设整数h处于0和M(i)-1之间,则其唯一对应第i个向量信令码的一个码字。此外,由于y值在构造上小于M(i)-1(即≤M(i)-2),因此b永远不等于hmod M(i)。由于h对应于最后单位间隔内发送的第i个向量信令码的码字的索引值,而且b对应于当前单位间隔内发送的码字的索引值,因此此类计算可确保不存在两个相同的前后相继码字。在整数y的计算中使用减模使得编码器根据减模数字(y)和前一码字(h)生成不同于该直接相邻的前一码字的输出码字。总之,在将选自于M个码字(0~M-1)的初始码字h在第一信令间隔内发送后,即根据h+1+y选择后一码字,其中,y为取值范围为0~M-2的数据依赖型减模(M-1)整数,从而使得不存在致使所述后一码字等于初始码字h的有效数据依赖型减模整数。
此外,还可使用其他类型的运算或预编码单元。举例而言,当M(i)为2的幂次方时,可利用简单的异或运算确保b和h不相等,这一方面将在后续ENRZ编码器实施例中进行说明。
图7所示为后解码器单元245的运算实施方式。该流程的输入为步骤710中的比特b(0),...,b(R-1)分块。此分块可由图2所示第i个通信子系统的解码器125生成。在步骤720中,所述后解码器单元可使用其历史记录存储单元内的表示整数h的比特计算整数y=(b-1-h)mod M(i),其中,b为具有二进制表示形式b(0),...,b(R-1)的整数。在步骤730中,以b替代所述历史记录值h,同时,将b发送于全局解码器260。
图8所示为全局解码器260的实施方式的运算过程。该流程的输入为y(1),...,y(k),其中每个y(i)均为所述第i个通信子系统的后解码器单元所生成的比特分块。在步骤820中,按照上述(式2)中的公式,根据y(1),..,y(k)算得整数X。该整数的二进制表示形式即为图2中所需的比特270序列。
如上所述,在一些应用中,全局编码器205可仅将输入比特以分组形式发送至相应通信子系统,而且全局解码器260可仅通过对输入比特分块进行收集和衔接而获得比特270。以下,对一些此类实施例进行了讨论。
时钟提取
《Holden I》描述了一种基于比较器的检测器,该检测器用于向量信令码,且设计为使得所有比较器均不产生多义判定条件;也就是说,在任何时候,每一比较器输出如非明确为真,则必明确为假。基于此类代码和检测器的实施方式可与简单的转态检测器联用,从而提取子系统转态信息(本文称之为“边沿信号”),以对如图2中235所示的时钟提取电路进行驱动。下文中详细描述了三种用于此类代码的电路。这些电路在所述文献中称为AH-DF-HPF,UDH-DF-HPF和A-XOR。
在上述文献中称为PCD-DH的第四类时钟提取器使用每码字检测器。此类型检测器与比较器输出中具有多义输出的向量信令码合用。
总体而言,时钟提取实施方式对子系统检测器输出中的变化进行检测。在一些实施方式中,仅对某一有效码字到另一有效码字的变更进行检测,在其他实施方式中,通过向输入信号比较器提供判定反馈和/或迟滞而避免信号反射和噪声所导致的无关转态。其后,可使用包括本领域已知方法在内的多种方法中的任何一种对边沿信号进行分析,以消除近乎同时发生的检测器输出转态所导致的伪影,从而产生衍生自检测器边沿的可靠采样时钟。此方面的一种实施方式中,采用固定或可变延迟级以及简单的状态机,该延迟级和状态机设置为:在发生最终边沿信号转态并经过一固定延迟时间后,生成时钟输出,从而抑制该延迟间隔内的多边沿信号转态效应。
对于本领域技术人员而言容易理解的是,通信信道组内的传播延迟差异(也称偏斜)将使得接收数据的到达时间不同。当此偏斜量较为显著时(即超出一个发送单位间隔),可按照《Holden I》的启示对接收数据总体进行相干重建。
类似地,使用多个子系统的通信系统可通过如下方式生成全局接收时钟:应用将各个子系统接收时钟用作输入的相同边沿信号生成及采样时钟衍生方法;以及生成适于对如图2中270处所获得的接收数据总体进行采样的全局采样时钟。在子系统时钟提取情形中,各子系统结果间偏斜较为显著的实施方式必须对总体或全局解码器输出时钟的生成进行仔细控制,才能使得该全局解码器的所有分量输入均有效,且其结果能满足后续电路所必需的所有设置和保持时间。一些实施方式可要求对子系统结果实施中间保持锁存和/或《Holden I》所描述或一般实际使用的偏斜减轻措施。
时钟提取代码/接收器分类
上述时钟方案所使用的代码及相应接收器可分为两类。第一组代码可称为非多义比较器输出(Unambiguous Comparator Output,UCO)代码/接收器。在此类代码/接收器组合中,所述接收器内使用的二进制或多线比较器电路针对该代码中的每个码字均具有非多义输出。永为UCO码的一例为ENRZ码,也即《Cronie I》所述的H4码,或称尺寸为4的阿达玛码。
第二组代码可称为多义比较器输出(Ambiguous Comparator Output,ACO)代码/接收器。在此类代码/接收器组合中,给定比较器有时具有处于同一电平的多个输入,因此对于一些码字具有多义输出。这些多义输出其后由解码器级进行解析。永为ACO码的一例为《Cronie II》中所述的8b8w码。
在实际实施情形中,大部分代码为UCO码或ACO码。此外,还有数种代码,其一类接收器实现形式为ACO码,而另一类接收器实现形式为UCO码,此类代码一般具有更加复杂的多输入模拟探测器。
AH-DF-HPF——模拟迟滞加判定反馈高通滤波时钟方案
以下时钟方案仅适用于UCO代码/接收器方案。
如图16所示,在最为简单的时钟提取实施方式中,为每个比较器增加模拟迟滞功能,以滤除噪声和反射在线路内引起的多处过零交叉。然而,此类方案具有一些已知缺点。为了正确选择迟滞偏移值,必须获知通信信道内所有反射的最大幅度。已知此类实施方式中,前导边沿所遭受的噪声和反射可导致过早转态,从而使得时间维度上的有效眼开发生闭合,并降低接收器处理高难度通道的能力,因此其将在恢复后的时钟内增加抖动。类似地,所增加的迟滞使得比较器的接收灵敏度下降,从而还减小了幅度维度上的眼开度。最后,此类模拟迟滞实施方式含有闭环电路,该电路在实施时必须多加小心。
所述迟滞比较器的功能可描述如下:
针对每个检测器(detector),均在比较器上施加上述迟滞功能:
HysOffset=以统计或适应性方式确定的超出接收信号内反射及其他噪声源预期幅度的电压值。
C(x)=Hysteresis(detector inputs(x),HysOffset)
在下例中,为了清晰起见,“x”值示为0~2。其为ENRZ码的情形。对于其他UCO代码,“x”的最大范围与比较器数目相等。
通过使用异或函数找出任何线路中发生的变化来生成时钟信号。在每一时钟内,所述代码在一条线路上产生一次转态。
时钟=(C(0)XOR Q(0))OR(C(l)XOR Q(1))OR(C(2)XOR Q(2))
针对每个比较器,均使用标称延迟时间为1/2单位间隔(Unit Interval,UI)的延迟线路进行数据延迟。实际延迟时间可取决于实施状况,而且可稍大于或稍小于1/2UI。
D(0)=HalfUIDelayLine(C(0))
D(l)=HalfUIDelayLine(C(1))
D(2)=HalfUIDelayLine(C(2))
在一些实施方式中,针对每个比较器,均使用D触发器(D Flip-Flop,DFF)或锁存级联对每一比特进行恢复:
Q(0)=DFF(Clock,D(0))
Q(l)=DFF(Clock,D(1))
Q(2)=DFF(Clock,D(2))
/*数据解码及时间重设*/
DecodedData=Decode(Q(0),Q(1),Q(2))
RetimedDecodedData=DFFs(Clock,DecodedData)
UDH-DF-HPF——展开式数字迟滞加判定反馈高通滤波时钟方案
以下时钟方案仅适用于UCO代码/接收器方案。
在图17所示AH-DF-HPF时钟方案实施方式中,进一步实施六次二进制比较,从而使得每次数据比较还可获得迟滞比较的两值。此实施方式的优点为,所述迟滞功能的闭环部分为数字式部分,而且该电路的数据路径部分具有比AH-DF-HPF更高的灵敏度。由于需要额外比较器生成所需迟滞比较,因此该实施方式的缺点包括更大的实施尺寸以及更高的功耗。
在一种实施方式中,使用两个额外的独立比较器在模拟输入中添加或减去一固定值,而非使用模拟迟滞反馈。之后,便可以数字方式实施所述迟滞功能。
在另一实施方式中,使用合并式比较器,该比较器产生三个输出——常规比较器输出;带与偏移值相加后比较结果的输出;带与减去偏移值后比较结果的输出。
本实施例采用带独立比较器的实施方式。在本实施例中,常规比较器Comparator的功能描述如下:
Comparator(Inputs)
比较之前,先由偏移值比较器OffComparator实施运算,以将偏移值与比较器输入相加。其描述如下:
OffComparator(Inputs,HysOffset)
在三比较器代码/接收器方案,例如ENRZ码所用方案中,比较器为:
OffCompOutHigh(0)=OffComparator(Inputs(0),HysOffset)
CompOut(0)=Comparator(Inputs(0))
OffCompOutLow(0)=OffComparator(Inputs(0),-HysOffset)
HysCompOutHigh(1)=OffComparator(Inputs(1),HysOffset)
CompOut(1)=Comparator(Inputs(1))
HysCompOutLow(1)=OffComparator(Inputs(1),-HysOffset)
HysCompOutHigh(2)=OffComparator(Inputs(2),HysOffset)
CompOut(2)=Comparator(Inputs(2))
HysCompOutLow(2)=OffComparator(Inputs(2),-HysOffset)
此电路通过将触发器输出与中心相反一侧的比较器输出相比较的方式恢复时钟:
时钟=((NOT Q(0))ANDCompOutHigh(0))OR(Q(0)AND(NOT CompOutLow(0)))OR((NOTQ(1))AND CompOutHigh(1))OR(Q(1)AND(NOT CompOutLow(1)))OR ((NOT Q(2))ANDCompOutHigh(2))OR(Q(2)AND(NOT CompOutLow(2)))
其余部分与AH-DF-HPF实施方式相同。
A-XOR——模拟异或时钟方案
图18所示为利用模拟异或时钟方案进行时钟提取的实施方式。该实施方式与UCO和ACO代码/接收器方案均相兼容。
每一比较器功能均分为两半。每一比较器的第一半为一个通过线性输出执行该比较器功能的线性低增益比较器。之后,这些线性值中的每一个均通过一个模拟低通滤波器。每一线性值均由作为所述比较功能第二半的模拟异或电路与其自身的模拟低通滤波后形式相比较。模拟异或电路在本领域内广为人知。所述模拟异或电路将产生一个电压输出,当所述输入具有不同值时,该电压输出的值大于其在当所述输入具有相同值时的值。
在此之后,将所述三个模拟异或电路的输出相加。求和器的输出通过限幅增益级,从而使信号具有陡峭的边沿。该信号之后形成所述时钟。
与所述时钟路径并行的是,在数据路径中,所述低增益比较器的输出通过一个增益级,从而形成常规二进制比较器。所述时钟用于对该数据进行采样。
此电路的一个问题在于,其针对某些代码转态所检测出的变化少于针对其他代码转态检测出的变化。此外,该电路对反射和噪声也较敏感。
PCD-DH——每码字检测器,数字迟滞时钟方案
此实施方式与UCO和ACO代码/接收器方案均相兼容。
如图19所示,此时钟提取电路实施方式不使用模拟迟滞电路。相反地,其使用普通比较器1910。其中,使用特制的展开式等延迟数字检测器,该检测器针对每一可用码字均设有一个输出。
这些每码字输出当码字存在于比较器1910的输出端时为高值,而当码字不存在时为低值。上述电路实施为使得每个所述比较器的输出与每个所述每码字检测器的输出之间的延迟大致相等。此类等延迟电路的一例为针对每个码字具有一个与门1920的电路。该与门的引脚数目与比较器的数目相同。该与门引脚的输入端连接于所述比较器的相应真值输出端或补值输出端,在该图中,各与门1920示为具有不同真值输入端和补值输入端。图示具体解码值为示例性而非限制性值。
当上述检测器与ACO码共用时,各每码字检测器仅连接于码字检测时所需的比较器输出端,而不连接于针对码字具有多义值的比较器输出端。
每个所述每码字检测器的输出端连接于D输入端设置为高值的每码字可重置D触发器(或同等电路)的置位输入端。为了说明目的,触发器1930在图19示为边沿触发型置位/复位触发器,其中,当输入S为上升沿时,输出Q为真,当输入R为上升沿时,输出Q为假。如此,一旦与门1920检测到任何码字时,均将使相应触发器1930置位。所有触发器1930的输出一起执行或运算1940后,由延迟线路(DL)1950施加延迟,其中,所述延迟线路通过静态或动态校准而在数据眼图的中心产生上升沿。该上升沿信号用作数据重定时电路内的时钟。此外,该上升沿信号还连接于每个触发器1930的重置输入端,以清空所述检测器,使其用于下一时钟周期。
上述实施方式将对被检测码字时钟周期内的第一次反射进行捕捉,并忽略将导致过零交叉的后续反射。
内存链接
作为应用上述系统和方法的一个具体实施例,本发明的一种实时方式描述为将一个或多个动态随机存储器(Dynamic Random Access Memory,DRAM)单元连接于内存控制器的链接。
传统上,此类链接为面向字节的链接,其中,每个数据字节以单端方式在8条线路中传输,此外,还在第9条线路中传输用于指示在相应内存操作中应用或忽略该数据字节的写屏蔽信号。另外,还具有两条线路,用于提供使用差分信令的选通信号。如《Wiley》和《Cornelius》等现有技术所述,当具有如下能力较为有利:将时钟信息嵌入所述数据内,从而消除对所述独立选通信号的需求。下述各实施例展示了若干向量信令码实施例及其与上述一般原理的联用方式。
为了使图2所示系统可用于此类内存链接,这些应用中的向量信令码字数目必须满足以下不等式:
257≤(M(1)-1)*...*(M(k)-1) (式3)
这是因为,传输8个比特的数据时需要256个不同码字,而且至少需要第257个码字来传输由所述写屏蔽信号实现的对在此内存操作中忽略该数据字节的指示。
实施例1:ENRZ3
如《Cronie I》所述,ENRZ为一种从4×4阿达玛变换得到的向量信令码。其具有在四条线路上传输的8个码字。该8个码字为向量(1,-1/3,-1/3,-1/3)的4种排列形式以及(-1,1/3,1/3,1/3)的4种排列形式。在此情况中,k=3且M(1)=M(2)=M(3)=8,满足(式3)不等式。所得实施方式下称ENRZ3,以指明其具有3个子系统,每个子系统均使用ENRZ向量信令码。
图9所示为其编码器的例示工作方式。全局编码器的输入由与0~256(含端点)的整数(即257个不同值)对应的9个比特x0,x1,...,x8组成。该全局编码器的一种实现形式可如上述图5所示。其生成3个三比特组,分别称为(a0,al,a2),(b0,bl,b2)和(c0,cl,c2),每个ENRZ子系统一个比特组。这些向量中的每一个均对应一个整数对7取模结果的二进制表示形式。这表示这些向量当中没有任何向量由三个“1”组成。每个历史记录单元320均含有与前一单位间隔内传输的比特序列对应的3个比特,分别称为h0,h1和h2。
本实施例中预编码单元305的具体输入特征允许简化,因此与图6所示通用预编码单元运算方式不同。其中,每个预编码单元利用其相应历史记录比特对来自全局编码器205的输入210的补值的异或值进行计算。由于向量210中任何向量均不完全由“1”组成,所以这些向量中任何向量的补值均不完全由“0”组成,从而使得该预编码单元的运算可保证该运算的结果总是相异于相应历史记录单元320内的比特。每个所述预编码单元均将计算出的比特发送于相应ENRZ编码器105,并同时以这些比特替代上述历史记录比特。
在此实施方式中,每个通信子系统在其相应的四线接口上传输3个比特。因此,其线路数为12。每个子系统使用3个多输入比较器(如《Holden I》中所述,也称一般性比较器)以恢复其比特。根据上述文献内容,这些比较器的输出可用于在每个子系统上实施时钟恢复。因此,比较器总数为9。
图10为上述通信系统解码器的接收器部分的一种例示实施方式。运行时,每个ENRZ解码器125向相应后解码器单元405发送一个三比特组240。这些单元先利用其历史记录单元420内的3个比特对所述输入比特实施异或运算,然后对该结果进行补值,并最终将其发送于全局解码器260。同时,其还以被发送的比特替代其3个历史记录比特。
此实施方式中的全局解码器260的运行过程可如图8所示。
如《Hormati》所述,此编码系统的ISI比为1,为可能实现的最低ISI比。这表示此编码系统对ISI噪声较不敏感。该通信系统使用12条信号线路和9个比较器。为了实现高数据速率运行,所述线路必须以3个低偏斜四线组实现布线。
实施例2:S34
S3为一种在3条线路中传输且由向量(+1,0,-1)的6种排列方式组成的向量信令码。在此情形中,我们可将k选为4,以与图2中的4个通信子系统相对应,而且设置M(1)=M(2)=M(3)=M(4)=6,以满足(式3)不等式。所得实施方式在本文中称为S34,以表示其4个子系统中的每个子系统均使用S3向量信令码。此编码方案与《Wiley》所报道方案相类似,但具体编码和解码细节不同。
图11所示为上述编码器的一种实施方式。全局编码器的输入为与0~256(含端点)的整数对应的9个比特x0,x1,...,x8。这表示,当x8=1时,x0=x1=...=x7=0。在此通信系统中,不设置全局编码器单元。相反地,所述输入比特划分为3个两比特组(x0,x1),(x2,x3)和(x4,x5),以及一个三比特组(x6,x7,x8)。由于输入比特的限制,上述第4个比特组对应于0~4(含端点)的整数。
每个历史记录单元320均含有与前一单位间隔内传输的比特序列对应的3个比特,且可被视为整数对6取模后的结果,分别称为h0、h1、h2和h3。
预编码单元305的运行方式如图6所示。每个该预编码单元均将所算出的比特发送于相应S3编码器105,并同时以这些比特替代上述历史记录比特。
在此实施例中,每个通信子系统在其相应的三线接口上利用三元信令传输2个或多个比特。在优选实施方式中,编码器105可通过生成长度为3的两个比特向量而便捷地表示其三元输出,其中,每个比特向量仅具有一个“1”,而且在这些向量中,各个“1”的位置互不对应。运行时,第一比特向量可编码+1在所述S3向量信令码中的位置,第二比特向量可编码-1的位置,从而可理解为+1传输在第一比特向量中1所对应的线路中,-1传输在第二比特向量中1所对应的线路中,0传输在对应上述两比特向量中均不为1的线路中。对熟悉本领域的人员容易理解的是,上述各比特向量可用于驱动输出线路驱动器中的晶体管,以使其生成所需的+1和-1输出信号值。
图12所示为此类编码器的运行过程实施例,其中,图12A和图12B所示为两逻辑电路。此两电路的输入为3个输入比特a,b,c,分别对应于0~5(含端点)的整数,其中a为所述整数的最低位,c为其最高位。图12A电路实际上并不使用输入a,而是将其三个输出计算为NOR(b,c)、b和c。运行时,该电路输出可解读为所选待传输S3码字内+1的位置掩码。图12B电路对上述3个输入全部使用,并自上而下输出逻辑函数和NOR(c,a^b),其中,为x的补值,x^y为x和y的异或运算结果,x&y为x和y的逻辑与运算结果,NOR(x,y)为x和y的或非运算结果。所示电路仅为一种示例,本领域技术人员了解许多其他方案。
图13给出了图1解码器125用于S3编码情形的一种例示实施方式。三条通信线路S3D01、S3D02和S3D03连入比较器S3D20、S3D25和S3D30的网络。运行时,当线路S3D01上的值大于线路S3D02上的值时,S3D20生成输出“0”,否则该输出为“1”。类似地,当且仅当线路S3D01上的值大于线路S3D03上的值时,S3D25的输出为“0”,而且当且仅当线路S3D02上的值大于线路S3D03上的值时,S3D30的输出为“0”。解码器125电路将其第一输出计算为值B&C,将其第二输出计算为值A^B^C,且将其第三输出计算为值其中,A、B和C分别为单元S3D20、S3D25和S3D30的输出。
此实施方式中后解码器单元的运行过程如图7所示。由于,各后解码器单元的比特输出可通过简单相互衔接而重新生成图2输出比特270,因此无需设置明确的全局解码器。
此编码系统的ISI比为2。这表示,与ENRZ3相比,该编码系统更易受ISI噪声影响。此通信系统使用12条信号线路和12个比较器。所述线路必须以4个低偏斜三线组实现布线。
实施例3:S42×P3码
S4码为一种在4条线路中传输且由向量(+1,0,0,-1)的12种不同排列方式组成的向量信令码。该代码可使用6对成对比较器进行检测,且其ISI比为2。
P3码为一种在3条线路中传输且由(1,0,-1),(-1,0,1),(0,1,-1)和(0,-1,1)这4个码字组成的向量信令码。这些码字可通过以比较器x-y和(x+y)/2-z处理所述3条线路的所接收信号(x,y,z)的方式进行检测。该代码的ISI比为1。
对于图2通信系统,我们将通信子系统的数目选为3,即k=3,其中,前两个通信子系统使用S4向量信令码,第三个子系统使用P3向量信令码。我们令M(1)=M(2)=12,且M(3)=4,从而满足(式3)不等式。所得代码称为S42×P3。
图2中全局编码器205和图2中全局解码器260可分别按照图5和图8所示流程工作。此外,历史记录预编码和后编码单元220和245可分别按照图3和图4所示流程工作。
图14给出了S4码编码器的一种实施方式。该编码器分别通过上方和下方的电路并根据输入a,b,c,d生成两个比特向量(p0,p1,p2,p3)和(m0,m1,m2,m3),所述输入表示一个0~11(含端点)的整数,其中,a为该整数的最低位,而d为其最高位。比特序列(p0,p1,p2,p3)为相应S4码字中+1的位置掩码,而(m0,m1,m2,m3)为该码字中-1的位置掩码。
图15给出了P3码编码器的一种实施方式。与S4编码器相类似,该编码器根据输入a和b生成两个比特向量(p0,p1)和(m0,m1)。这些向量分别为相应P3码字中+1和-1的位置掩码。
上述各例示实施方式仅用于说明目的。其还可通过本领域熟知的方法得到进一步优化。
上述编码系统的ISI比为2。这表明,该编码系统对ISI噪声的敏感度高于ENRZ3方案,但与S34对ISI噪声的敏感度相类似。这一方面通过下述统计模拟结果得到证实。
该通信系统使用11条信号线路和14个比较器。所述线路必须以2个低偏斜四线组以及1个低偏斜三线组实现布线。
实施例:OCT3
OCT为一种在3条线路中传输且由((0.6,-1,0.4),((-0.2,-0.8,1),((-0.8,-0.2,1),((1,-0.6,-0.4)这8个码字组成的向量信令码。该代码可通过以x-y,(x+2*z)/3-y,(y+2*z)/3-x和(x+y)/2-1这4个比较器处理代表了所述3条接口线路接收值的输入(x,y,z)的方式进行检测。该代码的首次描述见于《Shokrollahi I》。
对于图2通信系统,我们将通信子系统的数目选为3,即k=3,每个通信子系统均使用OCT向量信令码。我们还令M(1)=M(2)=M(3)=8,从而满足(式3)不等式。所得代码称为OCT3。
在第一实施方式中,图2中全局编码器205和图2中全局解码器260分别按照图5和图8所示流程工作,而且历史记录预编码和后编码单元220和245分别按照图3和图4所示流程工作。在一替代实施方式中,历史记录预编码和后编码单元220和245分别按照图9和图10所示ENRZ3流程工作。
此编码系统的ISI比为8/3。这表明,该编码系统对ISI噪声的敏感度高于所有上述系统。这一方面通过下述统计模拟结果得到证实。该通信系统使用9条信号线路和12个比较器。所述线路必须以3个低偏斜三线组实现布线。
实施例:C182
C18码为一种在4条线路中传输且由以下18个码字组成的向量信令码。(-1,1/3,-1/3,1),(-1,1/3,1,-1/3),(-1,1,-1/3,1/3),(-1,1,13,-1/3),(-1/3,1,-1,1/3),(-1/3,1,1/3,-1),(1/3,-1,-1/3,1),(1/3,-1,1,-1/3),(1,-1,-1/3,1/3),(1,-1,1/3,-1/3),(1,-1/3,-1,1/3),(1,-1/3,1/3,-1),(-1,-1/3,1/3,1),(-1,-1/3,1,1/3),(-1/3,1/3,-1,1),(-1/3,1/3,1,-1),(1/3,1,-1,-1/3),(1/3,1,-1/3,-1).
该代码可通过以x-z,x-u,y-z,y-u和z-u这5个比较器处理代表了所述4条接口线路接收值的输入(x,y,z,u)的方式进行检测。该代码由《Shokrollahi II》首次披露。
对于图2通信系统,我们将通信子系统的数目选为2,即k=2,每个通信子系统均使用C18向量信令码。我们还令M(1)=M(2)=18,从而满足(式3)不等式。所得代码称为C182。
此通信系统可构建为不使用全局编码器单元或全局解码器单元。历史记录预编码和后编码单元220和245可分别按照图3和图4所示流程工作。
此编码系统的ISI比为3。这表明,该编码系统对ISI噪声的敏感度高于所有上述系统。这一方面通过下述统计模拟结果得到证实。该通信系统使用8条信号线路和10个比较器。所述线路必须以2个低偏斜四线组实现布线。
统计模拟
在以下模拟中,我们将高低电平之间的峰间电压选为200mV,所使用信道模型以传统集成电路器件间所布微芯片通信信道特征为基础。所使用的唯一均衡手段为具有一个前导和一个后导的Tx FIR。所述信道代表实际移动DRAM信道,其信号发送速率为7G波特/秒(bps),且接口在每个单位间隔内传输一个完整字节(加上掩码)。因此,总吞吐量为56Gbps。
所述模拟由Kandou Bus专有的统计眼图程序软件完成,该软件称为“KEYE”。所有所得眼图的最小水平眼开度和最小垂直眼开度记于表1。在多数情况下,上述两最小值并不发生于同一开眼区。
表1
可以看出且预期到的是,最小水平眼开度为ISI比的递减函数。ENRZ3之外的所有代码均因更高的串扰和更低的容限而使得垂直眼开度减小。
多相实施方式
以上所述每一实施例均存在一种可替代实施方式,该实施方式可通过并行方式实现更高运行速度,通常称为多相实施方式。在一些实施方式中,为了促进环路展开,可以更便捷的方式使得图3所示编码器和预编码器位置反转。
在一种实施方式中,例示发送编码功能如图20所示,例示接收解码功能如图22所示,所述编码功能分为开环和闭环两部分。如此划分的目的在于,为了使所述闭环部分尽可能地小,从而可实现最高的运行速度。该闭环部分使用线路中所发信号的历史记录信息。在一种实施方式中,所述闭环电路使用以往时钟时间的样本。上述电路的开环部分并不对线路中的历史记录信息施加作用。
由于该电路的开环部分并不使用历史记录信息,因此正如图21中例示发送编码功能和图23中例示接收解码功能所示,在一种实施方式中,可采用并行运行的多个上述电路。这通常称为多相电路,其原因在于,所述并行电路的输入馈入与输出生成在时间上与其他并行电路(如不同电路相的此类电路)之间设有偏移。
上述并行运行方式可显著提高所述开环编码电路的吞吐量。在此之后,上述各并行电路的输出可通过多路复合恢复为一个可由所述闭环编码电路处理的输出。
在发送器中,所述并行开环编码电路必须实施的操作为,将数据输入b(0)~b(L-1)分解为具有M(K)-1个状态的分块。
所述闭环编码电路实施的操作为,将所述向量与前一发送向量相比较。如果两向量相同,则以预设重复码代替所述向量。
在接收器中,所述闭环解码电路必须实施的操作为,将所接收向量与所述重复码相比较。如果两向量相同,则以该重复码的上一接收向量代替所述向量。
所述并行开环解码电路必须实施的操作为,将具有M(K)-1个状态的各向量重新组合为b(0)~b(L-1)的数据输出。
一般开环和闭环操作
所述编码器和解码器电路的开环和闭环部分之间的任务分配可实现作用于接口高频层面的向量信令码的高速运行。举例而言,使用《Fox I》中TL-3和TL-4码的实施方式可划分为开环和闭环部分,从而可实现更高的速度,其中,该速度也可通过其他方式实现。这两代码并不实施时钟编码,而是通过降低向量信令的高频频谱内容而降低其功耗。
实施方式
在一种发送器实施方式中,发送器包括:全局发送编码器,该全局发送编码器用于接收待分配至一通信信道的两个或更多个子信道的输入数据并生成一组减模子信道发送数据;以及用于所述两个或更多个子信道中每个子信道的通信子系统,每个所述通信子系统包括:数据历史记录预编码器,该数据历史记录预编码器用于从所述全局发送编码器接收所述一组减模子信道发送数据中的相应一个,并根据所述减模子信道发送数据以及前一码字生成子信道发送数据,从而通过不会在相邻信令间隔内发送同一给定码字的方式实现信令转态;数据编码器,该数据编码器用于将所述子信道发送数据编码为向量信令码的码字;以及驱动器,该驱动器用于在所述子信道上生成代表向量信令码的物理信号。
在一种此类发送器实施方式中,所述全局发送编码器对所述输入数据实施运算,以生成待分配至所述两个或更多个子信道的多个结果。
在一种此类发送器实施方式中,所述数据编码器中的每一个保持有至少一个以往发送间隔的历史记录,以保证其子信道发送数据在每个发送间隔内均发生变化。
在一种此类发送器实施方式中,每个子信道的向量信令码为ENRZ、S3、OCT、C18、S4或P3。
在一种此类发送器实施方式中,至少一个通信子系统的向量信令码为S4,且至少一个其他通信子系统的向量信令码为P3。
在一种此类发送器实施方式中,所述数据编码器中的每一个保持有至少一个以往发送间隔的历史记录,以保证其发送向量在每个发送间隔内均发生变化。在另一此类实施方式中,所述发送器实施为具有并行设置的所述数据历史记录预编码器。
在一种接收器实施方式中,接收器包括:电路,该电路用于接收通信子信道内的物理信号;数据解码器,该数据解码器用于对代表向量信令码的所述接收信号进行解码;数据后解码器,该数据后解码器用于接收解码后的所述接收信号并生成接收子系统数据;以及全局解码器,该全局解码器用于接收从所述两个或更多个通信子系统中的每一个所接收的且待重组为一组输入数据的所述接收子系统数据。
在一种此类接收器实施方式中,至少每个通信子信道接收器的定时信息衍生自其通信子信道内的信号转态。
在一种此类接收器实施方式中,所述全局解码器对所述接收子系统数据实施补值运算,以获得所述输入数据的所接收的形式。
在一种此类接收器实施方式中,每个所述数据后解码器保持有至少一个以往接收间隔的历史记录,以从解码后的所述接收信号准确生成所述接收子系统数据。
在一种此类接收器实施方式中,至少一个所述通信子信道接收器的定时信息衍生自由相应子信道发送数据的预编码生成的接收信号转态。
在一种此类接收器实施方式中,所述全局解码器的定时信息获得自至少一个子信道接收器的定时信息。
在一种此类接收器实施方式中,所述数据编码器中的每一个保持有至少一个以往接收间隔的历史记录,以准确地将数据发送给后解码器。
在一种此类接收器实施方式中,所述接收器实施为具有并行设置的所述后解码器。
在一种此类接收器实施方式中,所述接收器还包括时钟提取电路,其中,该时钟提取电路还包括选自模拟迟滞、判定反馈、数字判定反馈、偏移值比较器、模拟异或逻辑、每码字检测器逻辑和每码字触发器中的一个或多个实现形式。在另一此类实施方式中,所述每码字触发器的输出相互结合后通过一延迟线路电路。在另一此类实施方式中,所述延迟线路的输出用于清空所述每码字触发器。
在一种实施方式中,图24所示的一种方法2400包括:在框体2402中,处理输入数据,并将所述输入数据划分后分配至两个或更多个子信道,每个子信道包括多条信号线路;对所述两个或更多个子信道中的每个子信道,以基本并行的方式实施如下步骤:在框体2406中,对输入数据的一部分进行预编码,并将其分配至相应子信道,以生成子信道发送数据;在框体2410中,将所述子信道发送数据编码为向量信令码的码字;以及在框体2414中,在所述子信道上对表示所述码字的物理信号进行驱动。
在图25所示的一种实施方式中,一种方法包括:在框体2505中,检测两个或更多个通信子信道内的物理信号,以生成接收信号,每个子信道包括多条信号线路;在框体2510中,对所述两个或更多个子信道中的每个子信道,从相应子信道编码的向量信令码中衍生出定时信息;对所述两个或更多个子信道中的每个子信道,在框体2515中,将所述接收信号解码为具有M个元素的向量信令码的表示形式;在框体2520中,对所述两个或更多个子信道中的每个子信道,生成表示减模(M-1)数据的接收子系统数据;以及在框体2525中,对所述两个或更多个子信道中的每个子信道的所述接收子系统数据进行处理,以生成输入数据输出的接收形式。
Claims (15)
1.一种用于通过一通信信道的两个或更多个子信道发送信息的发送器,其特征在于,包括:
全局发送编码器,用于接收待分配至一通信信道的两个或更多个子信道的输入数据并生成一组减模子信道发送数据,每个子信道包括多条信号线路;
用于所述两个或更多个子信道中每个子信道的通信子系统,每个所述通信子系统包括:
数据历史记录预编码器,用于从所述全局发送编码器接收所述一组减模子信道发送数据中的相应一个,并根据所述相应的减模子信道发送数据以及前一码字生成子信道发送数据,从而通过不会在相邻信令间隔内发送同一给定码字的方式实现信令转态;
数据编码器,用于将所述子信道发送数据编码为向量信令码的码字;以及
驱动器,用于在所述子信道的所述多条信号线路上生成表示所述向量信令码的物理信号。
2.如权利要求1所述的发送器,其特征在于,所述全局发送编码器对所述输入数据实施运算,以生成待分配至所述两个或更多个子信道的多个结果。
3.如权利要求1所述的发送器,其特征在于,所述数据历史记录预编码器中的每一个保持有至少一个以往发送间隔的历史记录,以保证其子信道发送数据在每个发送间隔内均发生变化。
4.如权利要求1所述的发送器,其特征在于,每个子信道的向量信令码为ENRZ、S3、OCT、C18、S4或P3。
5.如权利要求1所述的发送器,其特征在于,至少一个通信子系统的向量信令码为S4,且至少一个其他通信子系统的向量信令码为P3。
6.如权利要求1所述的发送器,其特征在于,所述数据编码器中的每一个保持有至少一个以往发送间隔的历史记录,以保证其发送向量在每个发送间隔内均发生变化。
7.如权利要求1所述的发送器,其特征在于,该发送器实施为具有并行设置的所述数据历史记录预编码器。
8.如权利要求1所述的发送器,其特征在于,还包括:
两个或更多个接收子系统,每个接收子系统包括:
接收电路,用于接收一接收子信道内的物理接收信号;
数据解码器,用于对接收信号进行解码,所述接收信号代表向量信令码的接收码字;
数据后解码器,用于接收解码后的所述接收信号并生成接收子系统数据;以及
全局解码器,用于从所述两个或更多个接收子系统中的每一个接收子系统数据,所述子系统数据用于重组为第二组输入数据的接收形式。
9.一种用于通过一通信信道的两个或更多个子信道发送信息的方法,其特征在于,包括:
将待分配至两个或更多个子信道的输入数据处理成一组减模子信道发送数据,每个子信道包括多条信号线路;对所述两个或更多个子信道中的每个子信道,以并行的方式实施如下步骤:
根据所述一组减模子信道发送数据中的相应一个以及前一码字,对输入数据的分配至相应子信道的部分进行预编码,以生成子信道发送数据,从而通过不会在相邻信令间隔内发送同一给定码字的方式实现信令转态;
将所述子信道发送数据编码为向量信令码的码字;以及
在所述子信道上对表示所述码字的物理信号进行驱动。
10.如权利要求9所述的方法,其特征在于,对输入数据进行处理包括对所述输入数据实施运算,以生成待分配至所述两个或更多个子信道的多个结果。
11.如权利要求9所述的方法,其特征在于,所述预编码包括保持至少一个以往发送间隔的历史记录,以保证其子信道发送数据在每个发送间隔内均发生变化。
12.如权利要求9所述的方法,其特征在于,每个子信道的向量信令码为ENRZ、S3、OCT、C18、S4或P3。
13.如权利要求9所述的方法,其特征在于,至少一个通信子系统的向量信令码为S4,且至少一个其他通信子系统的向量信令码为P3。
14.如权利要求9所述的方法,其特征在于,对所述子信道发送数据编码包括保持至少一个以往发送间隔的历史记录,以保证其发送向量在每个发送间隔内均发生变化。
15.如权利要求9所述的方法,其特征在于,所述预编码以并行的方式执行。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US201461946574P | 2014-02-28 | 2014-02-28 | |
US61/946,574 | 2014-02-28 | ||
PCT/US2015/018363 WO2015131203A1 (en) | 2014-02-28 | 2015-03-02 | Clock-embedded vector signaling codes |
Publications (2)
Publication Number | Publication Date |
---|---|
CN106105123A CN106105123A (zh) | 2016-11-09 |
CN106105123B true CN106105123B (zh) | 2019-06-28 |
Family
ID=52693057
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201580010265.2A Active CN106105123B (zh) | 2014-02-28 | 2015-03-02 | 用于发送时钟嵌入式向量信令码的方法和系统 |
Country Status (5)
Country | Link |
---|---|
US (5) | US9363114B2 (zh) |
EP (2) | EP3111607B1 (zh) |
KR (1) | KR102240544B1 (zh) |
CN (1) | CN106105123B (zh) |
WO (1) | WO2015131203A1 (zh) |
Families Citing this family (53)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9288089B2 (en) | 2010-04-30 | 2016-03-15 | Ecole Polytechnique Federale De Lausanne (Epfl) | Orthogonal differential vector signaling |
US9985634B2 (en) | 2010-05-20 | 2018-05-29 | Kandou Labs, S.A. | Data-driven voltage regulator |
US9288082B1 (en) | 2010-05-20 | 2016-03-15 | Kandou Labs, S.A. | Circuits for efficient detection of vector signaling codes for chip-to-chip communication using sums of differences |
US9246713B2 (en) | 2010-05-20 | 2016-01-26 | Kandou Labs, S.A. | Vector signaling with reduced receiver complexity |
US9251873B1 (en) | 2010-05-20 | 2016-02-02 | Kandou Labs, S.A. | Methods and systems for pin-efficient memory controller interface using vector signaling codes for chip-to-chip communications |
US9106220B2 (en) | 2010-05-20 | 2015-08-11 | Kandou Labs, S.A. | Methods and systems for high bandwidth chip-to-chip communications interface |
US9077386B1 (en) | 2010-05-20 | 2015-07-07 | Kandou Labs, S.A. | Methods and systems for selection of unions of vector signaling codes for power and pin efficient chip-to-chip communication |
US9268683B1 (en) | 2012-05-14 | 2016-02-23 | Kandou Labs, S.A. | Storage method and apparatus for random access memory using codeword storage |
CN104995612B (zh) | 2013-01-17 | 2020-01-03 | 康杜实验室公司 | 低同步开关噪声芯片间通信方法和系统 |
KR102241045B1 (ko) | 2013-04-16 | 2021-04-19 | 칸도우 랩스 에스에이 | 고 대역폭 통신 인터페이스를 위한 방법 및 시스템 |
EP2997704B1 (en) | 2013-06-25 | 2020-12-16 | Kandou Labs S.A. | Vector signaling with reduced receiver complexity |
US9806761B1 (en) | 2014-01-31 | 2017-10-31 | Kandou Labs, S.A. | Methods and systems for reduction of nearest-neighbor crosstalk |
WO2015117102A1 (en) | 2014-02-02 | 2015-08-06 | Kandou Labs SA | Method and apparatus for low power chip-to-chip communications with constrained isi ratio |
EP3111607B1 (en) | 2014-02-28 | 2020-04-08 | Kandou Labs SA | Clock-embedded vector signaling codes |
US9509437B2 (en) | 2014-05-13 | 2016-11-29 | Kandou Labs, S.A. | Vector signaling code with improved noise margin |
US11240076B2 (en) | 2014-05-13 | 2022-02-01 | Kandou Labs, S.A. | Vector signaling code with improved noise margin |
US9852806B2 (en) | 2014-06-20 | 2017-12-26 | Kandou Labs, S.A. | System for generating a test pattern to detect and isolate stuck faults for an interface using transition coding |
US9112550B1 (en) | 2014-06-25 | 2015-08-18 | Kandou Labs, SA | Multilevel driver for high speed chip-to-chip communications |
KR102288337B1 (ko) | 2014-07-10 | 2021-08-11 | 칸도우 랩스 에스에이 | 증가한 신호대잡음 특징을 갖는 벡터 시그널링 코드 |
US9432082B2 (en) | 2014-07-17 | 2016-08-30 | Kandou Labs, S.A. | Bus reversable orthogonal differential vector signaling codes |
US9444654B2 (en) | 2014-07-21 | 2016-09-13 | Kandou Labs, S.A. | Multidrop data transfer |
KR101949964B1 (ko) | 2014-08-01 | 2019-02-20 | 칸도우 랩스 에스에이 | 임베딩된 클록을 갖는 직교 차동 벡터 시그널링 코드 |
US9674014B2 (en) | 2014-10-22 | 2017-06-06 | Kandou Labs, S.A. | Method and apparatus for high speed chip-to-chip communications |
WO2016210445A1 (en) | 2015-06-26 | 2016-12-29 | Kandou Labs, S.A. | High speed communications system |
US9984035B2 (en) | 2015-08-27 | 2018-05-29 | Qualcomm Incorporated | Efficient encoding and decoding architecture for high-rate data transfer through a parallel bus |
US10055372B2 (en) | 2015-11-25 | 2018-08-21 | Kandou Labs, S.A. | Orthogonal differential vector signaling codes with embedded clock |
EP3408935B1 (en) | 2016-01-25 | 2023-09-27 | Kandou Labs S.A. | Voltage sampler driver with enhanced high-frequency gain |
EP3826184A1 (en) | 2016-04-22 | 2021-05-26 | Kandou Labs, S.A. | High performance phase locked loop |
US10003454B2 (en) | 2016-04-22 | 2018-06-19 | Kandou Labs, S.A. | Sampler with low input kickback |
EP3449606A4 (en) | 2016-04-28 | 2019-11-27 | Kandou Labs S.A. | LOW POWER MULTILAYER ATTACK CIRCUIT |
US10153591B2 (en) | 2016-04-28 | 2018-12-11 | Kandou Labs, S.A. | Skew-resistant multi-wire channel |
CN109313622B (zh) * | 2016-04-28 | 2022-04-15 | 康杜实验室公司 | 用于密集路由线组的向量信令码 |
US9906358B1 (en) | 2016-08-31 | 2018-02-27 | Kandou Labs, S.A. | Lock detector for phase lock loop |
US10411922B2 (en) | 2016-09-16 | 2019-09-10 | Kandou Labs, S.A. | Data-driven phase detector element for phase locked loops |
US10200188B2 (en) | 2016-10-21 | 2019-02-05 | Kandou Labs, S.A. | Quadrature and duty cycle error correction in matrix phase lock loop |
US10200218B2 (en) | 2016-10-24 | 2019-02-05 | Kandou Labs, S.A. | Multi-stage sampler with increased gain |
US10372665B2 (en) | 2016-10-24 | 2019-08-06 | Kandou Labs, S.A. | Multiphase data receiver with distributed DFE |
CN110741562B (zh) | 2017-04-14 | 2022-11-04 | 康杜实验室公司 | 向量信令码信道的流水线式前向纠错 |
US10693473B2 (en) | 2017-05-22 | 2020-06-23 | Kandou Labs, S.A. | Multi-modal data-driven clock recovery circuit |
US10116468B1 (en) | 2017-06-28 | 2018-10-30 | Kandou Labs, S.A. | Low power chip-to-chip bidirectional communications |
US10686583B2 (en) | 2017-07-04 | 2020-06-16 | Kandou Labs, S.A. | Method for measuring and correcting multi-wire skew |
US10693587B2 (en) | 2017-07-10 | 2020-06-23 | Kandou Labs, S.A. | Multi-wire permuted forward error correction |
US10203226B1 (en) | 2017-08-11 | 2019-02-12 | Kandou Labs, S.A. | Phase interpolation circuit |
US10256795B1 (en) * | 2017-10-11 | 2019-04-09 | Micron Technology, Inc. | Pipelined latches to prevent metastability |
US10326623B1 (en) | 2017-12-08 | 2019-06-18 | Kandou Labs, S.A. | Methods and systems for providing multi-stage distributed decision feedback equalization |
US10467177B2 (en) | 2017-12-08 | 2019-11-05 | Kandou Labs, S.A. | High speed memory interface |
CN111684772B (zh) * | 2017-12-28 | 2023-06-16 | 康杜实验室公司 | 同步切换多输入解调比较器 |
US10243614B1 (en) | 2018-01-26 | 2019-03-26 | Kandou Labs, S.A. | Method and system for calibrating multi-wire skew |
US10554380B2 (en) | 2018-01-26 | 2020-02-04 | Kandou Labs, S.A. | Dynamically weighted exclusive or gate having weighted output segments for phase detection and phase interpolation |
US11088878B2 (en) * | 2020-01-03 | 2021-08-10 | Korea University Research And Business Foundation | Transceiver using multi-level braid signaling and method of operating the same |
US20210342285A1 (en) * | 2020-04-30 | 2021-11-04 | Advanced Micro Devices, Inc. | Encoding of symbols for a computer interconnect based on frequency of symbol values |
US11545980B1 (en) * | 2021-09-08 | 2023-01-03 | Qualcomm Incorporated | Clock and data recovery for multi-phase, multi-level encoding |
US11831472B1 (en) | 2022-08-30 | 2023-11-28 | Kandou Labs SA | Pre-scaler for orthogonal differential vector signalling |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6084883A (en) * | 1997-07-07 | 2000-07-04 | 3Com Corporation | Efficient data transmission over digital telephone networks using multiple modulus conversion |
US6954492B1 (en) * | 2000-04-19 | 2005-10-11 | 3Com Corporation | Method of differential encoding a precoded multiple modulus encoder |
Family Cites Families (453)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US668687A (en) | 1900-12-06 | 1901-02-26 | Louis G Mayer | Thill-coupling. |
US780883A (en) | 1903-11-18 | 1905-01-24 | Mortimer Livingston Hinchman | Advertising device. |
US3196351A (en) | 1962-06-26 | 1965-07-20 | Bell Telephone Labor Inc | Permutation code signaling |
US3636463A (en) | 1969-12-12 | 1972-01-18 | Shell Oil Co | Method of and means for gainranging amplification |
US3939468A (en) | 1974-01-08 | 1976-02-17 | Whitehall Corporation | Differential charge amplifier for marine seismic applications |
US3970795A (en) | 1974-07-16 | 1976-07-20 | The Post Office | Measurement of noise in a communication channel |
JPS5279747A (en) | 1975-12-26 | 1977-07-05 | Sony Corp | Noise removal circuit |
US4206316A (en) | 1976-05-24 | 1980-06-03 | Hughes Aircraft Company | Transmitter-receiver system utilizing pulse position modulation and pulse compression |
US4181967A (en) | 1978-07-18 | 1980-01-01 | Motorola, Inc. | Digital apparatus approximating multiplication of analog signal by sine wave signal and method |
US4276543A (en) | 1979-03-19 | 1981-06-30 | Trw Inc. | Monolithic triple diffusion analog to digital converter |
US4486739A (en) | 1982-06-30 | 1984-12-04 | International Business Machines Corporation | Byte oriented DC balanced (0,4) 8B/10B partitioned block transmission code |
US4499550A (en) | 1982-09-30 | 1985-02-12 | General Electric Company | Walsh function mixer and tone detector |
US4722084A (en) | 1985-10-02 | 1988-01-26 | Itt Corporation | Array reconfiguration apparatus and methods particularly adapted for use with very large scale integrated circuits |
US4772845A (en) | 1987-01-15 | 1988-09-20 | Raytheon Company | Cable continuity testor including a sequential state machine |
US4864303A (en) | 1987-02-13 | 1989-09-05 | Board Of Trustees Of The University Of Illinois | Encoder/decoder system and methodology utilizing conservative coding with block delimiters, for serial communication |
US4774498A (en) | 1987-03-09 | 1988-09-27 | Tektronix, Inc. | Analog-to-digital converter with error checking and correction circuits |
US5053974A (en) | 1987-03-31 | 1991-10-01 | Texas Instruments Incorporated | Closeness code and method |
US4897657A (en) | 1988-06-13 | 1990-01-30 | Integrated Device Technology, Inc. | Analog-to-digital converter having error detection and correction |
US7421633B2 (en) | 2005-03-21 | 2008-09-02 | Texas Instruments Incorporated | Controller receiving combined TMS/TDI and suppyling separate TMS and TDI |
US4974211A (en) | 1989-03-17 | 1990-11-27 | Hewlett-Packard Company | Digital ultrasound system with dynamic focus |
US5168509A (en) | 1989-04-12 | 1992-12-01 | Kabushiki Kaisha Toshiba | Quadrature amplitude modulation communication system with transparent error correction |
FR2646741B1 (fr) | 1989-05-03 | 1994-09-02 | Thomson Hybrides Microondes | Echantillonneur-bloqueur a haute frequence d'echantillonnage |
US5172280A (en) | 1989-10-26 | 1992-12-15 | Archive Corporation | Apparatus and method for automatic write current calibration in a streaming tape drive |
US5599550A (en) | 1989-11-18 | 1997-02-04 | Kohlruss; Gregor | Disposable, biodegradable, wax-impregnated dust-cloth |
US5166956A (en) | 1990-05-21 | 1992-11-24 | North American Philips Corporation | Data transmission system and apparatus providing multi-level differential signal transmission |
US5266907A (en) | 1991-06-25 | 1993-11-30 | Timeback Fll | Continuously tuneable frequency steerable frequency synthesizer having frequency lock for precision synthesis |
US5287305A (en) | 1991-06-28 | 1994-02-15 | Sharp Kabushiki Kaisha | Memory device including two-valued/n-valued conversion unit |
EP0543070A1 (en) | 1991-11-21 | 1993-05-26 | International Business Machines Corporation | Coding system and method using quaternary codes |
US5626651A (en) | 1992-02-18 | 1997-05-06 | Francis A. L. Dullien | Method and apparatus for removing suspended fine particles from gases and liquids |
US5311516A (en) | 1992-05-29 | 1994-05-10 | Motorola, Inc. | Paging system using message fragmentation to redistribute traffic |
US5283761A (en) | 1992-07-22 | 1994-02-01 | Mosaid Technologies Incorporated | Method of multi-level storage in DRAM |
US5412689A (en) | 1992-12-23 | 1995-05-02 | International Business Machines Corporation | Modal propagation of information through a defined transmission medium |
US5511119A (en) | 1993-02-10 | 1996-04-23 | Bell Communications Research, Inc. | Method and system for compensating for coupling between circuits of quaded cable in a telecommunication transmission system |
FR2708134A1 (fr) | 1993-07-22 | 1995-01-27 | Philips Electronics Nv | Circuit échantillonneur différentiel. |
US5459465A (en) | 1993-10-21 | 1995-10-17 | Comlinear Corporation | Sub-ranging analog-to-digital converter |
US5461379A (en) | 1993-12-14 | 1995-10-24 | At&T Ipm Corp. | Digital coding technique which avoids loss of synchronization |
US5449895A (en) | 1993-12-22 | 1995-09-12 | Xerox Corporation | Explicit synchronization for self-clocking glyph codes |
US5553097A (en) | 1994-06-01 | 1996-09-03 | International Business Machines Corporation | System and method for transporting high-bandwidth signals over electrically conducting transmission lines |
JP2710214B2 (ja) | 1994-08-12 | 1998-02-10 | 日本電気株式会社 | フェーズロックドループ回路 |
GB2305036B (en) | 1994-09-10 | 1997-08-13 | Holtek Microelectronics Inc | Reset signal generator |
US5566193A (en) | 1994-12-30 | 1996-10-15 | Lucent Technologies Inc. | Method and apparatus for detecting and preventing the communication of bit errors on a high performance serial data link |
US5659353A (en) | 1995-03-17 | 1997-08-19 | Bell Atlantic Network Services, Inc. | Television distribution system and method |
SG82563A1 (en) | 1995-07-07 | 2001-08-21 | Sun Microsystems Inc | An apparatus and method for packetizing and segmenting mpeg packets |
US5875202A (en) | 1996-03-29 | 1999-02-23 | Adtran, Inc. | Transmission of encoded data over reliable digital communication link using enhanced error recovery mechanism |
US5825808A (en) | 1996-04-04 | 1998-10-20 | General Electric Company | Random parity coding system |
US6242321B1 (en) | 1996-04-23 | 2001-06-05 | International Business Machines Corporation | Structure and fabrication method for non-planar memory elements |
US5889981A (en) | 1996-05-07 | 1999-03-30 | Lucent Technologies Inc. | Apparatus and method for decoding instructions marked with breakpoint codes to select breakpoint action from plurality of breakpoint actions |
US5856935A (en) | 1996-05-08 | 1999-01-05 | Motorola, Inc. | Fast hadamard transform within a code division, multiple access communication system |
US5727006A (en) | 1996-08-15 | 1998-03-10 | Seeo Technology, Incorporated | Apparatus and method for detecting and correcting reverse polarity, in a packet-based data communications system |
US5999016A (en) | 1996-10-10 | 1999-12-07 | Altera Corporation | Architectures for programmable logic devices |
US5982954A (en) | 1996-10-21 | 1999-11-09 | University Technology Corporation | Optical field propagation between tilted or offset planes |
US5949060A (en) | 1996-11-01 | 1999-09-07 | Coincard International, Inc. | High security capacitive card system |
US5802356A (en) | 1996-11-13 | 1998-09-01 | Integrated Device Technology, Inc. | Configurable drive clock |
EP0844740B1 (en) | 1996-11-21 | 2003-02-26 | Matsushita Electric Industrial Co., Ltd. | A/D converter and A/D conversion method |
US5995016A (en) | 1996-12-17 | 1999-11-30 | Rambus Inc. | Method and apparatus for N choose M device selection |
US6005895A (en) | 1996-12-20 | 1999-12-21 | Rambus Inc. | Apparatus and method for multilevel signaling |
DE69731074T2 (de) | 1997-04-30 | 2005-10-06 | Hewlett-Packard Development Co., L.P., Houston | Anordnung und Verfahren zur Übertragung von Daten über eine Vielzahl von Kanälen |
US6247138B1 (en) * | 1997-06-12 | 2001-06-12 | Fujitsu Limited | Timing signal generating circuit, semiconductor integrated circuit device and semiconductor integrated circuit system to which the timing signal generating circuit is applied, and signal transmission system |
US6904110B2 (en) | 1997-07-31 | 2005-06-07 | Francois Trans | Channel equalization system and method |
US6154498A (en) | 1997-09-26 | 2000-11-28 | Intel Corporation | Computer system with a semi-differential bus signaling scheme |
JPH11103253A (ja) | 1997-09-29 | 1999-04-13 | Nec Corp | アナログ−デジタル変換器 |
US6480548B1 (en) | 1997-11-17 | 2002-11-12 | Silicon Graphics, Inc. | Spacial derivative bus encoder and decoder |
US6292559B1 (en) | 1997-12-19 | 2001-09-18 | Rice University | Spectral optimization and joint signaling techniques with upstream/downstream separation for communication in the presence of crosstalk |
KR100382181B1 (ko) | 1997-12-22 | 2003-05-09 | 모토로라 인코포레이티드 | 단일 계좌 휴대용 무선 금융 메시지 유닛 |
US6317465B1 (en) | 1998-02-10 | 2001-11-13 | Matsushita Electric Industrial Co., Ltd. | Data transmission system |
US6686879B2 (en) | 1998-02-12 | 2004-02-03 | Genghiscomm, Llc | Method and apparatus for transmitting and receiving signals having a carrier interferometry architecture |
US6172634B1 (en) | 1998-02-25 | 2001-01-09 | Lucent Technologies Inc. | Methods and apparatus for providing analog-fir-based line-driver with pre-equalization |
EP0966133B1 (en) | 1998-06-15 | 2005-03-02 | Sony International (Europe) GmbH | Orthogonal transformations for interference reduction in multicarrier systems |
US6522699B1 (en) | 1998-06-19 | 2003-02-18 | Nortel Networks Limited | Transmission system for reduction of amateur radio interference |
US6084958A (en) | 1998-06-23 | 2000-07-04 | Starium Ltd | Determining the manner in which the wires connecting to a base set of a telephone system are used for transmission and reception of electrical signals representing a communication |
US6226330B1 (en) | 1998-07-16 | 2001-05-01 | Silicon Graphics, Inc. | Eigen-mode encoding of signals in a data group |
US6346907B1 (en) | 1998-08-07 | 2002-02-12 | Agere Systems Guardian Corp. | Analog-to-digital converter having voltage to-time converter and time digitizer, and method for using same |
US6433800B1 (en) | 1998-08-31 | 2002-08-13 | Sun Microsystems, Inc. | Graphical action invocation method, and associated method, for a computer system |
US6097732A (en) | 1998-10-30 | 2000-08-01 | Advanced Micro Devices, Inc. | Apparatus and method for controlling transmission parameters of selected home network stations transmitting on a telephone medium |
US6278740B1 (en) | 1998-11-19 | 2001-08-21 | Gates Technology | Multi-bit (2i+2)-wire differential coding of digital signals using differential comparators and majority logic |
SG116488A1 (en) | 1998-12-16 | 2005-11-28 | Silverbrook Res Pty Ltd | Printer transfer roller with internal drive motor. |
US6175230B1 (en) | 1999-01-14 | 2001-01-16 | Genrad, Inc. | Circuit-board tester with backdrive-based burst timing |
US6865234B1 (en) | 1999-01-20 | 2005-03-08 | Broadcom Corporation | Pair-swap independent trellis decoder for a multi-pair gigabit transceiver |
US6483828B1 (en) | 1999-02-10 | 2002-11-19 | Ericsson, Inc. | System and method for coding in a telecommunications environment using orthogonal and near-orthogonal codes |
US6556628B1 (en) | 1999-04-29 | 2003-04-29 | The University Of North Carolina At Chapel Hill | Methods and systems for transmitting and receiving differential signals over a plurality of conductors |
AU4606700A (en) | 1999-05-07 | 2000-11-21 | Salviac Limited | A tissue engineering scaffold |
US6697420B1 (en) | 1999-05-25 | 2004-02-24 | Intel Corporation | Symbol-based signaling for an electromagnetically-coupled bus system |
US6404820B1 (en) | 1999-07-09 | 2002-06-11 | The United States Of America As Represented By The Director Of The National Security Agency | Method for storage and reconstruction of the extended hamming code for an 8-dimensional lattice quantizer |
US6496889B1 (en) | 1999-09-17 | 2002-12-17 | Rambus Inc. | Chip-to-chip communication system using an ac-coupled bus and devices employed in same |
US7124221B1 (en) | 1999-10-19 | 2006-10-17 | Rambus Inc. | Low latency multi-level communication interface |
US7269212B1 (en) | 2000-09-05 | 2007-09-11 | Rambus Inc. | Low-latency equalization in multi-level, multi-line communication systems |
US7555263B1 (en) | 1999-10-21 | 2009-06-30 | Broadcom Corporation | Adaptive radio transceiver |
US6316987B1 (en) | 1999-10-22 | 2001-11-13 | Velio Communications, Inc. | Low-power low-jitter variable delay timing circuit |
US6473877B1 (en) | 1999-11-10 | 2002-10-29 | Hewlett-Packard Company | ECC code mechanism to detect wire stuck-at faults |
TW483255B (en) | 1999-11-26 | 2002-04-11 | Fujitsu Ltd | Phase-combining circuit and timing signal generator circuit for carrying out a high-speed signal transmission |
US6690739B1 (en) | 2000-01-14 | 2004-02-10 | Shou Yee Mui | Method for intersymbol interference compensation |
US8164362B2 (en) * | 2000-02-02 | 2012-04-24 | Broadcom Corporation | Single-ended sense amplifier with sample-and-hold reference |
US6650638B1 (en) | 2000-03-06 | 2003-11-18 | Agilent Technologies, Inc. | Decoding method and decoder for 64b/66b coded packetized serial data |
DE10016445C2 (de) | 2000-03-29 | 2002-03-28 | Infineon Technologies Ag | Elektronische Ausgangsstufe |
EP1277304B1 (en) | 2000-04-28 | 2009-07-01 | Broadcom Corporation | High-speed serial data transceiver systems and related methods |
US6865236B1 (en) | 2000-06-01 | 2005-03-08 | Nokia Corporation | Apparatus, and associated method, for coding and decoding multi-dimensional biorthogonal codes |
KR100335503B1 (ko) | 2000-06-26 | 2002-05-08 | 윤종용 | 서로 다른 지연 특성을 동일하게 하는 신호 전달 회로,신호 전달 방법 및 이를 구비하는 반도체 장치의 데이터래치 회로 |
US6597942B1 (en) | 2000-08-15 | 2003-07-22 | Cardiac Pacemakers, Inc. | Electrocardiograph leads-off indicator |
US6563382B1 (en) | 2000-10-10 | 2003-05-13 | International Business Machines Corporation | Linear variable gain amplifiers |
US20020044316A1 (en) | 2000-10-16 | 2002-04-18 | Myers Michael H. | Signal power allocation apparatus and method |
EP1202483A1 (en) | 2000-10-27 | 2002-05-02 | Alcatel | Correlated spreading sequences for high rate non-coherent communication systems |
DE60020241T2 (de) | 2000-11-06 | 2005-11-24 | Alcatel | Optische Modulationsart für NRZ-Signale und optischer Sender |
AU2002226044A1 (en) | 2000-11-13 | 2002-05-21 | David C. Robb | Distributed storage in semiconductor memory systems |
US20020191603A1 (en) | 2000-11-22 | 2002-12-19 | Yeshik Shin | Method and system for dynamic segmentation of communications packets |
US6384758B1 (en) | 2000-11-27 | 2002-05-07 | Analog Devices, Inc. | High-speed sampler structures and methods |
US6661355B2 (en) | 2000-12-27 | 2003-12-09 | Apple Computer, Inc. | Methods and apparatus for constant-weight encoding & decoding |
EP2287778B1 (en) | 2001-02-12 | 2015-04-22 | Symbol Technologies, Inc. | Data symbol calibration in RFID tags |
US6766342B2 (en) | 2001-02-15 | 2004-07-20 | Sun Microsystems, Inc. | System and method for computing and unordered Hadamard transform |
US7110349B2 (en) | 2001-03-06 | 2006-09-19 | Brn Phoenix, Inc. | Adaptive communications methods for multiple user packet radio wireless networks |
US20020152340A1 (en) | 2001-03-29 | 2002-10-17 | International Business Machines Corporation | Pseudo-differential parallel source synchronous bus |
US8498368B1 (en) | 2001-04-11 | 2013-07-30 | Qualcomm Incorporated | Method and system for optimizing gain changes by identifying modulation type and rate |
US6675272B2 (en) | 2001-04-24 | 2004-01-06 | Rambus Inc. | Method and apparatus for coordinating memory operations among diversely-located memory components |
US6982954B2 (en) | 2001-05-03 | 2006-01-03 | International Business Machines Corporation | Communications bus with redundant signal paths and method for compensating for signal path errors in a communications bus |
TW503618B (en) | 2001-05-11 | 2002-09-21 | Via Tech Inc | Data comparator using positive/negative phase strobe signal as the dynamic reference voltage and the input buffer using the same |
TW569534B (en) | 2001-05-15 | 2004-01-01 | Via Tech Inc | Data transmission system using differential signals as edge alignment triggering signals and input/output buffers thereof |
CN1463500A (zh) | 2001-05-22 | 2003-12-24 | 皇家菲利浦电子有限公司 | 解码变长码字序列的方法 |
US6452420B1 (en) | 2001-05-24 | 2002-09-17 | National Semiconductor Corporation | Multi-dimensional differential signaling (MDDS) |
DE10134472B4 (de) | 2001-07-16 | 2005-12-15 | Infineon Technologies Ag | Sende- und Empfangsschnittstelle und Verfahren zur Datenübertragung |
JP3939122B2 (ja) | 2001-07-19 | 2007-07-04 | 富士通株式会社 | レシーバ回路 |
US6907552B2 (en) | 2001-08-29 | 2005-06-14 | Tricn Inc. | Relative dynamic skew compensation of parallel data lines |
US6664355B2 (en) | 2001-08-31 | 2003-12-16 | Hanyang Hak Won Co., Ltd. | Process for synthesizing conductive polymers by gas-phase polymerization and product thereof |
US6621427B2 (en) | 2001-10-11 | 2003-09-16 | Sun Microsystems, Inc. | Method and apparatus for implementing a doubly balanced code |
US6999516B1 (en) | 2001-10-24 | 2006-02-14 | Rambus Inc. | Technique for emulating differential signaling |
US6624699B2 (en) | 2001-10-25 | 2003-09-23 | Broadcom Corporation | Current-controlled CMOS wideband data amplifier circuits |
US7706524B2 (en) | 2001-11-16 | 2010-04-27 | Rambus Inc. | Signal line routing to reduce crosstalk effects |
US7142612B2 (en) | 2001-11-16 | 2006-11-28 | Rambus, Inc. | Method and apparatus for multi-level signaling |
US7039136B2 (en) | 2001-11-19 | 2006-05-02 | Tensorcomm, Inc. | Interference cancellation in a signal |
JP2003163612A (ja) | 2001-11-26 | 2003-06-06 | Advanced Telecommunication Research Institute International | ディジタル信号の符号化方法及び復号化方法 |
US7609778B2 (en) | 2001-12-20 | 2009-10-27 | Richard S. Norman | Methods, apparatus, and systems for reducing interference on nearby conductors |
US6624688B2 (en) | 2002-01-07 | 2003-09-23 | Intel Corporation | Filtering variable offset amplifer |
US7400276B1 (en) | 2002-01-28 | 2008-07-15 | Massachusetts Institute Of Technology | Method and apparatus for reducing delay in a bus provided from parallel, capacitively coupled transmission lines |
US6993311B2 (en) | 2002-02-20 | 2006-01-31 | Freescale Semiconductor, Inc. | Radio receiver having an adaptive equalizer and method therefor |
JP3737058B2 (ja) | 2002-03-12 | 2006-01-18 | 沖電気工業株式会社 | アナログ加減算回路、主増幅器、レベル識別回路、光受信回路、光送信回路、自動利得制御増幅回路、自動周波数特性補償増幅回路、及び発光制御回路 |
US7231558B2 (en) | 2002-03-18 | 2007-06-12 | Finisar Corporation | System and method for network error rate testing |
SE521575C2 (sv) | 2002-03-25 | 2003-11-11 | Ericsson Telefon Ab L M | Kalibrering av A/D omvandlare |
US7197084B2 (en) | 2002-03-27 | 2007-03-27 | Qualcomm Incorporated | Precoding for a multipath channel in a MIMO system |
US7269130B2 (en) | 2002-03-29 | 2007-09-11 | Bay Microsystems, Inc. | Redundant add/drop multiplexor |
FR2839339B1 (fr) | 2002-05-03 | 2004-06-04 | Inst Francais Du Petrole | Methode de dimensionnement d'un element de colonne montante avec conduites auxiliaires integrees |
US6573853B1 (en) | 2002-05-24 | 2003-06-03 | Broadcom Corporation | High speed analog to digital converter |
US7142865B2 (en) | 2002-05-31 | 2006-11-28 | Telefonaktie Bolaget Lm Ericsson (Publ) | Transmit power control based on virtual decoding |
US7180949B2 (en) | 2002-06-04 | 2007-02-20 | Lucent Technologies Inc. | High-speed chip-to-chip communication interface |
JP3961886B2 (ja) | 2002-06-06 | 2007-08-22 | パイオニア株式会社 | 情報記録装置 |
US6973613B2 (en) | 2002-06-28 | 2005-12-06 | Sun Microsystems, Inc. | Error detection/correction code which detects and corrects component failure and which provides single bit error correction subsequent to component failure |
US6976194B2 (en) | 2002-06-28 | 2005-12-13 | Sun Microsystems, Inc. | Memory/Transmission medium failure handling controller and method |
KR100602027B1 (ko) | 2002-07-03 | 2006-07-19 | 휴우즈 일렉트로닉스 코오포레이션 | 저밀도 패리티 검사(ldpc) 부호를 이용한비트-인터리브형 부호화 변조 |
US7292629B2 (en) | 2002-07-12 | 2007-11-06 | Rambus Inc. | Selectable-tap equalizer |
US6996379B2 (en) | 2002-07-23 | 2006-02-07 | Broadcom Corp. | Linear high powered integrated circuit transmitter |
US20040027185A1 (en) | 2002-08-09 | 2004-02-12 | Alan Fiedler | High-speed differential sampling flip-flop |
US7869497B2 (en) | 2002-08-30 | 2011-01-11 | Nxp B.V. | Frequency-domain decision feedback equalizing device and method |
US8064508B1 (en) | 2002-09-19 | 2011-11-22 | Silicon Image, Inc. | Equalizer with controllably weighted parallel high pass and low pass filters and receiver including such an equalizer |
US7787572B2 (en) | 2005-04-07 | 2010-08-31 | Rambus Inc. | Advanced signal processors for interference cancellation in baseband receivers |
US7127003B2 (en) | 2002-09-23 | 2006-10-24 | Rambus Inc. | Method and apparatus for communicating information using different signaling types |
JP3990966B2 (ja) | 2002-10-08 | 2007-10-17 | 松下電器産業株式会社 | 差動増幅器 |
US7586972B2 (en) | 2002-11-18 | 2009-09-08 | The Aerospace Corporation | Code division multiple access enhanced capacity system |
US7176823B2 (en) | 2002-11-19 | 2007-02-13 | Stmicroelectronics, Inc. | Gigabit ethernet line driver and hybrid architecture |
US7236535B2 (en) | 2002-11-19 | 2007-06-26 | Qualcomm Incorporated | Reduced complexity channel estimation for wireless communication systems |
FR2849728B1 (fr) | 2003-01-06 | 2005-04-29 | Excem | Procede et dispositif pour la transmission avec une faible diaphonie |
US7362697B2 (en) | 2003-01-09 | 2008-04-22 | International Business Machines Corporation | Self-healing chip-to-chip interface |
US7339990B2 (en) | 2003-02-07 | 2008-03-04 | Fujitsu Limited | Processing a received signal at a detection circuit |
US7620116B2 (en) | 2003-02-28 | 2009-11-17 | Rambus Inc. | Technique for determining an optimal transition-limiting code for use in a multi-level signaling system |
US7348989B2 (en) | 2003-03-07 | 2008-03-25 | Arch Vision, Inc. | Preparing digital images for display utilizing view-dependent texturing |
US7023817B2 (en) | 2003-03-11 | 2006-04-04 | Motorola, Inc. | Method and apparatus for source device synchronization in a communication system |
WO2004088913A1 (ja) | 2003-03-31 | 2004-10-14 | Fujitsu Limited | 位相比較回路及びクロックリカバリ回路 |
US7397848B2 (en) | 2003-04-09 | 2008-07-08 | Rambus Inc. | Partial response receiver |
US7080288B2 (en) | 2003-04-28 | 2006-07-18 | International Business Machines Corporation | Method and apparatus for interface failure survivability using error correction |
US7085153B2 (en) | 2003-05-13 | 2006-08-01 | Innovative Silicon S.A. | Semiconductor memory cell, array, architecture and device, and method of operating same |
US6734811B1 (en) | 2003-05-21 | 2004-05-11 | Apple Computer, Inc. | Single-ended balance-coded interface with embedded-timing |
JP4492920B2 (ja) | 2003-05-27 | 2010-06-30 | ルネサスエレクトロニクス株式会社 | 差動信号伝送システム |
US6876317B2 (en) | 2003-05-30 | 2005-04-05 | Texas Instruments Incorporated | Method of context based adaptive binary arithmetic decoding with two part symbol decoding |
US7388904B2 (en) | 2003-06-03 | 2008-06-17 | Vativ Technologies, Inc. | Near-end, far-end and echo cancellers in a multi-channel transceiver system |
US7082557B2 (en) | 2003-06-09 | 2006-07-25 | Lsi Logic Corporation | High speed serial interface test |
CN1799234A (zh) | 2003-06-30 | 2006-07-05 | 国际商业机器公司 | 用于块编码调制方案的矢量均衡器和矢量序列估计器 |
US7389333B2 (en) | 2003-07-02 | 2008-06-17 | Fujitsu Limited | Provisioning a network element using custom defaults |
JP4201128B2 (ja) | 2003-07-15 | 2008-12-24 | 株式会社ルネサステクノロジ | 半導体集積回路装置 |
US20050027876A1 (en) | 2003-07-29 | 2005-02-03 | Toshitomo Umei | Data transmission method, data transmission system, and data transmission apparatus |
US7358869B1 (en) | 2003-08-20 | 2008-04-15 | University Of Pittsburgh | Power efficient, high bandwidth communication using multi-signal-differential channels |
US7428273B2 (en) | 2003-09-18 | 2008-09-23 | Promptu Systems Corporation | Method and apparatus for efficient preamble detection in digital data receivers |
KR100976489B1 (ko) | 2003-10-01 | 2010-08-18 | 엘지전자 주식회사 | 이동통신의 다중입력 다중출력 시스템에 적용되는데이터의 변조 및 코딩 방식 제어 방법 |
DE602004028144D1 (de) | 2003-10-22 | 2010-08-26 | Nxp Bv | Verfahren und einrichtung zum senden von daten über mehrere übertragungsleitungen |
US7289568B2 (en) | 2003-11-19 | 2007-10-30 | Intel Corporation | Spectrum management apparatus, method, and system |
US7639596B2 (en) | 2003-12-07 | 2009-12-29 | Adaptive Spectrum And Signal Alignment, Inc. | High speed multiple loop DSL system |
WO2005062509A1 (ja) | 2003-12-18 | 2005-07-07 | National Institute Of Information And Communications Technology | 送信装置、受信装置、送信方法、受信方法、ならびに、プログラム |
US7370264B2 (en) | 2003-12-19 | 2008-05-06 | Stmicroelectronics, Inc. | H-matrix for error correcting circuitry |
US7012463B2 (en) | 2003-12-23 | 2006-03-14 | Analog Devices, Inc. | Switched capacitor circuit with reduced common-mode variations |
US8180931B2 (en) | 2004-01-20 | 2012-05-15 | Super Talent Electronics, Inc. | USB-attached-SCSI flash-memory system with additional command, status, and control pipes to a smart-storage switch |
US20050174841A1 (en) | 2004-02-05 | 2005-08-11 | Iota Technology, Inc. | Electronic memory with tri-level cell pair |
US7049865B2 (en) | 2004-03-05 | 2006-05-23 | Intel Corporation | Power-on detect circuit for use with multiple voltage domains |
US7308048B2 (en) | 2004-03-09 | 2007-12-11 | Rambus Inc. | System and method for selecting optimal data transition types for clock and data recovery |
US20050213686A1 (en) | 2004-03-26 | 2005-09-29 | Texas Instruments Incorporated | Reduced complexity transmit spatial waterpouring technique for multiple-input, multiple-output communication systems |
GB0407663D0 (en) | 2004-04-03 | 2004-05-05 | Ibm | Variable gain amplifier |
ES2545905T3 (es) | 2004-04-16 | 2015-09-16 | Thine Electronics, Inc. | Circuito de transmisión, circuito de recepción, método y sistema de transmisión de datos |
US7602246B2 (en) | 2004-06-02 | 2009-10-13 | Qualcomm, Incorporated | General-purpose wideband amplifier |
US7581157B2 (en) | 2004-06-24 | 2009-08-25 | Lg Electronics Inc. | Method and apparatus of encoding and decoding data using low density parity check code in a wireless communication system |
US7587012B2 (en) | 2004-07-08 | 2009-09-08 | Rambus, Inc. | Dual loop clock recovery circuit |
KR100629675B1 (ko) | 2004-07-16 | 2006-09-28 | 학교법인 포항공과대학교 | 4개 신호선을 이용한 3개 데이터의 전류모드 차동 전송방법 및 시스템 |
US7599390B2 (en) | 2004-07-21 | 2009-10-06 | Rambus Inc. | Approximate bit-loading for data transmission over frequency-selective channels |
US7579968B2 (en) | 2004-07-27 | 2009-08-25 | Nxp B.V. | Encoding of data words using three or more level levels |
US7366942B2 (en) | 2004-08-12 | 2008-04-29 | Micron Technology, Inc. | Method and apparatus for high-speed input sampling |
US7460612B2 (en) | 2004-08-12 | 2008-12-02 | Texas Instruments Incorporated | Method and apparatus for a fully digital quadrature modulator |
US7697915B2 (en) | 2004-09-10 | 2010-04-13 | Qualcomm Incorporated | Gain boosting RF gain stage with cross-coupled capacitors |
US8441287B2 (en) | 2004-09-20 | 2013-05-14 | The Trustees Of Columbia University In The City Of New York | Low voltage track and hold circuits |
US7869546B2 (en) | 2004-09-30 | 2011-01-11 | Telefonaktiebolaget Lm Ericsson (Publ) | Multicode transmission using Walsh Hadamard transform |
US7746764B2 (en) | 2004-10-22 | 2010-06-29 | Parkervision, Inc. | Orthogonal signal generation using vector spreading and combining |
US7327803B2 (en) | 2004-10-22 | 2008-02-05 | Parkervision, Inc. | Systems and methods for vector power amplification |
US7346819B2 (en) | 2004-10-29 | 2008-03-18 | Rambus Inc. | Through-core self-test with multiple loopbacks |
TWI269524B (en) | 2004-11-08 | 2006-12-21 | Richwave Technology Corp | Low noise and high gain low noise amplifier |
TWI239715B (en) | 2004-11-16 | 2005-09-11 | Ind Tech Res Inst | Programmable gain current amplifier |
ITVA20040054A1 (it) | 2004-11-23 | 2005-02-23 | St Microelectronics Srl | Metodo per stimare coefficienti di attenuazione di canali, metodo di ricezione di simboli e relativi ricevitore e trasmettitore a singola antenna o multi-antenna |
US7496162B2 (en) | 2004-11-30 | 2009-02-24 | Stmicroelectronics, Inc. | Communication system with statistical control of gain |
US20060126751A1 (en) | 2004-12-10 | 2006-06-15 | Anthony Bessios | Technique for disparity bounding coding in a multi-level signaling system |
US7349484B2 (en) | 2004-12-22 | 2008-03-25 | Rambus Inc. | Adjustable dual-band link |
US7457393B2 (en) | 2004-12-29 | 2008-11-25 | Intel Corporation | Clock recovery apparatus, method, and system |
US7882413B2 (en) | 2005-01-20 | 2011-02-01 | New Jersey Institute Of Technology | Method and/or system for space-time encoding and/or decoding |
US7199728B2 (en) | 2005-01-21 | 2007-04-03 | Rambus, Inc. | Communication system with low power, DC-balanced serial link |
WO2006096678A1 (en) | 2005-03-08 | 2006-09-14 | Qualcomm Flarion Technologies, Inc. | Transmission methods and apparatus combining pulse modulation and hierarchical modulation |
US7735037B2 (en) | 2005-04-15 | 2010-06-08 | Rambus, Inc. | Generating interface adjustment signals in a device-to-device interconnection system |
US20060251421A1 (en) | 2005-05-09 | 2006-11-09 | Ben Gurion University Of The Negev, Research And Development Authority | Improved free space optical bus |
US7335976B2 (en) | 2005-05-25 | 2008-02-26 | International Business Machines Corporation | Crosstalk reduction in electrical interconnects using differential signaling |
US7656321B2 (en) | 2005-06-02 | 2010-02-02 | Rambus Inc. | Signaling system |
US7330058B2 (en) | 2005-07-01 | 2008-02-12 | Via Technologies, Inc. | Clock and data recovery circuit and method thereof |
US7639746B2 (en) | 2005-07-01 | 2009-12-29 | Apple Inc. | Hybrid voltage/current-mode transmission line driver |
JPWO2007013278A1 (ja) | 2005-07-27 | 2009-02-05 | 直樹 末広 | データ通信システム及びデータ送信装置 |
US7808883B2 (en) | 2005-08-08 | 2010-10-05 | Nokia Corporation | Multicarrier modulation with enhanced frequency coding |
TW200710801A (en) | 2005-09-02 | 2007-03-16 | Richtek Techohnology Corp | Driving circuit and method of electroluminescence display |
US7650525B1 (en) | 2005-10-04 | 2010-01-19 | Force 10 Networks, Inc. | SPI-4.2 dynamic implementation without additional phase locked loops |
US7870444B2 (en) | 2005-10-13 | 2011-01-11 | Avago Technologies Fiber Ip (Singapore) Pte. Ltd. | System and method for measuring and correcting data lane skews |
WO2007060756A1 (ja) | 2005-11-22 | 2007-05-31 | Matsushita Electric Industrial Co., Ltd. | 位相比較器及び位相調整回路 |
US7570704B2 (en) | 2005-11-30 | 2009-08-04 | Intel Corporation | Transmitter architecture for high-speed communications |
JP4705858B2 (ja) | 2006-02-10 | 2011-06-22 | Okiセミコンダクタ株式会社 | アナログ・ディジタル変換回路 |
US7987415B2 (en) | 2006-02-15 | 2011-07-26 | Samsung Electronics Co., Ltd. | Method and system for application of unequal error protection to uncompressed video for transmission over wireless channels |
US7694204B2 (en) | 2006-03-09 | 2010-04-06 | Silicon Image, Inc. | Error detection in physical interfaces for point-to-point communications between integrated circuits |
US7356213B1 (en) | 2006-03-28 | 2008-04-08 | Sun Microsystems, Inc. | Transparent switch using optical and electrical proximity communication |
US8129969B1 (en) | 2006-04-07 | 2012-03-06 | Marvell International Ltd. | Hysteretic inductive switching regulator with power supply compensation |
US20070263711A1 (en) | 2006-04-26 | 2007-11-15 | Theodor Kramer Gerhard G | Operating DSL subscriber lines |
US8209580B1 (en) * | 2006-05-08 | 2012-06-26 | Marvell International Ltd. | Error correction coding for varying signal-to-noise ratio channels |
US7539532B2 (en) | 2006-05-12 | 2009-05-26 | Bao Tran | Cuffless blood pressure monitoring appliance |
US8091006B2 (en) | 2006-06-02 | 2012-01-03 | Nec Laboratories America, Inc. | Spherical lattice codes for lattice and lattice-reduction-aided decoders |
KR100806117B1 (ko) | 2006-06-23 | 2008-02-21 | 삼성전자주식회사 | 전압제어 발진기, 이를 구비한 위상동기루프 회로, 및위상동기루프 회로의 제어방법 |
US7688102B2 (en) | 2006-06-29 | 2010-03-30 | Samsung Electronics Co., Ltd. | Majority voter circuits and semiconductor devices including the same |
US7925030B2 (en) | 2006-07-08 | 2011-04-12 | Telefonaktiebolaget Lm Ericsson (Publ) | Crosstalk cancellation using load impedence measurements |
US7439761B2 (en) | 2006-07-12 | 2008-10-21 | Infineon Technologies Ag | Apparatus and method for controlling a driver strength |
ATE479284T1 (de) * | 2006-07-13 | 2010-09-15 | Qualcomm Inc | Videokodierung mit feinkörniger skalierbarkeit anhand von zyklisch ausgerichteten fragmenten |
US7933770B2 (en) | 2006-07-14 | 2011-04-26 | Siemens Audiologische Technik Gmbh | Method and device for coding audio data based on vector quantisation |
KR100744141B1 (ko) | 2006-07-21 | 2007-08-01 | 삼성전자주식회사 | 싱글 엔디드 신호 라인의 가상 차동 상호 연결 회로 및가상 차동 신호 방식 |
US8295250B2 (en) | 2006-07-24 | 2012-10-23 | Qualcomm Incorporated | Code interleaving for a structured code |
US7336112B1 (en) | 2006-08-21 | 2008-02-26 | Huaya Microelectronics, Ltd. | False lock protection in a delay-locked loop (DLL) |
US20080104374A1 (en) | 2006-10-31 | 2008-05-01 | Motorola, Inc. | Hardware sorter |
US7873980B2 (en) | 2006-11-02 | 2011-01-18 | Redmere Technology Ltd. | High-speed cable with embedded signal format conversion and power control |
ITVA20060065A1 (it) | 2006-11-03 | 2008-05-04 | St Microelectronics Srl | Memoria con celle a tre livelli e relativo metodo di gestione. |
US7698088B2 (en) | 2006-11-15 | 2010-04-13 | Silicon Image, Inc. | Interface test circuitry and methods |
US20080159448A1 (en) | 2006-12-29 | 2008-07-03 | Texas Instruments, Incorporated | System and method for crosstalk cancellation |
US7462956B2 (en) | 2007-01-11 | 2008-12-09 | Northrop Grumman Space & Mission Systems Corp. | High efficiency NLTL comb generator using time domain waveform synthesis technique |
JP2008192232A (ja) | 2007-02-05 | 2008-08-21 | Spansion Llc | 半導体装置およびその制御方法 |
US9231790B2 (en) | 2007-03-02 | 2016-01-05 | Qualcomm Incorporated | N-phase phase and polarity encoded serial interface |
US8064535B2 (en) | 2007-03-02 | 2011-11-22 | Qualcomm Incorporated | Three phase and polarity encoded serial interface |
JP4864769B2 (ja) | 2007-03-05 | 2012-02-01 | 株式会社東芝 | Pll回路 |
CN101286775A (zh) | 2007-04-12 | 2008-10-15 | 北京三星通信技术研究有限公司 | 采用增强信号检测的多天线空间复用系统 |
US20100180143A1 (en) | 2007-04-19 | 2010-07-15 | Rambus Inc. | Techniques for improved timing control of memory devices |
KR100871711B1 (ko) | 2007-05-03 | 2008-12-08 | 삼성전자주식회사 | 싱글-엔디드 시그널링과 차동 시그널링을 지원하는 다중위상 송/수신 회로 및 차동 시그널링에서 싱글-엔디드시그널링 전환을 위한 클럭킹 방법 |
WO2008151251A1 (en) | 2007-06-05 | 2008-12-11 | Rambus, Inc. | Techniques for multi-wire encoding with an embedded clock |
EP2471457A1 (en) | 2007-06-07 | 2012-07-04 | Microchips, Inc. | Electrochemical biosensors and arrays |
CN101072048B (zh) | 2007-06-13 | 2013-12-04 | 华为技术有限公司 | 信息参数的调整方法及装置 |
US8045670B2 (en) | 2007-06-22 | 2011-10-25 | Texas Instruments Incorporated | Interpolative all-digital phase locked loop |
US8102934B2 (en) | 2007-08-16 | 2012-01-24 | Samsung Electronics Co., Ltd. | Transmitting apparatus and method |
US20090059782A1 (en) | 2007-08-29 | 2009-03-05 | Rgb Systems, Inc. | Method and apparatus for extending the transmission capability of twisted pair communication systems |
CN101399798B (zh) | 2007-09-27 | 2011-07-06 | 北京信威通信技术股份有限公司 | 一种ofdma无线通信系统的稳健信号传输方法及装置 |
US8159375B2 (en) | 2007-10-01 | 2012-04-17 | Rambus Inc. | Simplified receiver for use in multi-wire communication |
US9197470B2 (en) | 2007-10-05 | 2015-11-24 | Innurvation, Inc. | Data transmission via multi-path channels using orthogonal multi-frequency signals with differential phase shift keying modulation |
JP5465376B2 (ja) | 2007-10-18 | 2014-04-09 | ピーエスフォー ルクスコ エスエイアールエル | 半導体装置、およびドライバ制御方法 |
US8279094B2 (en) | 2007-10-24 | 2012-10-02 | Rambus Inc. | Encoding and decoding techniques with improved timing margin |
US7899653B2 (en) * | 2007-10-30 | 2011-03-01 | Micron Technology, Inc. | Matrix modeling of parallel data structures to facilitate data encoding and/or jittery signal generation |
US8279976B2 (en) | 2007-10-30 | 2012-10-02 | Rambus Inc. | Signaling with superimposed differential-mode and common-mode signals |
JP2009118049A (ja) | 2007-11-05 | 2009-05-28 | Panasonic Corp | 離散時間型増幅回路及びアナログ・ディジタル変換器 |
US8245094B2 (en) | 2007-11-20 | 2012-08-14 | California Institute of Technology Texas A & M | Rank modulation for flash memories |
JP2009134573A (ja) | 2007-11-30 | 2009-06-18 | Nec Corp | マルチチップ半導体装置およびデータ転送方法 |
US8429492B2 (en) | 2007-11-30 | 2013-04-23 | Marvell World Trade Ltd. | Error correcting code predication system and method |
WO2009075936A1 (en) | 2007-12-07 | 2009-06-18 | Rambus Inc. | Encoding and decoding techniques for bandwidth-efficient communication |
EP2071786B1 (en) | 2007-12-14 | 2020-12-23 | Vodafone Holding GmbH | Method and transceiver for data communication |
US8588254B2 (en) | 2007-12-17 | 2013-11-19 | Broadcom Corporation | Method and system for energy efficient signaling for 100mbps Ethernet using a subset technique |
KR100934007B1 (ko) | 2007-12-18 | 2009-12-28 | 한국전자통신연구원 | 다중입력 다중출력 수신기에서 다차원 검출 장치 및방법과, 이를 이용한 수신 장치 |
WO2009086142A1 (en) * | 2007-12-19 | 2009-07-09 | Rambus Inc. | Asymmetric communication on shared links |
US8253454B2 (en) | 2007-12-21 | 2012-08-28 | Realtek Semiconductor Corp. | Phase lock loop with phase interpolation by reference clock and method for the same |
CN101601199B (zh) | 2007-12-28 | 2013-04-17 | 日本电气株式会社 | 用于多扇区无线通信系统的信号处理及其方法 |
US8055095B2 (en) | 2008-01-23 | 2011-11-08 | Sparsense, Inc. | Parallel and adaptive signal processing |
CN101499048A (zh) | 2008-01-29 | 2009-08-05 | 国际商业机器公司 | 总线编/解码方法和总线编/解码器 |
FR2927205A1 (fr) | 2008-01-31 | 2009-08-07 | Commissariat Energie Atomique | Procede de codage spatio-temporel a faible papr pour systeme de communication multi-antenne de type uwb impulsionnel |
US7841909B2 (en) | 2008-02-12 | 2010-11-30 | Adc Gmbh | Multistage capacitive far end crosstalk compensation arrangement |
KR20090090928A (ko) | 2008-02-22 | 2009-08-26 | 삼성전자주식회사 | 저잡음 증폭기 |
CN101478286A (zh) | 2008-03-03 | 2009-07-08 | 锐迪科微电子(上海)有限公司 | 方波-正弦波信号转换方法及转换电路 |
WO2009111175A1 (en) | 2008-03-06 | 2009-09-11 | Rambus Inc. | Error detection and offset cancellation during multi-wire communication |
EP2592552B1 (en) | 2008-03-11 | 2015-11-25 | Agere Systems Inc. | Methods and apparatus for storing data in a multi-level cell flash memory device with cross-page sectors, multi-page coding and per-page coding |
KR100963410B1 (ko) | 2008-03-11 | 2010-06-14 | 한국전자통신연구원 | 릴레이 시스템에서 신호점 재배열 또는 중첩 변조를 기반으로 하는 협력 수신 다이버시티 장치 및 방법 |
US7583209B1 (en) | 2008-03-19 | 2009-09-01 | Mitsubishi Electric Research Laboratories, Inc. | System and method for signaling on a bus using forbidden pattern free codes |
US8644497B2 (en) | 2008-04-24 | 2014-02-04 | Lantiq Deutschland Gmbh | Method and apparatus for adding a communication connection to a vectored group |
US7990185B2 (en) | 2008-05-12 | 2011-08-02 | Menara Networks | Analog finite impulse response filter |
US8498344B2 (en) | 2008-06-20 | 2013-07-30 | Rambus Inc. | Frequency responsive bus coding |
CN101610115A (zh) | 2008-06-20 | 2009-12-23 | 华为技术有限公司 | 光信号的产生方法及装置 |
US8149955B2 (en) | 2008-06-30 | 2012-04-03 | Telefonaktiebolaget L M Ericsson (Publ) | Single ended multiband feedback linearized RF amplifier and mixer with DC-offset and IM2 suppression feedback loop |
FR2933556B1 (fr) | 2008-07-07 | 2010-08-20 | Excem | Circuit de reception pseudo-differentiel |
JP2011529298A (ja) | 2008-07-27 | 2011-12-01 | ラムバス・インコーポレーテッド | 受信側の供給負荷の分散方法及びシステム |
US8341492B2 (en) | 2008-07-28 | 2012-12-25 | Broadcom Corporation | Quasi-cyclic LDPC (low density parity check) code construction |
US8687968B2 (en) | 2008-08-18 | 2014-04-01 | Nippon Telegraph And Telephone Corporation | Vector sum phase shifter, optical transceiver, and control circuit |
US20100046644A1 (en) | 2008-08-19 | 2010-02-25 | Motorola, Inc. | Superposition coding |
JP2010062944A (ja) | 2008-09-04 | 2010-03-18 | Kyushu Institute Of Technology | 無線通信システム、無線受信装置および無線送信装置 |
FR2936384A1 (fr) | 2008-09-22 | 2010-03-26 | St Microelectronics Grenoble | Dispositif d'echange de donnees entre composants d'un circuit integre |
US8442099B1 (en) | 2008-09-25 | 2013-05-14 | Aquantia Corporation | Crosstalk cancellation for a common-mode channel |
US8103287B2 (en) | 2008-09-30 | 2012-01-24 | Apple Inc. | Methods and apparatus for resolving wireless signal components |
US8601338B2 (en) | 2008-11-26 | 2013-12-03 | Broadcom Corporation | Modified error distance decoding of a plurality of signals |
KR101173942B1 (ko) | 2008-11-28 | 2012-08-14 | 한국전자통신연구원 | 데이터 송신 장치, 데이터 수신 장치, 데이터 전송 시스템 및 데이터 전송 방법 |
US8917783B2 (en) | 2008-12-03 | 2014-12-23 | Rambus Inc. | Resonance mitigation for high-speed signaling |
AU2008264232B2 (en) | 2008-12-30 | 2012-05-17 | Canon Kabushiki Kaisha | Multi-modal object signature |
US8472513B2 (en) | 2009-01-14 | 2013-06-25 | Lsi Corporation | TX back channel adaptation algorithm |
JP4748227B2 (ja) | 2009-02-10 | 2011-08-17 | ソニー株式会社 | データ変調装置とその方法 |
TWI430622B (zh) | 2009-02-23 | 2014-03-11 | Inst Information Industry | 訊號傳輸裝置、傳輸方法及其電腦程式產品 |
US8428177B2 (en) | 2009-02-25 | 2013-04-23 | Samsung Electronics Co., Ltd. | Method and apparatus for multiple input multiple output (MIMO) transmit beamforming |
US8274311B2 (en) | 2009-02-27 | 2012-09-25 | Yonghua Liu | Data transmission system and method |
CN101854223A (zh) | 2009-03-31 | 2010-10-06 | 上海交通大学 | 矢量量化码书生成方法 |
JP5316194B2 (ja) | 2009-04-20 | 2013-10-16 | ソニー株式会社 | Ad変換器 |
US8437440B1 (en) | 2009-05-28 | 2013-05-07 | Marvell International Ltd. | PHY frame formats in a system with more than four space-time streams |
EP2262267A1 (en) * | 2009-06-10 | 2010-12-15 | Panasonic Corporation | Filter coefficient coding scheme for video coding |
JP5187277B2 (ja) | 2009-06-16 | 2013-04-24 | ソニー株式会社 | 情報処理装置、及びモード切り替え方法 |
EP2457333B1 (en) | 2009-07-20 | 2015-12-16 | Lantiq Deutschland GmbH | Method and apparatus for vectored data communication |
US9566439B2 (en) | 2009-07-20 | 2017-02-14 | Saluda Medical Pty Limited | Neuro-stimulation |
JP5272948B2 (ja) | 2009-07-28 | 2013-08-28 | ソニー株式会社 | 増幅回路、半導体集積回路、無線伝送システム、通信装置 |
TW201106663A (en) | 2009-08-05 | 2011-02-16 | Novatek Microelectronics Corp | Dual-port input equalizer |
KR101079603B1 (ko) | 2009-08-11 | 2011-11-03 | 주식회사 티엘아이 | 3레벨 전압을 이용하는 차동 데이터 송수신 장치 및 차동 데이터 송수신 방법 |
US9189242B2 (en) | 2009-09-24 | 2015-11-17 | Nvidia Corporation | Credit-based streaming multiprocessor warp scheduling |
EP2494753A2 (en) | 2009-10-30 | 2012-09-05 | Bangor University | Synchronisation process in optical frequency division multiplexing transmission systems |
US8681894B2 (en) | 2009-11-03 | 2014-03-25 | Telefonaktiebolaget L M (Publ) | Digital affine transformation modulated power amplifier for wireless communications |
US8279745B2 (en) | 2009-11-23 | 2012-10-02 | Telefonaktiebolaget L M Ericsson (Publ) | Orthogonal vector DSL |
TW201145918A (en) | 2009-12-27 | 2011-12-16 | Maxlinear Inc | Methods and apparatus for synchronization in multiple-channel communication systems |
TWI562554B (en) | 2009-12-30 | 2016-12-11 | Sony Corp | Communications system and device using beamforming |
CN102014475B (zh) | 2010-01-08 | 2012-01-04 | 华为技术有限公司 | 资源映射、码分复用方法及装置 |
US8295336B2 (en) | 2010-03-16 | 2012-10-23 | Micrel Inc. | High bandwidth programmable transmission line pre-emphasis method and circuit |
WO2011119359A2 (en) | 2010-03-24 | 2011-09-29 | Rambus Inc. | Coded differential intersymbol interference reduction |
US9288089B2 (en) | 2010-04-30 | 2016-03-15 | Ecole Polytechnique Federale De Lausanne (Epfl) | Orthogonal differential vector signaling |
US8386895B2 (en) | 2010-05-19 | 2013-02-26 | Micron Technology, Inc. | Enhanced multilevel memory |
US9077386B1 (en) | 2010-05-20 | 2015-07-07 | Kandou Labs, S.A. | Methods and systems for selection of unions of vector signaling codes for power and pin efficient chip-to-chip communication |
US8880783B2 (en) | 2011-07-05 | 2014-11-04 | Kandou Labs SA | Differential vector storage for non-volatile memory |
US9479369B1 (en) | 2010-05-20 | 2016-10-25 | Kandou Labs, S.A. | Vector signaling codes with high pin-efficiency for chip-to-chip communication and storage |
US9083576B1 (en) | 2010-05-20 | 2015-07-14 | Kandou Labs, S.A. | Methods and systems for error detection and correction using vector signal prediction |
US8755426B1 (en) | 2012-03-15 | 2014-06-17 | Kandou Labs, S.A. | Rank-order equalization |
US9596109B2 (en) | 2010-05-20 | 2017-03-14 | Kandou Labs, S.A. | Methods and systems for high bandwidth communications interface |
US9362962B2 (en) | 2010-05-20 | 2016-06-07 | Kandou Labs, S.A. | Methods and systems for energy-efficient communications interface |
US9401828B2 (en) | 2010-05-20 | 2016-07-26 | Kandou Labs, S.A. | Methods and systems for low-power and pin-efficient communications with superposition signaling codes |
US9059816B1 (en) | 2010-05-20 | 2015-06-16 | Kandou Labs, S.A. | Control loop management and differential delay correction for vector signaling code communications links |
US8385387B2 (en) | 2010-05-20 | 2013-02-26 | Harris Corporation | Time dependent equalization of frequency domain spread orthogonal frequency division multiplexing using decision feedback equalization |
US9288082B1 (en) | 2010-05-20 | 2016-03-15 | Kandou Labs, S.A. | Circuits for efficient detection of vector signaling codes for chip-to-chip communication using sums of differences |
US9251873B1 (en) | 2010-05-20 | 2016-02-02 | Kandou Labs, S.A. | Methods and systems for pin-efficient memory controller interface using vector signaling codes for chip-to-chip communications |
US8539318B2 (en) | 2010-06-04 | 2013-09-17 | École Polytechnique Fédérale De Lausanne (Epfl) | Power and pin efficient chip-to-chip communications with common-mode rejection and SSO resilience |
US9246713B2 (en) | 2010-05-20 | 2016-01-26 | Kandou Labs, S.A. | Vector signaling with reduced receiver complexity |
US8593305B1 (en) | 2011-07-05 | 2013-11-26 | Kandou Labs, S.A. | Efficient processing and detection of balanced codes |
US8649445B2 (en) | 2011-02-17 | 2014-02-11 | École Polytechnique Fédérale De Lausanne (Epfl) | Methods and systems for noise resilient, pin-efficient and low power communications with sparse signaling codes |
US9564994B2 (en) | 2010-05-20 | 2017-02-07 | Kandou Labs, S.A. | Fault tolerant chip-to-chip communication with advanced voltage |
US9106220B2 (en) | 2010-05-20 | 2015-08-11 | Kandou Labs, S.A. | Methods and systems for high bandwidth chip-to-chip communications interface |
US9300503B1 (en) | 2010-05-20 | 2016-03-29 | Kandou Labs, S.A. | Methods and systems for skew tolerance in and advanced detectors for vector signaling codes for chip-to-chip communication |
US8989317B1 (en) | 2010-05-20 | 2015-03-24 | Kandou Labs, S.A. | Crossbar switch decoder for vector signaling codes |
US8718184B1 (en) | 2012-05-03 | 2014-05-06 | Kandou Labs S.A. | Finite state encoders and decoders for vector signaling codes |
US9071476B2 (en) | 2010-05-20 | 2015-06-30 | Kandou Labs, S.A. | Methods and systems for high bandwidth chip-to-chip communications interface |
US9178503B2 (en) | 2010-05-28 | 2015-11-03 | Xilinx, Inc. | Differential comparator circuit having a wide common mode input range |
US8578246B2 (en) | 2010-05-31 | 2013-11-05 | International Business Machines Corporation | Data encoding in solid-state storage devices |
US8615703B2 (en) | 2010-06-04 | 2013-12-24 | Micron Technology, Inc. | Advanced bitwise operations and apparatus in a multi-level system with nonvolatile memory |
US9667379B2 (en) * | 2010-06-04 | 2017-05-30 | Ecole Polytechnique Federale De Lausanne (Epfl) | Error control coding for orthogonal differential vector signaling |
US8897134B2 (en) | 2010-06-25 | 2014-11-25 | Telefonaktiebolaget L M Ericsson (Publ) | Notifying a controller of a change to a packet forwarding configuration of a network element over a communication channel |
WO2012001616A2 (en) | 2010-06-27 | 2012-01-05 | Valens Semiconductor Ltd. | Methods and systems for time sensitive networks |
US8602643B2 (en) | 2010-07-06 | 2013-12-10 | David Phillip Gardiner | Method and apparatus for measurement of temperature and rate of change of temperature |
US8547272B2 (en) | 2010-08-18 | 2013-10-01 | Analog Devices, Inc. | Charge sharing analog computation circuitry and applications |
US8773964B2 (en) | 2010-09-09 | 2014-07-08 | The Regents Of The University Of California | CDMA-based crosstalk cancellation for on-chip global high-speed links |
US8429495B2 (en) | 2010-10-19 | 2013-04-23 | Mosaid Technologies Incorporated | Error detection and correction codes for channels and memories with incomplete error characteristics |
US20120106539A1 (en) | 2010-10-27 | 2012-05-03 | International Business Machines Corporation | Coordinating Communications Interface Activities in Data Communicating Devices Using Redundant Lines |
JP5623883B2 (ja) | 2010-11-29 | 2014-11-12 | ルネサスエレクトロニクス株式会社 | 差動増幅器及びデータドライバ |
WO2012082854A2 (en) | 2010-12-17 | 2012-06-21 | Mattson Technology, Inc. | Inductively coupled plasma source for plasma processing |
US8750176B2 (en) | 2010-12-22 | 2014-06-10 | Apple Inc. | Methods and apparatus for the intelligent association of control symbols |
US8620166B2 (en) | 2011-01-07 | 2013-12-31 | Raytheon Bbn Technologies Corp. | Holevo capacity achieving joint detection receiver |
WO2012121689A1 (en) | 2011-03-04 | 2012-09-13 | Hewlett-Packard Development Company, L.P. | Antipodal-mapping-based encoders and decoders |
US8594164B2 (en) | 2011-03-25 | 2013-11-26 | Broadcom Corporation | Systems and methods for flow control of a remote transmitter |
US9432298B1 (en) | 2011-12-09 | 2016-08-30 | P4tents1, LLC | System, method, and computer program product for improving memory systems |
CN107529709B (zh) * | 2011-06-16 | 2019-05-07 | Ge视频压缩有限责任公司 | 解码器、编码器、解码和编码视频的方法及存储介质 |
EP2557687B1 (en) | 2011-08-11 | 2018-06-13 | Telefonaktiebolaget LM Ericsson (publ) | Low-noise amplifier, receiver, method and computer program |
WO2013028181A1 (en) | 2011-08-23 | 2013-02-28 | Intel Corporation | Digital delay-locked loop with drift sensor |
TW201310897A (zh) | 2011-08-29 | 2013-03-01 | Novatek Microelectronics Corp | 具動態轉導補償之多輸入差動放大器 |
US9455765B2 (en) | 2011-09-07 | 2016-09-27 | Commscope, Inc. Of North Carolina | Communications connectors having frequency dependent communications paths and related methods |
EP2573946B1 (en) | 2011-09-23 | 2014-07-30 | Alcatel Lucent | Power adaptation avoidance during crosstalk measurements |
CN103036537B (zh) | 2011-10-09 | 2016-02-17 | 瑞昱半导体股份有限公司 | 相位内插器、多相位内插装置及内插时钟的产生方法 |
EP2774267A1 (en) | 2011-11-02 | 2014-09-10 | Marvell World Trade Ltd. | Differential amplifier |
US9444656B2 (en) | 2011-11-04 | 2016-09-13 | Altera Corporation | Flexible receiver architecture |
US8854945B2 (en) | 2011-11-09 | 2014-10-07 | Qualcomm Incorporated | Enhanced adaptive gain control in heterogeneous networks |
WO2013085811A1 (en) | 2011-12-06 | 2013-06-13 | Rambus Inc. | Receiver with enhanced isi mitigation |
JP5799786B2 (ja) | 2011-12-09 | 2015-10-28 | 富士電機株式会社 | オートゼロアンプ及び該アンプを使用した帰還増幅回路 |
US8898504B2 (en) | 2011-12-14 | 2014-11-25 | International Business Machines Corporation | Parallel data communications mechanism having reduced power continuously calibrated lines |
JP6205659B2 (ja) | 2011-12-15 | 2017-10-04 | マーベル ワールド トレード リミテッド | プロセス、温度、及び負荷インピーダンスの変動に対して無感応のrf電力検出回路 |
US8909840B2 (en) | 2011-12-19 | 2014-12-09 | Advanced Micro Devices, Inc. | Data bus inversion coding |
FR2985125A1 (fr) | 2011-12-21 | 2013-06-28 | France Telecom | Procede de transmission d'un signal numerique pour un systeme ms-marc semi-orthogonal, produit programme et dispositif relais correspondants |
US8520348B2 (en) | 2011-12-22 | 2013-08-27 | Lsi Corporation | High-swing differential driver using low-voltage transistors |
US8750406B2 (en) | 2012-01-31 | 2014-06-10 | Altera Corporation | Multi-level amplitude signaling receiver |
US8615062B2 (en) | 2012-02-07 | 2013-12-24 | Lsi Corporation | Adaptation using error signature analysis in a communication system |
US8964825B2 (en) | 2012-02-17 | 2015-02-24 | International Business Machines Corporation | Analog signal current integrators with tunable peaking function |
US9537644B2 (en) | 2012-02-23 | 2017-01-03 | Lattice Semiconductor Corporation | Transmitting multiple differential signals over a reduced number of physical channels |
JP5597660B2 (ja) | 2012-03-05 | 2014-10-01 | 株式会社東芝 | Ad変換器 |
US8711919B2 (en) | 2012-03-29 | 2014-04-29 | Rajendra Kumar | Systems and methods for adaptive blind mode equalization |
US8604879B2 (en) | 2012-03-30 | 2013-12-10 | Integrated Device Technology Inc. | Matched feedback amplifier with improved linearity |
US8614634B2 (en) | 2012-04-09 | 2013-12-24 | Nvidia Corporation | 8b/9b encoding for reducing crosstalk on a high speed parallel bus |
US8717215B2 (en) | 2012-05-18 | 2014-05-06 | Tensorcom, Inc. | Method and apparatus for improving the performance of a DAC switch array |
US9183085B1 (en) | 2012-05-22 | 2015-11-10 | Pmc-Sierra, Inc. | Systems and methods for adaptively selecting from among a plurality of error correction coding schemes in a flash drive for robustness and low latency |
US9188433B2 (en) | 2012-05-24 | 2015-11-17 | Qualcomm Incorporated | Code in affine-invariant spatial mask |
US8996740B2 (en) | 2012-06-29 | 2015-03-31 | Qualcomm Incorporated | N-phase polarity output pin mode multiplexer |
EP2688217B1 (en) | 2012-07-20 | 2015-02-25 | Alcatel Lucent | Method and apparatus for fast and accurate acquisition of crosstalk coefficients |
JP5792690B2 (ja) | 2012-07-26 | 2015-10-14 | 株式会社東芝 | 差動出力回路および半導体集積回路 |
US8961239B2 (en) | 2012-09-07 | 2015-02-24 | Commscope, Inc. Of North Carolina | Communication jack having a plurality of contacts mounted on a flexible printed circuit board |
US8873659B2 (en) | 2012-10-19 | 2014-10-28 | Broadcom Corporation | Reduced pair Ethernet transmission system |
US9093791B2 (en) | 2012-11-05 | 2015-07-28 | Commscope, Inc. Of North Carolina | Communications connectors having crosstalk stages that are implemented using a plurality of discrete, time-delayed capacitive and/or inductive components that may provide enhanced insertion loss and/or return loss performance |
US8873606B2 (en) | 2012-11-07 | 2014-10-28 | Broadcom Corporation | Transceiver including a high latency communication channel and a low latency communication channel |
US8975948B2 (en) | 2012-11-15 | 2015-03-10 | Texas Instruments Incorporated | Wide common mode range transmission gate |
US9036764B1 (en) | 2012-12-07 | 2015-05-19 | Rambus Inc. | Clock recovery circuit |
US9048824B2 (en) | 2012-12-12 | 2015-06-02 | Intel Corporation | Programmable equalization with compensated impedance |
KR102003926B1 (ko) | 2012-12-26 | 2019-10-01 | 에스케이하이닉스 주식회사 | 디엠퍼시스 버퍼 회로 |
CN104995612B (zh) | 2013-01-17 | 2020-01-03 | 康杜实验室公司 | 低同步开关噪声芯片间通信方法和系统 |
US9069995B1 (en) | 2013-02-21 | 2015-06-30 | Kandou Labs, S.A. | Multiply accumulate operations in the analog domain |
WO2014164889A2 (en) | 2013-03-11 | 2014-10-09 | Spectra7 Microsystems Ltd | Reducing electromagnetic radiation emitted from high-speed interconnects |
US9355693B2 (en) | 2013-03-14 | 2016-05-31 | Intel Corporation | Memory receiver circuit for use with memory of different characteristics |
US9203351B2 (en) | 2013-03-15 | 2015-12-01 | Megachips Corporation | Offset cancellation with minimum noise impact and gain-bandwidth degradation |
JP6032081B2 (ja) | 2013-03-22 | 2016-11-24 | 富士通株式会社 | 受信回路、及び半導体集積回路 |
JP6079388B2 (ja) | 2013-04-03 | 2017-02-15 | 富士通株式会社 | 受信回路及びその制御方法 |
US9152495B2 (en) | 2013-07-03 | 2015-10-06 | SanDisk Technologies, Inc. | Managing non-volatile media using multiple error correcting codes |
CN103516650B (zh) | 2013-09-10 | 2016-06-01 | 华中科技大学 | 一种mimo无线通信非相干酉空时调制的对跖解调方法及对跖解调器 |
US8976050B1 (en) | 2013-09-12 | 2015-03-10 | Fujitsu Semiconductor Limited | Circuitry and methods for use in mixed-signal circuitry |
JP6171843B2 (ja) | 2013-10-25 | 2017-08-02 | 富士通株式会社 | 受信回路 |
US9106465B2 (en) | 2013-11-22 | 2015-08-11 | Kandou Labs, S.A. | Multiwire linear equalizer for vector signaling code receiver |
WO2015117102A1 (en) | 2014-02-02 | 2015-08-06 | Kandou Labs SA | Method and apparatus for low power chip-to-chip communications with constrained isi ratio |
EP3111607B1 (en) | 2014-02-28 | 2020-04-08 | Kandou Labs SA | Clock-embedded vector signaling codes |
US9509437B2 (en) | 2014-05-13 | 2016-11-29 | Kandou Labs, S.A. | Vector signaling code with improved noise margin |
US9710412B2 (en) | 2014-05-15 | 2017-07-18 | Qualcomm Incorporated | N-factorial voltage mode driver |
US9148087B1 (en) | 2014-05-16 | 2015-09-29 | Kandou Labs, S.A. | Symmetric is linear equalization circuit with increased gain |
US9397873B2 (en) | 2014-06-11 | 2016-07-19 | Marvell World Trade Ltd. | Compressed orthogonal frequency division multiplexing (OFDM) symbols in a wireless communication system |
US9112550B1 (en) | 2014-06-25 | 2015-08-18 | Kandou Labs, SA | Multilevel driver for high speed chip-to-chip communications |
GB2527604A (en) * | 2014-06-27 | 2015-12-30 | Ibm | Data encoding in solid-state storage devices |
US9432082B2 (en) | 2014-07-17 | 2016-08-30 | Kandou Labs, S.A. | Bus reversable orthogonal differential vector signaling codes |
US9444654B2 (en) | 2014-07-21 | 2016-09-13 | Kandou Labs, S.A. | Multidrop data transfer |
KR101949964B1 (ko) | 2014-08-01 | 2019-02-20 | 칸도우 랩스 에스에이 | 임베딩된 클록을 갖는 직교 차동 벡터 시그널링 코드 |
JP6361433B2 (ja) | 2014-10-02 | 2018-07-25 | 富士通株式会社 | 周波数検出回路及び受信回路 |
US9674014B2 (en) | 2014-10-22 | 2017-06-06 | Kandou Labs, S.A. | Method and apparatus for high speed chip-to-chip communications |
US9374250B1 (en) | 2014-12-17 | 2016-06-21 | Intel Corporation | Wireline receiver circuitry having collaborative timing recovery |
US10341145B2 (en) | 2015-03-03 | 2019-07-02 | Intel Corporation | Low power high speed receiver with reduced decision feedback equalizer samplers |
WO2016210445A1 (en) | 2015-06-26 | 2016-12-29 | Kandou Labs, S.A. | High speed communications system |
US10055372B2 (en) | 2015-11-25 | 2018-08-21 | Kandou Labs, S.A. | Orthogonal differential vector signaling codes with embedded clock |
EP3826184A1 (en) | 2016-04-22 | 2021-05-26 | Kandou Labs, S.A. | High performance phase locked loop |
CN109313622B (zh) | 2016-04-28 | 2022-04-15 | 康杜实验室公司 | 用于密集路由线组的向量信令码 |
US10153591B2 (en) | 2016-04-28 | 2018-12-11 | Kandou Labs, S.A. | Skew-resistant multi-wire channel |
US10409319B2 (en) | 2017-04-17 | 2019-09-10 | Intel Corporation | System, apparatus and method for providing a local clock signal for a memory array |
US20190103903A1 (en) | 2017-10-02 | 2019-04-04 | Mediatek Inc. | Codebook Designs To Support ULA And Non-ULA Scenarios |
US10291439B1 (en) | 2017-12-13 | 2019-05-14 | Micron Technology, Inc. | Decision feedback equalizer |
SG11202006861XA (en) * | 2018-01-26 | 2020-08-28 | California Inst Of Techn | Systems and methods for communicating by modulating data on zeros |
US10873345B2 (en) * | 2018-02-05 | 2020-12-22 | Qualcomm Incorporated | Enhanced polar code construction |
-
2015
- 2015-03-02 EP EP15710999.2A patent/EP3111607B1/en active Active
- 2015-03-02 CN CN201580010265.2A patent/CN106105123B/zh active Active
- 2015-03-02 WO PCT/US2015/018363 patent/WO2015131203A1/en active Application Filing
- 2015-03-02 KR KR1020167026717A patent/KR102240544B1/ko active IP Right Grant
- 2015-03-02 EP EP20155839.2A patent/EP3672176B1/en active Active
- 2015-03-02 US US14/636,098 patent/US9363114B2/en active Active
-
2016
- 2016-06-07 US US15/176,085 patent/US9686106B2/en active Active
- 2016-12-23 US US15/390,293 patent/US10020966B2/en active Active
-
2018
- 2018-07-10 US US16/031,875 patent/US10374846B2/en active Active
-
2019
- 2019-08-06 US US16/533,592 patent/US10805129B2/en active Active
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6084883A (en) * | 1997-07-07 | 2000-07-04 | 3Com Corporation | Efficient data transmission over digital telephone networks using multiple modulus conversion |
US6954492B1 (en) * | 2000-04-19 | 2005-10-11 | 3Com Corporation | Method of differential encoding a precoded multiple modulus encoder |
Non-Patent Citations (2)
Title |
---|
"Generalized Differential Vector Signaling";A. Abbasfar;《2009 IEEE International Conference on Communications》;20090811;全文 |
"V.92:the last dial-up modem";Dae-Young Kim,等;《 IEEE Transactions on Communications ( Volume: 52, Issue: 1, Jan. 2004 )》;20040303;全文 |
Also Published As
Publication number | Publication date |
---|---|
CN106105123A (zh) | 2016-11-09 |
EP3672176B1 (en) | 2022-05-11 |
US20170111192A1 (en) | 2017-04-20 |
KR102240544B1 (ko) | 2021-04-19 |
US9686106B2 (en) | 2017-06-20 |
US10805129B2 (en) | 2020-10-13 |
US10020966B2 (en) | 2018-07-10 |
US20160294586A1 (en) | 2016-10-06 |
US20180324008A1 (en) | 2018-11-08 |
US20150249559A1 (en) | 2015-09-03 |
KR20160127102A (ko) | 2016-11-02 |
EP3672176A1 (en) | 2020-06-24 |
EP3111607A1 (en) | 2017-01-04 |
WO2015131203A1 (en) | 2015-09-03 |
EP3111607B1 (en) | 2020-04-08 |
US10374846B2 (en) | 2019-08-06 |
US9363114B2 (en) | 2016-06-07 |
US20190363916A1 (en) | 2019-11-28 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN106105123B (zh) | 用于发送时钟嵌入式向量信令码的方法和系统 | |
CN106576087B (zh) | 带内嵌时钟的正交差分向量信令码 | |
CN108463977A (zh) | 带内嵌时钟的正交差分向量信令码 | |
US5200979A (en) | High speed telecommunication system using a novel line code | |
CN105993151B (zh) | 低isi比低功率芯片间通信方法和装置 | |
CN106664071B (zh) | 高速芯片间通信用多电平驱动电路 | |
CA2249979C (en) | Transition controlled balanced encoding scheme | |
US5239496A (en) | Digital parallel correlator | |
CN1713626B (zh) | 电压电平编码系统和方法 | |
EP0777876A1 (en) | Method and apparatus for synchronized transmission of data between a network adaptor and multiple transmission channels | |
CN107171728B (zh) | 1b4b与曼彻斯特编码的正向、反向传输方法及装置、系统 | |
CN105591645A (zh) | 一种多级串并转换电路 | |
EP0151430A2 (en) | Detector | |
CN102594371B (zh) | 一种Turbo编码交织处理的方法及装置 | |
Lee et al. | Related-key differential attacks on Cobra-S128, Cobra-F64a, and Cobra-F64b | |
Wu et al. | High throughput design and implementation of SHA-3 hash algorithm | |
CN109328434A (zh) | 均衡电路、接收电路以及集成电路装置 | |
CN103314362B (zh) | 用于数据流的基于向量的匹配电路 | |
CN106326156B (zh) | 基于自适应波特率的单端口通信处理电路和方法 | |
CN107733426A (zh) | 一种有迟滞功能的表决器及其设计方法 | |
Gorabal et al. | FPGA Implementation of UART with Single Error Correction and Double Error Detection (UART-SEC-DED) | |
RU2214045C1 (ru) | Устройство для кодирования - декодирования данных | |
CN117155354A (zh) | 一种连续脉冲同步装置、连续脉冲同步方法及芯片 | |
CN105978658A (zh) | 通信系统与方法 | |
JPH0691440B2 (ja) | ランダムパルスパターン発生回路 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
GR01 | Patent grant | ||
GR01 | Patent grant |