CN111788805A - 提供多级分布式判定反馈均衡的方法和系统 - Google Patents
提供多级分布式判定反馈均衡的方法和系统 Download PDFInfo
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Abstract
对两组或更多组节点进行预充电,以将与该两组或更多组节点连接的多输入求和锁存器的差分输出设置于预充电状态,所述两组或更多组节点包括一组数据信号节点和一组DFE校正节点;响应于采样时钟,生成差分数据电压以及总差分DFE校正信号;以及根据所述差分数据电压信号和总差分DFE校正信号的和将所述多输入求和锁存器的差分输出驱动至两种可能输出状态当中的一种来生成数据判定结果,以及随后通过将所述多输入求和锁存器的差分输出在锁存状态下保持由所述采样时钟决定的时间长度来保持所述数据判定结果。
Description
相关申请的交叉引用
本申请要求申请号为15/835,648,申请日为2017年12月8日,名称为“提供多级分布式判定反馈均衡的方法和系统”,发明人为Armin Tajalli的美国非临时申请的权益,并通过引用将其内容整体并入本文,以供所有目的之用。
参考文献
以下在先申请通过引用整体并入本文,以供所有目的之用:
公开号为2011/0268225,申请号为12/784,414,申请日为2010年5月20日,发明人为Harm Cronie和Amin Shokrollahi,名称为“正交差分向量信令”的美国专利申请,下称《Cronie 1》;
申请号为13/842,740,申请日为2013年3月15日,发明人为Brian Holden、AminShokrollahi及Anant Singh,名称为“芯片间通信用向量信令码的时偏耐受方法和系统及增强型检测器”的美国专利申请,下称《Holden 1》;
申请号为15/582,545,申请日为2017年4月28日,发明人为Ali Hormati和RichardSimpson,名称为“采用判定反馈均衡的时钟数据恢复”的美国专利申请,下称《Hormati 1》;
申请号为15/792,599,申请日为2017年10月24日,发明人为Armin Tajalli,名称为“具有分布式判定反馈均衡功能的多处理级数据接收器”的美国专利申请,下称《Tajalli1》。
背景技术
系统内集成电路等电子装置之间的数据通信通常会受到导线、印刷电路迹线或光纤等互连传输介质传输行为的制约。包括衰减、信号反射及频率相关传播特性在内的传输线路效应可导致传输信号的失真,因此需要采取校正措施。
其中,线性电路校正措施包括接收信号的放大,以及例如采用连续时间线性均衡(CTLE)的频域信号校正。
数据相关性均衡为本领域中众所周知的技术。通常,此类时域导向型均衡方法着重于对接收信号的符号间干扰(ISI)影响进行补偿。此类ISI由残留于通信传输介质中的先前传输信号的残余电学效应对当前符号间隔的幅度或时间的影响所致。举例而言,存在一项或多项阻抗异常的传输线路介质可能会导致信号反射。其中,当信号在该介质内传播时,将会在所述一项或多项异常的作用下被部分反射,而反射信号在延迟一定时间后以与未被反射的直接传输信号叠加的形式到达接收器。
发送器端可采用数字校正措施,例如通过有限脉冲响应(FIR)滤波进行预均衡,而接收器端可采用包括前向反馈均衡(FFE)和判定反馈均衡(DFE)在内的方法。
在判定反馈均衡中,先由接收器保持先前接收数据值的历史纪录,然后由传输线路模型进行处理,以推测每一此类历史数据值对当前接收信号的预期影响。所述传输线路模型既可预先算出,也可通过测量导出,还可通过试错方式生成,并且可涵盖一个或多个先前数据间隔的影响。针对所述一个或多个先前数据间隔的影响预测出的校正量统称为DFE校正量,该校正量既可在所得校正信号接收采样前与接收数据信号显式组合,也可通过以该DFE校正量对用于由接收数据采样器或比较器对接收数据信号进行比较的参考电平进行修正的方式隐式组合。
发明内容
当将判定反馈均衡方法应用于高速数据接收器时,需要对与特定先前接收单位间隔的影响相对应的多个DFE校正项进行组合,从而可能变得复杂化。此外,由于此类应用一般利用多个基本上并行的处理级对给定接收数据比特进行流水线式处理或延长其可用检测时间,因此进一步增加了难点。这些难点可包括:难以及时计算DFE校正量,并及时将其分配给各个并行处理级;在施加校正量时会发生检测器放大效果或增益下降等不良副作用。
因此,在本文描述的方法和系统中:对两组或更多组节点进行预充电,以将与该两组或更多组节点连接的锁存器的差分输出设置于预充电状态,所述两组或更多组节点包括(i)一组数据信号节点以及(ii)一组DFE校正节点;响应于采样时钟,通过根据接收差分输入电压信号对所述一组数据信号节点进行放电来生成差分数据电压信号,以及通过根据多个DFE校正因子的和对所述一组DFE校正节点进行放电来生成总差分DFE校正信号;以及根据所述差分数据电压信号和总差分DFE校正信号的和将所述锁存器的差分输出驱动至两种可能输出状态当中的一种来生成数据判定结果,并且随后通过将所述锁存器的差分输出在锁存状态下保持由所述采样时钟决定的时间长度来保持所述数据判定结果。
本文描述的方法和装置能够在高速数据接收器系统中实现DFE校正信息的有效计算和分配,并且在不对检测器增益产生显著影响的情况下实现DFE校正的施加。
附图说明
图1为采用判定反馈均衡以及多个并行处理级的数据接收器的一个信道的一种实施方式。
图2所示为将多个DFE校正量与多个并行处理级进行组合的一种实施方式的进一步细节。
图3为多种输入求和电路的示意图。
图4为一种计算多个DFE校正项以及输出求和校正结果的电路的示意图。
图5为根据一些实施方式的基于NOR的多输入求和锁存器的示意图。
图6所示为采用图3、图4及图5电路的另一实施方式。
图7所示为一个并行处理级的另一实施方式。
图8和图9所示为一个并行处理级的两种其他实施方式。
图10所示为采用本文所述元件的一种系统实施方式。
图11为根据一些实施方式的基于NAND的多输入求和锁存器的示意图。
图12为根据一些实施方式跨两个信令间隔的数据判定的时序图。
图13A和图13B为根据一些实施方式的基于NOR和基于NAND的多输入求和锁存器的框图。
图14为根据一些实施方式通过将基于NOR的多输入求和锁存器与基于NOR的锁存器相连接来延长保持时间的结构框图。
图15为根据一些实施方式的方法流程图。
具体实施方式
近年来,高速通信系统的信令速率已达每秒千兆比特,使得单个传输单位间隔以皮秒计。为了满足如此严苛的时序要求,必须通过最大程度地降低节点电容及消除不必要的处理元件以使得电路延迟最小化。对于可用时间预算,即使是模拟比较器的建立时间等次级电路特性也可能会成为一项重要的占比。
举例而言,现有数据通信接收器的判定反馈均衡系统存储针对先前接收单位间隔的一个或多个检测数据值的历史记录值,并根据这些历史记录值计算出DFE补偿值后,将其施加于接收信号,以便于当前单位间隔的检测。出于说明目的,简而言之,该计算可包括:将每一个先前单位间隔的数据值与预设比例缩放因子相乘;然后将每一个该比例缩放结果(每一者均表示前后相继的先前单位间隔对当前接收信号的潜在影响)相加,以生成表示所有此类先前单位间隔的累计预测影响的复合DFE补偿值。在典型的接收器设计中,这一DFE补偿值与当前接收信号输入组合,以产生更为准确地表示接收数据值的校正信号,该校正信号随后可进行时间采样和幅度采样,以获得检测接收数据值。
本领域技术人员可意识到的是,按照上述方法产生的DFE补偿值仅在先前单位间隔的数据值检测完成后才能完全确定。因此,随着数据速率的增大,必将在某一点上使得生成所述DFE补偿值第一项所需的信息(即先前单位间隔的接收数据值)没有足够的时间应用于下一单位间隔的检测。实际上,在当前实践中使用的最高数据速率下,由于单个数据值所需的检测时间可对应于多个单位间隔的时长,因此这一情形可发生于多个先前单位间隔。因此,针对一个或多个最近单位间隔,各实施方式中一般放弃这一“闭环”DFE法,而是利用“开环”法或“推测”法生成此类最近单位间隔的DFE补偿值的一个或多个元素。
图1所示为针对一个先前接收单位间隔进行推测式DFE的数据接收器的一种实施方式。该例包括接收器前端(110和120)以及针对一个接收数据比特(130,140,150,160)的完整数据路径。在完整的接收器实施方式,所述单个前端一般还与其他数据比特的数据路径共享。在一些实施方式中,既可在多个数据路径之间共享DFE计算子系统170和时钟数据恢复子系统180,也可由特定数据路径独享此两子系统。
在图示非限制性示例中,从通信信道中获取四个接收线路信号,这些信号可代表两对差分信号,或者代表传输以如《Cronie》中所述正交差分向量信令码(ODVS)编码的三个数据比特的一个四线数据流。如《Holden 1》中所述,连续时间线性均衡器110对所述接收线路信号进行频率依赖性放大,而多输入比较器(MIC)120可选通过将放大线路信号组合以解开ODVS编码并获得检测数据信号。在差分接收实施方式中,每一个此类MIC均具有两个有效输入并在功能上作为差分线路接收器,而在单端接收器实施方式中,直接对各个线路信号实施接收操作,免于使用任何MIC功能。
一种此类实施方式的工作传输单位间隔约为35皮秒,所对应的数据速率约为28千兆波特(GBd)。为了支持此类数据速率,所述例示接收器在每一个接收信号数据路径中设置两个并行处理级130和140,每一个该处理级对在交替单位间隔内从一对差分线路或ODVS子信道接收的数据进行检测。在所述数据速率下,该交替工作的并行处理器使得每一个处理级拥有两个单位间隔或70皮秒的时间对每一个接收数据比特进行捕获和检测。
与该通信系统关联的传输线路特性表明,判定反馈均衡(DFE)可能需要跨多达十个接收单位间隔。高数据速率使得现实当中极其难以实现前一接收数据值的关联第一DFE校正项的及时传输。因此,图1示例采用一个“推测”式或“开环”式DFE处理级,其中,各个检测器先分别在前一数据值为“1”或“0”的假设下捕获结果,在确定先前数据值之后,再选择正确的结果加以使用。
每一个并行处理级的操作均相同。对于130,积分采样处理级131和133在采样时钟Clk000的上升沿处同时捕获接收信号幅度与DFE校正量的组合结果。在采用单个推测式DFE元件的该例中,施加至131和133的DFE校正量的区别仅在于其时间上最为接近的一项,分别对应前一数据比特为“1”或“0”假定下的推测校正量。数字复用器135在另一个处理级140检测到所述前一数据比特的值后获得该值,并将合适的推测检测结果132或134引导至处理级130的数据输出138。
并行处理级140的操作相同,区别仅在于在采样时钟Clk180(Clk000的后一接收单位间隔)的上升沿处进行采样,而且复用器145随后利用处理级130所检测的先前数据比特的值将142和144当中的一者选为数据输出148。随后,高速复用器150将交替单位间隔接收值138和148组合成全速接收数据流155。在其他实施方式中,也可将所述接收值仍然保持为并行的低速数据流。
DFE补偿子系统170通过保持接收数据值的历史纪录而为所述两个处理级计算总DFE校正量DFEl,DFE2,DFE3,DFE4。在其他实施方式中,也可针对每一个处理级,或实际上针对每一个采样器,分别计算DFE校正量,但本发明不限于此。其中,所计算的DFE校正量的每一项HN均得自第N个先前接收单位间隔中接收的历史数据值X_N与从传输介质的信号传播模型获得的比例缩放因子KN的乘积。为了计算的简单性,总差分DFE校正信号的各项均视为相对于采样器正常检测阈值的基于零的差分校正量。在计算上,这表示,数据“1”对应于给定比例因子的“+1”乘数,而数据“0”对应于所述相同比例因子的“-1”乘数。
在至少一种实施方式中,所得DFE校正量表示为模拟差分信号,这些模拟差分信号设置为当将该对差分中的两个信号互换时,即使得与数据“1”对应的校正项变成与数据“0”对应的校正项。所述DFE校正量还可本身包含预设、可调或固定偏移或偏置电平或随后与其相组合,在一些实施方式中,这些电平可分别针对特定采样器,以实现对器件差异的补偿。因此,在一种此类实施方式中,举例而言,采样器131和采样器141用于分别对此两电路元件的信号幅度与器件差异进行补偿的所有DFE校正量和预设偏移电平的总和之间可互不相同。
在第一例中,时间T=0表示处理级140的当前接收单位间隔,该接收最终实现对数据值X(T=0)的检测。为了便于描述,下文中将所述数据值简称为X_0。同样地,T=-1表示上述接收时间的前一单位间隔,该单位间隔由130处理,以生成数据值X(T=-1),以下简称X_1(表示单个数据路径实例内依次处理的该时间顺序描述方式不应与描述多个数据路径实例内同时接收的数据比特时常用的“D0,D1,D2……”相混淆。本文所述各例均为在单个接收数据路径内进行的依次操作(即所述常用命名方式中数据比特D0在时间上的依次取值)。
H1~H10表示上述总DFE校正量的不同分量。在以下各例中,接收数据为二进制数据,因此每一个分量均由系数或校正因子K与+1(对于数据“1”)或-1(对于数据“0”)的乘积确定。在实际实施方式中,此类系数取决于网络传播和检测特性,并且可随线路、差分对、ODVS子信道和/或物理采样器实例的不同而不同。
DFE1=(K1×1)+(K2×X_2)+....+(K10×X_10)+C1 式1
DFE2=(K1×-1)+(K2×X_2)+....+(K10×X_10)+C2 式2
DFE3=(K1×1)+(K2×X_2)+....+(K10×X_10)+C3 式3
DFE4=(K1×-1)+(K2×X_2)+....+(K10×X_10)+C4 式4
例如,分别施加至处理级140内的141和143的总校正量DFE3和DFE4之间的区别仅在于与前一单位间隔对应的第一DFE校正项(H1)的符号以及偏置常数C1和C2所含的任何调整或校准差异。作为该第一项的推测式DFE处理的一环,式3和式4的第一校正项含有推测的数据“1”值和数据“0”值,而正确结果由随后根据处理级130在前一单位间隔内获得的实际X_1检测值选择的141或143生成。式1和式2表示130的校正操作,计算方式与上述类似。
图2为采用推测式DFE的一种多级接收器实施方式的更详细示意图。与上例一致,由相同的处理级230和240对在交替接收单位间隔采样的同一接收数据比特进行检测。
对于许多常见的放大器拓扑结构,作为本领域的已知知识,额外添加信号输入将导致信号增益减小,N输入放大器的该减小比例一般为因此,当在单个放大器内直接将九个或更多个DFE校正项与接收信号输入组合时,将大幅减小能够施加给接收信号的增益量。为了最大程度地减轻此类信号增益的降低,由三个不同电路分割所需的求和运算。
其中,每一个非推测式DFE校正项按照上述方式计算248,所输出249的求和结果如式5所示:
Hsum=(K2×D2)+....+(K10×D10) 式5
图4为实施这一计算与第一求和运算的一种电路实施方式示意图,该电路由九个子系统410……490构成,每一个子系统均进行一个校正项的计算处理。图4中仅明确示出第一子系统410和最后一个子系统490,其余各者不言自明。
在410中,当时钟Ck为低电平时,晶体管411和412对差分输出节点∑H+和∑H-进行预充电。当Ck拉高时,晶体管419允许电荷经差分晶体管对417/418排出,其中,电流按照DFE因子K2所确定的方式分为两支,所述DFE因子例如由配置DAC作为差分电流输入。晶体管413,414,415,416用作开关,以在X_2为“1”的第一(正向)构型和X_2为“0”的第二(反向)构型下,将差分对417/418连接至输出节点。如此,输出节点上的所得差分信号即按照式5要求,对应于+1或-1与预设校正因子K2的乘积。
其余八个相同的处理级420……490分别利用因子K3~K10和历史数据值X_3……X_10实施与410类似的计算。由于所有处理级在输出节点∑H+和∑H-上并行运行,因此所得差分输出表示所有九个计算项的求和结果。
在图2中,式5计算所需的DFE校正因子(K因子)由九个数模转换器(DAC)211~219生成,这些DAC统称220。在一种实施方式中,220中的每一个DAC均用于输出与DFE总和计算电路248所使用的特定校正因子KN相对应的差分模拟电压。
所得的DFE总和校正量249作为图中示为采样器242和244的第二求和电路的输入。图3电路330所示为一种合适的采样器实施方式,其中,差分输入Vdata和∑H在采样时钟Ck的上升沿处进行求和。
采样器242和244捕获的结果表示在先前单位间隔数据值为“1”(对应242)或“0”(对应244)这一假定下的推测结果。因此,输入至这些采样器的信号必须以第一DFE校正项H1的合适的不同值进行抵消。
为了生成此类值,由图2中示为放大器241和243的第三求和电路对接收输入信号125进行处理,每一个所述放大器均用于添加推测式DFE校正因子K1,此两校正因子的区别仅在于所得校正量的符号不同。其中,DAC 250用于提供校正因子255。图3所示的电路310为一种适合用于图2中241和243的合适实施方式示意图。所述两个电路实例的区别仅在于控制信号X_0的设置方式:在241中,X_0与逻辑“1”硬连线;在243中,X_0与逻辑“0”硬连线。310的不同输入元件的信号增益可通过调节不同信号路径(如差分对313/314与差分对320/321)对求和结果的电流贡献的方式进行改动。在一种实施方式中,所述调节通过按比例缩放晶体管相对尺寸的方式实现。在另一实施方式中,通过将多个相同晶体管元件实例并联的方式实现上述调节。采用多个相同晶体管元件实例的此类实施方式如图10所示,其中,通过将输入信号Vin提供给六个相互并联的相同电流模式输出采样器而使得输入信号Vin的增益为6,而推测式DFE分量+H1和-H1提供给三个相互并联的相同电流模式输出采样器,而且已知的DFE因子X2H2……X10H10当中的每一者均与相应的相同电流模式输出采样器连接。由于每一个相同电流模式输出采样器均提供相等的电流量,因此相互并联的多个此类采样器能够在公共输出节点上提供电流模式求和结果。
如上所述,推测式检测结果通过以由前一单位间隔X_1内获得的数据值控制的复用器245选择有效采样结果的方式进行解析。在一些实施方式中,可通过加入复用器270而在数据历史纪录单元210中生成全速串行流。在替代实施方式中,也可直接对来自不同处理级的数据流进行操作,无需通过复用操作将其转为单个流。
在一种实施方式中,处理级230在前一单位间隔内检测到的数据值X_1直接从处理级230中获取,以用于最大程度减小电路传播延迟,而非获取自数据历史纪录单元210。同样地,处理级240在前一单位间隔内检测到的数据值X_2也可在该处理级内供其所用,以及时生成H2 DFE校正项。作为一种可选的流水线式优化方案,锁存器246图示为捕获并保持输出数据值,以用于供248进行H2的计算,从而增大生成DFE总和校正量249时的时间裕量。在一些实施方式中,还将类似的流水线式锁存器用于增大对复用器245的选择操作进行控制的X_1数据值的时间裕量。
在下文中,出于描述目的,信号VA+/VA-可对应于至少根据接收差分输入电压信号Vin(在图3中示为Vdata+/Vdata-)生成的差分数据电压信号,而VB+/VB-对应于根据DFE校正因子H2……H10的求和结果(在图3和图4中示为∑H+和∑H-)形成的总差分DFE校正信号。一些实施方式可不使用推测式DFE项+H1和-H1,而替代实施方式可在下述各种设置方式中使用推测式DFE。
在一些实施方式中,如图6所示,一种装置包括离散时间积分处理级。在图6中,该离散时间积分处理级包括积分器610,620,以及可采取积分器形式的DFE求和电路248。该离散时间积分处理级包括两组或更多组节点,该两组或更多组节点至少包括一组用于保持电压VA+/-的数据信号节点以及一组用于保持电压VB+/-的DFE校正节点。该离散时间积分处理级用于:对所述两组或更多组节点进行预充电,以将与该两组或更多组节点连接的多输入求和锁存器630的差分输出设置为预充电状态;以及响应于采样时钟,通过根据接收差分输入电压信号对所述一组数据信号节点进行放电而生成差分数据电压信号VA+/-,并通过根据多个DFE校正因子的求和结果对所述一组DFE校正节点进行放电而生成总差分DFE校正信号VB+/-。在图6中,多输入求和锁存器630可通过根据所述差分数据电压信号和总差分DFE校正信号的求和结果将该多输入求和锁存器的差分输出驱动至两个可能输出状态当中的一者而生成数据判定结果,该多输入求和锁存器设置为随后通过将该多输入求和锁存器的差分输出在锁存状态下保持由所述采样时钟决定的时间长度来保持所述数据判定结果。
在一些实施方式中,如图6所示,所述离散时间积分处理级还用于生成一对差分推测式DFE项K1+和K1-。在此类实施方式中,所述离散积分处理级可通过将所述一对差分推测式DFE项当中的每一个差分推测式DFE项分别施加至所述差分数据电压信号和总差分DFE校正信号的求和结果来生成一对推测式数据判定结果。在图6中,所述推测项施加至所述接收差分输入电压信号,并且由两个多输入求和锁存器630和640接收所述推测式数据判定结果。在此类实施方式中,所述装置进一步包括复用器650,该复用器用于在先前数据判定完成后,将所述一对推测式数据判定结果当中的一者选为数据判定结果。在替代实施方式中,如图9所示,所述推测式DFE项可施加至所述总DFE校正信号。
在一些实施方式中,第二锁存器635(在推测式DFE实施方式中,还有锁存器645)设置为接收所述数据判定结果,并将该数据判定结果提供为针对整个信令间隔的数据判定输出。
在一些实施方式中,由一个或多个CMOS反相器对所述差分数据电压信号和总差分DFE校正信号进行缓冲。
在一些实施方式中,所述离散时间积分处理级包括含所述一组数据信号节点的第一放大处理级,以及含所述一组DFE校正节点的第二放大处理级。在图6中,所述第一放大处理级可包括积分器610和620,而所述第二放大处理级包括DFE求和电路248。在此类实施方式中,所述第一放大处理级可包括相互并联的多个差分晶体管对,并且用于接收所述接收差分输入电压信号,并通过所述相互并联的多个差分晶体管对相应生成多条电流,其中,所施加的增益表示所述一组数据信号节点的放电速率。图10所示为一种此类设置方式,其中,与VGA2连接的每一个元件均为与图3中元件310类似的电路,而且并不施加所述推测式DFE项(这些推测式DFE项在图10中示为+/-H1)。
图6所示为在功能上等同于图2中处理级240的一种替代实施方式,该实施方式含有多输入求和锁存器630和640。在一些实施方式中,所述多输入求和锁存器可采取与分别如图13A和图13B示意图所示的基于NOR的SR锁存器或基于NAND的SR锁存器类似的形式。所述基于NOR的多输入求和锁存器和基于NAND的多输入求和锁存器的晶体管示意图分别示于图5和图11。如图5所示,所述基于NOR的多输入求和锁存器500形成差分数据电压信号VA+/VA-和总差分DFE校正信号VB+/VB-的输入求和结果,而且同时还用作差分结果Q+,Q-的限幅器和输出锁存器。如图5所示,所述求和结果通过将位于所述多输入求和锁存器一侧的正极性输入端VA+和VB+并联且将位于该多输入求和锁存器另一侧的负极性输入端VA-和VB-并联的方式形成。下表I和下表II分别给出基于NOR的多输入求和锁存器的真值表和基于NAND的多输入求和锁存器的真值表:
VA<sub>+</sub>+VB<sub>+</sub> | VA<sub>-</sub>+VB<sub>-</sub> | Q+ | Q- |
1 | 1 | 0(预充电状态) | 0(预充电状态) |
1 | 0 | 0 | 1 |
0 | 1 | 1 | 0 |
0 | 0 | 锁存 | 锁存 |
表I:基于NOR的多输入求和锁存器
VA<sub>+</sub>+VB<sub>+</sub> | VA<sub>-</sub>+VB<sub>-</sub> | Q+ | Q- |
1 | 1 | 锁存 | 锁存 |
1 | 0 | 0 | 1 |
0 | 1 | 1 | 0 |
0 | 0 | 1(预充电状态) | 1(预充电状态) |
表II:基于NAND的多输入求和锁存器
在图5的基于NOR的多输入求和锁存器中,由于保持VA+/-和VB+/-的所述各组节点预充电,因此(VA++VB+)和(VA_+VB-)的值最初为“1”,从而将差分输出Q+/Q-保持于状态“00”。虽然所述基于NOR和基于NAND的多输入求和锁存器的预充电状态和锁存状态彼此相反,但是数据判定状态“01”和“10”的输出完全一致。虽然上表中存在四种可能状态,但是需要注意的是,判定状态“01”和“10”的这两种输入组合方式对应于下降速率更快的求和结果。这是因为积分器610,620以及248中的积分器能够有效实现幅度至时间的转换,其中,输入至所述离散时间积分器的信号幅度转换为放电速率。在此类情形中,如图3和图12时序图所示,放电速率与输入信号幅度成正比,因此输入信号的幅度越高,相应输出节点的放电速度越快。随后,所述多输入求和锁存器先将所述差分数据电压信号和总差分DFE校正信号(此两信号为经时间转换处理后的信号)相组合,然后锁存至由(VA++VB+)和(VA-+VB-)极性求和结果的放电速率变化决定的数据判定结果。
图12为采用如图5所示基于NOR的多输入求和锁存器的电路的前后相继两个单位间隔的时序图。如图所示,保持VA+/-的一组数据信号节点和保持VB+/-的一组DFE校正信号节点处于预充电状态,而且基于NOR的多输入求和锁存器630的输出Q+/Q-也保持于预充电状态“00”。响应于采样时钟的上升沿,相应各组节点根据接收差分输入电压Vin+/Vin-以及所述多个DFE校正因子H_2……H_10的求和结果放电,从而生成差分数据电压信号VA+/VA和总差分DFE校正信号VB+/VB-。随后,通过根据所述差分数据电压信号和总差分DFE校正信号的求和结果,将多输入求和锁存器630的差分输出Q+/Q-驱动至两个可能状态当中的一者,生成数据判定结果。具体而言,当每组节点开始放电且这些节点上的电压随之开始下降时,Q+/Q-值因与VA+/-和VB+/-连接的NMOS晶体管开始截止且PMOS晶体管开始导通而开始增大。在图12的第一单位间隔内,求和结果VA++VB+的下降速度快于求和结果VA-+VB-的下降速度,因此Q+的增大速度开始快于Q-的增大速度。在达到某一阈值时,Q+的反馈使得Q-随后开始减小,从而形成Q+=“1”且Q-=“0”的数据判定结果。在所述多输入求和锁存器的输入状态变为“00”之前,由于所述离散时间积分器的各组节点仍然放电,因此(VA++VB+)和(VA-+VB-)的值继续下降,从而如上表I所示,使得Q+/Q-的差分输出状态保持于“10”,直至随后因采样时钟出现下降沿而使得各组节点针对下一采样周期进行预充电。响应于各组节点的预充电,差分输出Q+/Q-保持于预充电状态。图12中的第二单位间隔与第一单位间隔类似,但其中VA-+VB-求和结果的放电速度快于VA++VB+求和结果放电速度。
在一些实施方式中,如图所示,多输入求和锁存器630和640的下游设置交叉耦合的基于NOR的现有技术置位/复位锁存器635和645,以延长各结果的保持时间。图14所示为一种例示设置方式。如图14所示,基于NOR的多输入求和锁存器630的输出交叉耦合,并且提供给基于NOR的锁存器635。如以上结合图12所述,当对所述基于NOR的多输入求和锁存器的输入进行预充电时,将使得差分输出Q+/Q-进入预充电状态“00”,而该状态正是如表I所示基于NOR的多输入求和锁存器的“锁存”状态的输入条件。通过将所述差分输出Q+/Q-作为基于NOR的锁存器635的输入,可在整个时钟周期内保持所述数据判定结果。如此,如图12所示,基于NOR的锁存器635的输出Qout+/Qout-将仅根据多输入求和锁存器630的数据判定结果变化,并且随后一直保持至采样时钟的下一个上升沿。
在一些实施方式中,多输入求和锁存器630和640的每个一差分输入端还插入未缓冲的CMOS反相器(未图示)。在此类实施方式中,由于使用预充电状态“00”,因此可使用图11所示的基于NAND的多输入求和锁存器。当反相输入达到状态“11”时,即可实现中间数据判定结果的保持。
在替代实施方式中,可将图3和图4的MOSFET结构逆转,并且可利用电流源对一对预放电节点进行充电。在此类实施方式中,先将所述节点放电至状态“00”,然后此两节点可响应于采样时钟在电流源的作用下开始充电,直至达到状态“11”。在此类实施方式中,所述差分数据电压和总DFE校正信号可直接施加至所述基于NAND的多输入求和锁存器,或者与上述类似,通过CMOS反相器施加至基于NOR的多输入求和锁存器。
需要注意的是,可以使用各种结构的离散积分器310和330,并可通过不同结构的CMOS反相器将其与各种类型的多输入求和锁存器连接。例如,在图6中,可在多输入求和锁存器630和640的输入端纳入CMOS反相器(未图示)。在此类实施方式中,由于输入条件与上表I和上表II给定的预充电状态和锁存状态相逆,因此所述多输入求和锁存器也可为基于NAND的多输入求和锁存器。这一设计的优点在于能够实现所述多输入求和锁存器与离散时间积分器310和320之间的系统隔离。需要注意的是,所述CMOS反相器可引入额外增益,该额外增益可例如通过调节用于生成VA+/-和VB+/-的离散时间积分器内的放电速度而得到补偿。
虽然上述示例并未描述对推测式DFE项H_l+/-的使用,但是需要注意的是,这些推测式DFE项可以纳入图3以及图6至图10当中任何附图所示的结构中。也就是说,所述推测式DFE项可引入各个不同处理级中,而所述多输入求和锁存器和任何下游锁存器件的操作仍保持不变。例如,如图8所示,所述推测式DFE项可施加至接收差分输入电压Vin上,并可作为VA+/VA-的一部分;或者,所述推测式DFE项也可通过施加至历史DFE校正因子而纳入VB+/VB-中,正如图9所示结构一样。
所述钟控采样器的功能由输入求和器610和620执行,其与前例一致,可采用图3的电路310。与X_1数据值对应的“开环式”或“推测式”校正所使用的DFE校正因子K1图示为分别从DAC 660获得且作为610输入的正(即对应于X_1的推测值为“1”)因子与从DAC661获得且作为640输入的负(即对应于X_1的推测值为“0”)因子。在其他实施方式中,也可如上所述,以单个DAC提供上述两种推测选项的K1因子。
图7所示为上述实施方式的整个处理过程。其中,每一个DFE校正因子HN(在该例中,N=1……10)均通过将校正因子KN与相应历史数据值X_N相乘的方式获得。因此,如图所示,以DAC 721为例,该DAC用于生成校正因子K2,并通过将其与历史数据值X_2相乘711而生成采样器730的DFE校正项H2。如图所示,采样器730和760分别用于针对先前单位间隔数据X_1为“1”(对应于730)和为“0”(对应于760)这两种推测式假定情况进行检测。为了普遍性起见,图中将730和760示为分别生成仅H1校正项的假定值存在区别的输入校正项。如图所示,来自DAC 721~729的值可在730和760之间共享,但是每一采个样器730和760均分别使用其自身的乘数。如图所示,采样器730含有一组乘数710~719,而采样器760含有乘数750~759。如图4所示,每一个乘数均可以为多个晶体管的一种设置方式。与前例一致,图中示为以复用器770进行有效推测检测值的选择。
图8和图9所示为与图7实施方式类似的两种其他实施方式,此两实施方式的求和以及积分采样操作有所不同,以便突显所述实施方式的不同操作方面。
在图8中,先对所有非推测式DFE校正项求和820,然后将所得总校正量与输入信号Vin以及多输入求和锁存器840内的推测式DFE校正量810的总和组合。此外,还在总校正量820与Vin以及多输入求和锁存器870内的互补推测式DFE校正量830的总和之间进行类似的组合操作。多输入求和锁存器840和870执行以下多项功能:分别进行正负差分输入信号的求和(如Vin加推测式DFE校正量加DFE总和校正量);获得两个总和当中更负的一者。随后,以现有锁存器850和880锁存840和870的差分输出。
如上所述,复用器860根据实际接收的先前数据值,从所述两个推测结果当中选择一个。通过在推测式采样器之间共享非推测式校正量的总和,可以降低电路复杂度,使采样器810和830保持较少的输入,以及向这些输入施加较大的增益。在一种实施方式中,810和830向Vin提供6倍增益,并向推测式H1项提供3倍增益。
所有图示积分保持采样器均采用与上述相同的基本设计。在一种实施方式中,810和830沿用图3中330的设计,而820沿用图4设计。多输入求和锁存器实施方式840和870如图5所示,而下游锁存器850和880如图14结构所示,采用现有技术的交叉耦合NOR门置位/复位锁存器。如上所述,作为替代方案,可在所述两个输入求和锁存器的各个差分输入端插入未缓冲的CMOS反相器,相应地,可以图11所示替代电路进行电路替代。
图9所示为图7和图8设计的另一种变型。在图9中,所有的推测式和非推测式DFE校正项均分别求和,其中,920用于含X_1=“1”这一推测项的和,930用于含X_1=“0”这一推测项的和。这些加总后的校正量和放大后的输入信号910由两个输入求和锁存器940(对应推测值“1”)和970(对应推测值“0”)组合,以生成阈值比较结果。这些结果随后由950和980锁存,以供复用器960选择正确的推测结果。如此,由于积分采样处理级910仅具有一个输入,因此可提高具有更大的增益。在一种实施方式中,该处理级通过在Vin中采用九个并联差分晶体管对而实现9倍的Vin增益。在另一实施方式中,通过类似方式,实现6倍的推测式DFE校正项增益。
与上例一致,可在所述两个输入求和锁存器的各个差分输入端插入未缓冲的CMOS反相器,相应地,可以图11所示替代电路1100代替图5电路。
图7、图8、图9实施方式具有仅需对所有输入项基本同时实施单个钟控采样操作的共同优点。对于信号之间的时偏导致问题的应用中,这一点具有重要意义。
图10所示为采用上述元件的系统实施方式。其中,用于各信号路径之间增益调节的并联差分对元件被明确示出,而例如在图8中以元件810,820,830标示的求和操作以数据处理流程表示形式示出,而且每一个独立的求和操作均示为一条求和总线。每一个该求和操作均包括相同数目(在该非限制性示例中为九)的差分对元件,以通过彼此一致的负载条件减小不同求和结果之间的时偏。由于双输入求和锁存器(例如,如图5所示)的结果由求和结果(A+与B+之和)以及(A-与B-之和)当中最先落于另一者之下的一者确定,因此减小其输入时偏较为有利。
图15为根据一些实施方式的方法1500的流程图。如图所示,方法1500包括:对两组或更多组节点进行预充电1502,以将与该两组或更多组节点连接的多输入求和锁存器的差分输出设置于预充电状态,所述两组或更多组节点包括(i)一组数据信号节点以及(ii)一组DFE校正节点。在步骤1504中,响应于采样时钟,通过根据接收差分输入电压信号对所述一组数据信号节点进行放电而生成差分数据电压信号,以及通过根据多个DFE校正因子的求和结果对所述一组DFE校正节点进行放电而生成总差分DFE校正信号。在1506中,根据所述差分数据电压信号和总差分DFE校正信号的求和结果,将所述多输入求和锁存器的差分输出驱动至两种可能输出状态当中的一种,以生成数据判定结果。随后,通过将所述多输入求和锁存器的差分输出在锁存状态下保持由所述采样时钟决定的时间长度来保持1508所述数据判定结果。
在一些实施方式中,该方法还包括:生成一对差分推测式DFE项:+H1和-H1。在此类实施方式中,所述一对差分推测式DFE项当中的每一个差分推测式DFE项均可分别施加至所述差分数据电压信号和总差分DFE校正信号的求和结果,以生成一对推测式数据判定结果。在此类实施方式中,生成所述数据判定结果包括:响应于先前数据判定,选择所述一对推测式数据判定结果当中的一者。
在一些实施方式中,所述差分推测式DFE项通过所述差分数据电压信号施加至所述求和结果,而在替代实施方式中,也可通过所述差分DFE校正信号将所述差分推测式DFE项施加至所述求和结果。图6至图10所示为用于施加推测式DFE项的各种结构。
在一些实施方式中,该方法还包括:将所述数据判定结果提供给第二锁存器(如锁存器635/645),该第二锁存器用于将所述数据判定结果提供为整个信令间隔的输出。在一些实施方式中,以一个或多个CMOS反相器,对所述差分数据电压信号和总差分DFE校正信号进行缓冲处理。
在一些实施方式中,所述一组数据信号节点与第一放大处理级241/243的输出相连,其中所述一组DFE校正节点与第二放大处理级248相连。在此类实施方式中,该方法还包括:通过以相互并联的多个差分晶体管对并行生成多条电流将增益经所述第一放大处理级施加至所述接收差分输入电压信号施加,其中,所述多个差分晶体管对当中的每一差分晶体管对均接收所述差分输入电压信号,所施加的增益表示所述一组数据信号节点的放电速率。如图10所示,所述第一放大处理级可包括六个相互并联的相同电流模式输出采样器,以向差分输入电压信号Vin提供六倍增益。在此类实施方式中,每一个相同电流模式输出采样器均可包括一个晶体管差分对,该晶体管差分对接收所述差分输入电压信号,并生成通过提供给公共节点而进行模拟求和操作的电流。
在一些实施方式中,所述差分数据电压信号和总差分DFE校正信号的求和结果通过将所述差分电压信号和总差分DFE校正信号的同极性项提供给相互并联的相应晶体管对中的相应晶体管的方式生成,每一晶体管对内的晶体管均提供相应电流,这些电流经连接该晶体管对内的晶体管的公共节点相加。如图5所示,通过将所述差分数据电压信号和总差分DFE校正信号连接至按照同极性项分组的并联晶体管,使得VA+与VB+相加,而VA-与VB-相加。
为了描述方便性,以上示例建议通过DAC实现所述控制信号或电平的设置或调节。DAC可采用R-2R电阻梯、一元电阻链、二进制加权电阻或电容求和法或者本领域已知的其他方法。其他实施方式也可采用本领域已知的其他方法生成包括可设置电流源、可调节阻性或容性信号输出限制条件在内的可设置或可调节输出信号电平,并选择性地启用若干并联驱动元件,以分别递增式地对输出信号电平施加作用。
为了清楚地说明上述实施方式的所有元件,以上描述了分别执行单个推测式DFE处理级的两个基本上并行的处理级。然而,本发明不限于此,所述元件还可同等应用于采用更多或更少并行处理级的实施方式。同样地,本发明不限于单个推测式DFE处理级,所述元件还可同等应用于采用额外推测式DFE处理级或根本不采用推测式或开环式DFE的实施方式。
Claims (20)
1.一种方法,其特征在于,包括:
通过对与多输入求和锁存器连接的两组或更多组节点进行预充电,将所述多输入求和锁存器的差分输出设置于预充电状态,所述两组或更多组节点包括(i)一组数据信号节点,以及(ii)一组判定反馈均衡校正节点;
响应于采样时钟,通过根据所接收的差分输入电压信号对所述一组数据信号节点进行放电来生成差分数据电压信号,以及通过根据多个判定反馈均衡校正因子的和对所述一组判定反馈均衡校正节点进行放电来生成总差分判定反馈均衡校正信号;以及
根据所述差分数据电压信号与所述总差分判定反馈均衡校正信号的和,将所述多输入求和锁存器的所述差分输出驱动至两种可能输出状态当中的一种来生成数据判定结果,以及随后通过将所述多输入求和锁存器的所述差分输出在锁存状态下保持由所述采样时钟决定的时间长度来保持所述数据判定结果。
2.如权利要求1所述的方法,其特征在于,还包括生成一对差分推测式判定反馈均衡项。
3.如权利要求2所述的方法,其特征在于,所述一对差分推测式判定反馈均衡项当中的每一个差分推测式判定反馈均衡项分别施加至所述差分数据电压信号与所述总差分判定反馈均衡校正信号的所述和,以生成一对推测式数据判定结果,其中,生成所述数据判定结果包括:响应于先前数据判定的完成,选择所述一对推测式数据判定结果当中的一者。
4.如权利要求3所述的方法,其特征在于,所述每一个差分推测式判定反馈均衡项经所述差分数据电压信号施加至所述差分数据电压信号与所述总差分判定反馈均衡校正信号的所述和。
5.权利要求3所述的方法,其特征在于,所述每一个差分推测式判定反馈均衡项经所述差分判定反馈均衡校正信号施加至所述差分数据电压信号与所述总差分判定反馈均衡校正信号的所述和。
6.如权利要求1所述的方法,其特征在于,还包括将所述数据判定结果提供至输出锁存器,其中所述输出锁存器将所述数据判定结果作为整个信令间隔的输出。
7.权利要求1所述的方法,其特征在于,通过一个或多个互补金属氧化物半导体反相器,对所述差分数据电压信号以及所述总差分判定反馈均衡校正信号进行缓冲。
8.如权利要求1所述的方法,其特征在于,所述一组数据信号节点连接至第一放大处理级的输出,以及所述一组判定反馈均衡校正节点连接至第二放大处理级。
9.如权利要求8所述的方法,其特征在于,还包括通过相互并联的多个差分晶体管对并行生成多条电流以将增益经所述第一放大处理级施加至所接收的差分输入电压信号,所述多个差分晶体管对当中的每一差分晶体管对均接收所述差分输入电压信号,其中所施加的增益表示所述一组数据信号节点的放电速率。
10.如权利要求1所述的方法,其特征在于,通过将所述差分电压信号与所述总差分判定反馈均衡校正信号的同极性项提供至相互并联的各个晶体管对中的相应的晶体管来生成所述差分数据电压信号与所述总差分判定反馈均衡校正信号的所述和,其中每一晶体管对内的所述晶体管均提供相应的电流,所述电流通过连接所述晶体管对中的所述晶体管的公共节点进行相加。
11.一种装置,其特征在于,包括:
具有两组或更多组节点的离散时间积分处理级,所述两组或更多组节点包括(i)一组数据信号节点,以及(ii)一组判定反馈均衡校正节点,其中,所述离散时间积分处理级用于:
通过对与多输入求和锁存器连接的所述两组或更多组节点进行预充电而将所述多输入求和锁存器的差分输出设置于预充电状态;以及
响应于采样时钟,通过根据所接收的差分输入电压信号对所述一组数据信号节点进行放电来生成差分数据电压信号,以及通过根据多个判定反馈均衡校正因子的和对所述一组判定反馈均衡校正节点进行放电来生成总差分判定反馈均衡校正信号,
其中,所述多输入求和锁存器用于根据所述差分数据电压信号与所述总差分判定反馈均衡校正信号的和,将所述多输入求和锁存器的所述差分输出驱动至两种可能输出状态当中的一种来生成数据判定结果,所述多输入求和锁存器还用于随后通过将所述多输入求和锁存器的所述差分输出在锁存状态下保持由所述采样时钟决定的时间长度来保持所述数据判定结果。
12.如权利要求11所述的装置,其特征在于,所述离散时间积分处理级还用于生成一对差分推测式判定反馈均衡项。
13.如权利要求12所述的装置,其特征在于,所述离散时间积分处理级用于通过将所述一对差分推测式判定反馈均衡项当中的每一个差分推测式判定反馈均衡项分别施加至所述差分数据电压信号与所述总差分判定反馈均衡校正信号的所述和来生成一对推测式数据判定结果;
其中,所述装置包括第二多输入求和锁存器,所述多输入求和锁存器与所述第二多输入求和锁存器用于生成所述一对推测式数据判定结果中的相应的推测式数据判定结果;
其中,所述装置还包括复用器,所述复用器用于响应于先前数据判定的完成,选择所述一对推测式数据判定结果当中的一者作为所述数据判定结果。
14.如权利要求13所述的装置,其特征在于,所述每一个差分推测式判定反馈均衡项经所述差分数据电压信号施加至所述差分数据电压信号与所述总差分判定反馈均衡校正信号的所述和。
15.如权利要求13所述的装置,其特征在于,所述每一个差分推测式判定反馈均衡项经所述差分判定反馈均衡校正信号施加至所述差分数据电压信号与所述总差分判定反馈均衡校正信号的所述和。
16.如权利要求11所述的装置,其特征在于,还包括与所述多输入求和锁存器的输出连接的输出锁存器,其中,所述输出锁存器用于从所述多输入求和锁存器接收所述数据判定结果,以及将所述数据判定结果作为整个信令间隔的数据判定输出。
17.如权利要求11所述的装置,其特征在于,还包括用于对所述差分数据电压信号与所述总差分判定反馈均衡校正信号进行缓冲的一个或多个互补金属氧化物半导体反相器。
18.如权利要求11所述的装置,其特征在于,所述离散时间积分处理级包括具有所述一组数据信号节点的第一放大处理级以及具有所述一组判定反馈均衡校正节点的第二放大处理级。
19.如权利要求18所述的装置,其特征在于,所述第一放大处理级包括相互并联的多个差分晶体管对,所述差分晶体管对用于接收所接收的差分输入电压信号,并且响应地通过相互并联的所述多个差分晶体管对并行生成多条电流,其中所施加的增益表示所述一组数据信号节点的放电速率。
20.如权利要求11所述的装置,其特征在于,所述多输入求和锁存器用于通过将所述差分电压信号与所述总差分判定反馈均衡校正信号的同极性项提供至相互并联的各个晶体管对中的相应的晶体管来对所述差分数据电压信号与所述总差分判定反馈均衡校正信号进行求和,其中每一晶体管对中的所述晶体管均提供相应的电流,所述电流通过连接所述晶体管对中的所述晶体管的公共节点进行相加。
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